A first impurity region is formed by ion implantation through a first opening formed in a mask layer. By depositing a spacer layer on an etching stop layer on which the mask layer has been provided, a mask portion having the mask layer and the spacer layer is formed. By anisotropically etching the spacer layer, a second opening surrounded by a second sidewall is formed in the mask portion. A second impurity region is formed by ion implantation through the second opening. An angle of the second sidewall with respect to a surface is 90°±10° across a height as great as a second depth. Thus, accuracy in extension of an impurity region can be enhanced.

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.

Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.

Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer.

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

An object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H2O, may be eliminated. An oxide insulating layer containing a large number of defects such as dangling bonds may be formed in contact with the oxide semiconductor layer, such that the impurity diffuses into the oxide insulating layer and the impurity concentration in the oxide semiconductor layer is reduced. The oxide semiconductor layer or the oxide insulating layer in contact with the oxide semiconductor layer may be formed in a deposition chamber which is evacuated with use of a cryopump whereby the impurity concentration is reduced.

A method for producing a Ga-containing group III nitride semiconductor having reduced threading dislocation is disclosed. A buffer layer in a polycrystal, amorphous or polycrystal/amorphous mixed state, comprising AlGaN is formed on a substrate. The substrate having the buffer layer formed thereon is heat-treated at a temperature higher than a temperature at which a single crystal of a Ga-containing group III nitride semiconductor grows on the buffer layer and at a temperature that the Ga-containing group III nitride semiconductor does not grow, to reduce crystal nucleus density of the buffer layer as compared with the density before the heat treatment. After the heat treatment, the temperature of the substrate is decreased to a temperature that the Ga-containing group III nitride semiconductor grows, the temperature is maintained, and the Ga-containing group III nitride semiconductor is grown on the buffer layer.

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.

A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.

A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.

In a semiconductor device, where, with respect to a parasitic resistor in a current mirror circuit, a compensation resistor for compensating the parasitic resistor is provided in the current mirror circuit, the current mirror circuit includes at least two thin film transistors. The thin film transistors each have an island-shaped semiconductor film having a channel formation region and source or drain regions, a gate insulating film, a gate electrode, and source or drain electrodes, and the compensation resistor compensates the parasitic resistor of any one of the gate electrode, the source electrode, and the drain electrode. In addition, each compensation resistor has a conductive layer containing the same material as the gate electrode, the source or drain electrodes, or the source or drain regions.

Provided is a liquid crystal display including, on an insulation substrate having a polygonal display area and a peripheral area surrounding the display area a first signal line, a second signal line crossing the first signal line, a plurality of switching elements connected to the first signal line and the second signal line and disposed in the display area, a plurality of pixel electrodes each connected to the switching element and disposed in the display area, and a shielding conductor disposed in the peripheral area and extending along at least one side of the polygonal display area.

In a semiconductor device, a first interlayer insulating layer made of an inorganic material and formed on inverse stagger type TFTs, a second interlayer insulating layer made of an organic material and formed on the first interlayer insulating layer, and a pixel electrode formed in contact with the second interlayer insulating layer are disposed on a substrate, and an input terminal portion that is electrically connected to a wiring of another substrate is provided on an end portion of the substrate. The input terminal portion includes a first layer made of the same material as that of the gate electrode and a second layer made of the same material as that of the pixel electrode. With this structure, the number of photomasks used in the photolithography method can be reduced to 5.

The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.

The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.

According to one embodiment, a first gene encodes a reporter protein. The first gene is disposed at the downstream of the gene promoter. A second gene is disposed at the downstream of the gene promoter and encodes a replication origin-binding protein. An internal ribosome entry site is disposed between the first gene and the second gene. The transcription termination signal sequence encodes a signal for terminating the transcription of the first gene and the second gene. A replication origin sequence is recognized by the replication origin-binding protein.

Methods and devices for separating fluid-suspended plant somatic embryos and embryogenic tissue based on differences in their fluid drag properties are disclosed. Deposition method and device for depositing plant somatic embryos into embryo receiver comprising growth substrate by means of a fluid jet is disclosed. An automated system for processing plant somatic embryos from the bioreactor to the growth substrate is also disclosed.

The invention provides an improved design for the construction of extensible nucleic acid-based, ligand-controlled regulatory systems, and the nucleic acid regulatory systems resulting therefrom. The invention contemplates improving the design of the switches (ligand-controlled regulatory systems) through the design of an information transmission domain (ITD). The improved ITD eliminates free-floating ends of the switching and the competing strands, and localizes competitive hybridization events to a contiguous strand of competing and switching strands in a strand-displacement mechanism-based switch, thereby improving the kinetics of strand-displacement. The improved regulatory systems have many uses in various biological systems, including gene expression control or ligand-concentration sensing.

Described herein are techniques for assembling a polynucleotide encoding a transcription activator-like effector nucleases (TALEN). The techniques ligate and digest necessary modules for a TALEN assembly in one reactor or system. Methods and Kits for generating a TALEN are also described.

The invention relates to genes coding for TCP family transcription factors and having a biological role in the development of axillary buds and branch growth. Furthermore, the invention relates to the promoters of the transcription of said genes, to the genetic constructs containing same and to the uses thereof, including the use of agents that modulate the expression of these genes in order to modify plant architecture.

The invention relates to compounds that specifically bind a T1R1/T1R3 or T1R2/T1R3 receptor or fragments or sub-units thereof. The present invention also relates to the use of hetero-oligomeric and chimeric taste receptors comprising T1R1/T1R3 and T1R2/T1R3 in assays to identify compounds that respectively respond to umami taste stimuli and sweet taste stimuli. Further, the invention relates to the constitutive of cell lines that stably or transiently co-express a combination of T1R1 and T1R3; or T1R2 and T1R3; under constitutive or inducible conditions. The use of these cells lines in cell-based assays to identify umami and sweet taste modulatory compounds is also provided, particularly high throughput screening assays that detect receptor activity by use of fluorometric imaging.

This invention relates to the field of biotechnology or genetic engineering. Specifically, this invention relates to the field of gene expression. More specifically, this invention relates to novel substitution mutant receptors and their use in a nuclear receptor-based inducible gene expression system and methods of modulating the expression of a gene in a host cell for applications such as gene therapy, large scale production of proteins and antibodies, cell-based high throughput screening assays, functional genomics and regulation of traits in transgenic organisms.

A cushion element for a vehicle seat or headrest comprises a non-woven layer and a fiber composite material. An insert material is arranged between the non-woven layer and the fiber composite material, and has different compression properties than the fiber composite material. The fiber composite material forms together with the insert material and the non-woven layer a one-piece material composite.

According to an example embodiment, an apparatus is provided that produces a small-step switchable capacitor, which can have steps that are smaller in value than the smallest capacitor used in the system. In one embodiment, an input signal is connected to a switchable capacitor system that includes at least one and/or a plurality of small-step, switchable capacitors. In an example embodiment, a capacitor system may be provided that includes a first capacitance block coupled in series with a second capacitance block. In an example embodiment, the second capacitance block may include one or more switchable capacitors to provide a step in capacitance for the capacitor system between a first setting and a second setting using the one or more switchable capacitors. Also, in an example embodiment, the step in capacitance of the capacitor system may be determined based, at least in part, on a ratio of the capacitance of the second capacitance block to the capacitance of the first capacitance block.

The present invention provides an apparatus for enhancing Q factor of an inductor. The apparatus includes a negative resistance generator coupled to the inductor for providing a negative resistance, and a bias circuit coupled to the negative resistance generator for biasing the negative resistance generator.

A plurality of varactors are coupled via a first electrode to a shared terminal that in turn can operably couple to a source of control voltage. A second electrode for each varactor couples to a corresponding switch, where each switch couples to at least two different voltage levels. So configured, the second electrode of each varactor can be individually connected to either of two voltage levels. This can be leveraged to control, in coarse steps, the overall aggregate effective capacitance presented by these components. At least some of these varactors can have differing corresponding capacitances, the specific values of which can be selected in order to facilitate relatively equal spacing and substantially equal rates of reactance change versus the control voltage value between aggregate-capacitive reactance ranges as correspond to differing settings for the switches at various levels for the control voltage source.

Provided is an oscillator including: a MEMS resonator for mechanically vibrating; an output oscillator circuit for oscillating at a resonance frequency of the MEMS resonator to output an oscillation signal; and a MEMS capacitor for changing a capacitance thereof caused by a change in a distance between an anode electrode and a cathode beam according to an environmental temperature.

The invention discloses a varactor device (100) for improved temperature stability, comprising a first varactor (160) connected to a decoupling network (150). The device further comprises a voltage stabilizer (110), said stabilizer comprising a capacitor (140) and a temperature dependent capacitor (130), and in that the stabilizer comprises means for connection to a DC-feed (120). Suitably, the decoupling network (150) is connected in parallel to the first varactor (160), and the capacitor (140) of the voltage stabilizer (110) is connected in parallel to the decoupling network (150), the temperature dependent capacitor (130) of the voltage stabilizer (110) being connected in series to the diode of the voltage stabilizer (110).

An embodiment of the present invention provides an apparatus, comprising at least one anti-parallel pair VVC network comprised of two parallel VVCs with one biased in the opposite polarity of the other and at least one anti-series VVC network comprised of two VVCs configured in series, one biased in the opposite polarity of the other such that the resulting AC capacitive variations produce a desired capacitance variation.

The present invention provides a central frequency adjustment device and adjustable inductor layout; wherein, the central frequency adjustment device is applied in an inductor/capacitor tank (LC tank) for adjusting the central frequency of the LC tank. The device comprises a first inductor with a first end and a second end; a second inductor with one end coupled with the second end of the first inductor; and, a first trimmable wire connected to the first inductor in parallel and to the second inductor in series, which adjusts the central frequency by cutting off the first trimmable wire.

One embodiment relates to a circuit for active loss compensation. The circuit includes a parallel inductor-capacitive (LC) tank circuit having a first single-ended output. A first adjustable capacitor, which includes a first terminal and a second terminal, is coupled to the first single-ended output. The circuit also includes a first pair of transistors having sources coupled to a first common node. One transistor of the first pair of transistors has a drain coupled to the first single-ended output and the other transistor of the first pair of transistors has a gate coupled to the second terminal of the first adjustable capacitor. Other embodiments are also disclosed.

Disclosed are one-port and two-port voltage-tunable micro-electromechanical capacitors, switches, and filter devices. High aspect-ratio metal micromachining is used to implement very high quality factor (Q) tunable and fixed capacitors, fixed inductors, and low insertion loss tunable and fixed bandpass LC filters. The tunable capacitors can move in the plane of the substrate by the application of DC voltages and achieve greater than 100% of tuning. A combination of low-loss substrate and highest conductivity metal is used to achieve record high Q and low insertion loss at radio frequencies. The disclosed tunable capacitor structure can also be used as a micromechanical switch.

An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.

A tunable capacitor device may be provided in accordance with example embodiments of the invention. The tunable capacitor device may include a first capacitor; a second capacitor; a third capacitor, where the first, second, and third capacitors are connected in series, wherein the second capacitor is positioned between the first capacitor and the second capacitor; and at least one switch transistor, where the at least one switch transistor is connected in parallel with the second capacitor.

A circuit (C1-C4) is employed in a TWACS transponder (T) installed in an electric meter (M). The transponder generates inbound signals (IB) transmitted from the location of the electric meter to a central location (R). Firmware (F) within the transponder controls the flow of current for each pulse through the circuit by triggering a semi-conductor device such as a SCR (X1) or TRIAC (X2). The resulting current flow through the inductor for a subsequent pulse, regardless of the pulse's polarity, will be in the opposite direction to that of the previous pulse. The result is to maintain a constant level of magnetization of the inductor core which does not have to be overcome by energy in the subsequent pulse resulting in amplitude of all the pulses imposed on an AC waveform being substantially the same.

Methods and means related to an electronic circuit having an inductor and a memcapacitor are provided. Circuitry is formed upon a substrate such that an inductor and non-volatile memory capacitor are formed. Additional circuitry can be optionally formed on the substrate as well. The capacitive value of the memcapacitor is adjustable within a range by way of an applied programming voltage. The capacitive value of the memcapacitor is maintained until reprogrammed at some later time. Oscillators, phase-locked loops and other circuits can be configured using embodiments of the present teachings.

An improved grounding technique for mechanically adjustable rotary capacitors uses a directly grounded bronze sliding contact to effectively and continuously ground the rotating comb-like blades of the capacitor. RF measurements of the continuity and repeatability of the capacitance settings prove the suitability of the modified capacitors for using in pre-calibrated multi-capacitor MHz range impedance tuners.

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor.

There is provided a bearing for motor-powered fuel injection pumps, made from Cu—Ni-based sintered alloy, which is able to be obtained at a low cost, having excellent corrosion and abrasion resistances. The bearing contains 10 to 20% by mass of Ni, 5 to 13% by mass of Sn, 0.1 to 0.8% by mass of P, 1 to 6% by mass of C, and a remainder containing Cu and inevitable impurities, and is formed with a Ni—Sn—Cu—P phase containing at least 30% by mass of Sn in a grain boundary, and has a 8 to 18% porosity. The Ni—Sn—Cu—P phase contains 30 to 49% by mass of Ni, 10 to 30% by mass of Cu, 0.5 to 1.5% by mass of P, and a remainder containing Sn and inevitable impurities.

A device includes a chemical hydride fuel pellet having a plurality of holes extending from a first end to a second end. A plurality of tubes formed of water vapor permeable and hydrogen impermeable material extend from the first end to the second end through the tubes. A container has an inlet for water vapor containing gas coupled to the first end of the tubes and an outlet coupled to the second end of the tubes. A hydrogen outlet is coupled to the fuel pellet.

Magnesium-based hydrogen storage alloys with addition of transition and rare earth elements were produced by conventional induction melting and by rapid solidification. The magnesium based-alloys of this invention posses reversible hydrogen storage capacities ranging from 3 to over 6 wt. %, and excellent performance on the hydrogen absorption and desorption kinetics.

An object of the present invention is to provide a Ni-based superalloy, especially for a conventional casting, having a good balance among high temperature strength, corrosion resistance and oxidation resistance, as compared to a conventional material. The Ni-based superalloy comprises Cr, Co, Al, Ti, Ta, W, Mo, Nb, C, B, and inevitable impurities, the balance being Ni, the Ni-based superalloy having a superalloy composition comprising, by mass, 13.1 to 16.0% Cr, 11.1 to 20.0% Co, 2.30 to 3.30% Al, 4.55 to 6.00% Ti, 2.50 to 3.50% Ta, 4.00 to 5.50% W, 0.10 to 1.20% Mo, 0.10 to 0.90% Nb, 0.05 to 0.20% C, and 0.005 to 0.02% B.