Concurrency architecture verification engineer

Are you interested in concurrency, CPU design, and verification? Then we have just the opportunity for you.

Arm uses innovative tools [1] for modelling and reasoning about concurrency in our products. 

Those tools serve different purposes, such as: clarifying our architecture specification [2], communicating with our partners, and enabling verification of our CPU hardware designs.

This last point is at the intersection of architectural specification and CPU hardware design, which is where your role would be.

We seek to encourage interaction between those activities within Arm and beyond: by working hand in hand with architects and CPU verification teams to understand their requirements, you will improve our methodology and tools. You will also be in charge of inventing and prototyping new ways to verify pre-silicon designs.

This is an outstanding opportunity if you are interested in:

• developing open-source tools [3] which benefit the Arm ecosystem and wider communities such as language standard committees, compiler and kernel developers;
• furthering the understanding of an area that has been the subject of intense research in the last decade;
• demonstrating the impact of formal models on industrial products.

Our tools are written in Ocaml and C; knowing those languages would be ideal, as well as a working knowledge of Linux, git and RTL.

See also:

[1] https://developer.arm.com/architectures/cpu-architecture/a-profile/memory-model-tool

[2] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile

[3] http://diy.inria.fr

[4] https://github.com/herd/herdtools7/

Are you passionate about technology and information/cyber security? Do you want to know what it feels like to be part of a growing team that is building the foundations of a world-class information security program? We have more work than we can handle.

We are offering an internship with opportunities to gain experience in Threat monitoring and investigation, Risk management and mitigation, Incident management, Architectural governance and consultation, Vulnerability Management, and Security awareness and user behaviors.

What will I be accountable for?

Key projects may include:

• Monitoring incident management queues
• Creating or implementing security tooling
• Automating monitoring of internal controls
• Roll-out and education of a new set of information security policies
• Working with business units to create “get well” plans
• Helping to research and analyse requests for changes to policies and standards
• Conducting security reviews of third parties
• Developing training programs for users

We are an Equal Opportunity Employer and do not discriminate against any employee or applicant for employment because of race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, and basis of disability or any other federal, state or local protected class.

About the role

Are you passionate about technology and information/cyber security? Do you want to know what it feels like to be part of a growing team that is building the foundations of a world-class information security program? We have more work than we can handle.

We are offering an internship with opportunities to gain experience in Threat monitoring and investigation, Risk management and mitigation, Incident management, Architectural governance and consultation, Vulnerability Management, and Security awareness and user behaviors.

What will I be accountable for?

Key projects may include:

• Monitoring incident management queues
• Creating or implementing security tooling
• Automating monitoring of internal controls
• Roll-out and education of a new set of information security policies
• Working with business units to create “get well” plans
• Helping to research and analyse requests for changes to policies and standards
• Conducting security reviews of third parties
• Developing training programs for users

Arm has a range of vacancies for enthusiastic graduates with a passion for embedded software development, Open Source software and CPU Architecture. If you have a software background and a willingness to learn, you will be considered for work in one of these areas:

• Software design and implementation of features for our reference Mali Graphics processors (enabling our next generation Mali mobile IPs for APIs such as GLES, Vulkan, OpenCL, EGL) on Android
• Compiler development using LLVM for GPGPU kernels
• Compiler development including open source compilation technology for e.g. Apache TVM targeting Arm's CPUs, GPUs and NPUs.
• Improvements and performance optimisations for Arm Compute Library and ArmNN.
• Model Conditioning and sophisticated machine language framework optimisations in frameworks like Tensorflow and Pytorch.
• Performance analysis of NPUs, GPUs or CPUs
• Arm Secure Firmware development
• Software stack development to enable Arm IP.
• Operating system development (Linux, Zephyr, FreeRTOS, mbedOS, etc)
• Verification of Arm CPUs using full-stack operating system software
• Development of Software Tools for CPU Verification using Random Instruction Generation
• Software optimisation (JIT compilers, Android, ChromeOS, …)
• Build environments & Automation tooling

If you have an interest in CPU, GPU or NPU architecture and you are passionate about software, whether it’s kernel, driver, application or tools development; If you’d like to know more about how hardware and software interact, then this is an outstanding opportunity for you!

What will I be accountable for?

As a Graduate, you will be placed in a development team at Arm’s offices in Cambridge, UK where you will have a dedicated mentor, and be able to get to grips with the problems ranging across many software areas. You will work across all aspects of the software lifecycle whilst being supported by and learning from the rest of the team.

Whilst a lot of our work does involve Open Source software, many tasks require working with development platforms, or simulated hardware environments where features are being developed and tested before the physical devices have been built, so the problems you will be encouraged to understand and pursue are ones that are yet unknown to the general community.

If you consider yourself creative, innovative, a problem solver and you would like to influence and contribute to defining the next-generation CPUs that will be used in billions of devices worldwide, you will enjoy working and developing your professional career with us.

We are looking for graduate engineers who are passionate about understanding the workloads of the future to join our CPU benchmarking team.

Our benchmarking team is in charge of interacting with product managers, partners, CPU leads and performance modelling leads to understand the most relevant applications industry will use in the future and help to characterise and reproduce them on cutting-edge environments ranging from simulation to emulation or FPGA. The team is also responsible for investigating novel techniques to facilitate the utilisation of benchmarks that are relentlessly growing in complexity and make them suitable for the exploration of next generation CPU cores and systems.

As part of the CPU team, we will collaborate to innovate and find engineering solutions to the challenges of tomorrow in areas like IoT, automotive, servers or mobile; we will make devices smarter and more useful to society. Your contributions will help to build new technology that will influence the lives of billions of people!

Graduate on CPU Benchmark Role at Arm

We have exciting opportunities in the CPU group, where you will be part of a highly motivated team that helps define new generations of mainstream processors.

You will have real responsibilities from day one and you will get support and mentorship from specialists that will help you succeed and develop your career. Through teamwork, training, and dedication to personal development, we ensure that every graduate matures to become a specialist in the field.

You will work in a multi-site, multi-cultural environment and will have the opportunity to work on different projects.

What will your role be?

• You will contribute to the definition of the next generation of Arm’s IP products, identifying and enabling new benchmarks, and proposing new insights on methodologies that could improve current practice in benchmark characterisation and simulation.
• Together with marketing, technical leads, modelling leads and partners we will align on applications that will represent market requirements for future products.
• You will propose, develop and maintain innovative ways of making relevant applications and benchmarks suitable for sophisticated simulation platforms.
• You will collaborate with technical leads, performance modelling engineers and designers while doing performance analysis on existing and future designs.
• Explore new methodologies and novel software techniques that will improve modelling efficiency.

Are you creative, innovative, and passionate about new technologies?

Would you like to help us continue deploying billions of successful devices around the world, many of them enabling safety critical environments such as automotive or robotics?

We are looking for outstanding graduates to be part of our STL (Software Test Library) development team within our CPU group in Cambridge, UK. As part of your responsibilities, you will develop safety-critical software (often written in assembly and C) tightly couple with the internals of CPU design. You will also identify and build creative hardware features inside the CPU that improve the effectiveness of our solutions for segments where safety is of paramount importance without negatively affecting the power, performance and/or area of the core.

STLs execute opportunistically when the hardware is not fully utilized and perform continuous in-depth hardware diagnostics while the system is in operation. It identifies and notifies about functional misbehaviors derived from permanent faults triggered by natural hardware wear-out, or other uncontrollable factors before they may translate into catastrophic system failures with undesirable and even dangerous consequences.

If you are passionate about understanding the interaction between hardware and software, have used some HDL language (Verilog or VHDL) and can program on assembly and/or C, this could be an excellent opportunity to start your career with an exciting challenge. We work on a multi-cultural and multi-disciplinary environment that will motivate you to further improve your skills and also contribute and get deep knowledge on Arm CPU designs and development processes. Engineers with large experience in the field will coach you and help you navigate and learn the complexities of the CPU internals and the mechanisms to meet expectations on safety from emerging markets.

STL is a fundamental piece of the development strategy for sectors with strong safety requirements like automotive, health or robotics. Working with us, you are going to deeply influence and interact on the development of successful solutions for this sectors in conjunction with our multidisciplinary team.

We are an equal opportunity employer with an open culture and value diversity. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

Role Responsibilities

We have exciting opportunities in the CPU group for graduates, where you will become part of a highly motivated team that develops the STLs for Arm CPUs.

You will have real responsibilities from day one and you will get support and guidance from experts that will help you succeed and develop your career. Through teamwork, training, and dedication to personal development, we ensure that every graduate matures to become an expert in the field.

You will work in a multi-site, multi-cultural environment and will have the opportunity to work on different projects.

As a member of the team we will share the following responsibilities:

• We will define the STL design specifications, verification plan and the safety documents as per ISO26262 and IEC61508.
• We will build diagnostic software to target CPU sub-units like ALU, pre-fetchers, branch predictors, cache controllers, memory systems, etc.
• We will envision hardware design features aiming to improve STL effectiveness on ongoing and future CPU developments. We will also get along with the rest of the designers to implement them with minimum impact on area, performance and power.
• We will prove that the software as well as the STL-specific hardware features meet the specifications and work properly on different CPU configurations.
• We will generate the safety analysis of the STLs.

Tell Me More has regularly turned to Alfredo Corchado for insight on Mexico. He gives host Michel Martin one last look into his reporter's notebook.

Russia struck one of the key supply routes for the Armed Forces of Ukraine — the bridge across the Dnieper estuary near Odessa. The strike on the bridge came as a warning to Ukraine's allies — Romania and Moldova. "This is a warning not even to Ukraine, but to Moldova and Romania that service all these port destinations. This is a very serious violation of logistics for the AFU," military expert, retired colonel Anatoly Matviychuk said. The bridge was used as the main supply route for Western weapons. The weapons would be delivered to the Odessa region before being distributed throughout Ukraine.

Hard X-ray absorption spectroscopy is a valuable in situ probe for non-destructive diagnostics of metal sites. The low-energy interval of a spectrum (XANES) contains information about the metal oxidation state, ligand type, symmetry and distances in the first coordination shell but shows almost no dependency on the bridged metal–metal bond length. The higher-energy interval (EXAFS), on the contrary, is more sensitive to the coordination numbers and can decouple the contribution from distances in different coordination shells. Supervised machine-learning methods can combine information from different intervals of a spectrum; however, computational approaches for the near-edge region of the spectrum and higher energies are different. This work aims to keep all benefits of XANES and extend its sensitivity towards the interatomic distances in the first and second coordination shells. Using a binuclear bridged copper complex as a case study and cross-validation analysis as a quantitative tool it is shown that the first 170 eV above the edge are already sufficient to balance the contributions of Cu–O/N scattering and Cu–Cu scattering. As a more general outcome this work highlights the trivial but often overlooked importance of using `longer' energy intervals of XANES for structural refinement and machine-learning predictions. The first 200 eV above the absorption edge still do not require parametrization of Debye–Waller damping and can be calculated within full multiple scattering or finite difference approximations with only moderately increased computational costs.

Single crystals of the mol­ecular compound, {Cu20Ir6Cl8(C21H24N2)6(C4H4N2)3]·3.18CH3OH or [({Cu10Ir3}Cl4(IMes)3(pyrazine))2(pyrazine)]·3.18CH3OH [where IMes is 1,3-bis­(2,4,6-trimethylphen­yl)imidazol-2-yl­idene], with a unique heterometallic cluster have been prepared and the structure revealed using single-crystal X-ray diffraction. The mol­ecule is centrosymmetric with two {Cu10Ir3} cores bridged by a pyrazine ligand. The polymetallic cluster contains three stabilizing N-heterocyclic carbenes, four Cl ligands, and a non-bridging pyrazine ligand. Notably, the Cu—Ir core is arranged in an unusual shape containing 13 vertices, 22 faces, and 32 sides. The atoms within the trideca­metallic cluster are arranged in four planes, with 2, 4, 4, 3 metals in each plane. Ir atoms are present in alternate planes with an Ir atom featuring in the peripheral bimetallic plane, and two Ir atoms featuring on opposite sides of the non-adjacent tetra­metallic plane. The crystal contains two disordered methanol solvent mol­ecules with an additional region of non-modelled electron density corrected for using the SQUEEZE routine in PLATON [Spek (2015). Acta Cryst. C71, 9–18]. The given chemical formula and other crystal data do not take into account the unmodelled methanol solvent mol­ecule(s).

Full Text:

Bridges make travel faster and more convenient, but, in an earthquake, these structures are subject to forces that can cause extensive damage and make them unsafe. Now civil and environmental engineer Petros Sideris of Texas A&M University is leading a National Science Foundation (NSF)-funded research project to investigate the performance of hybrid sliding-rocking (HSR) columns. HSR columns provide the same support as conventional bridge infrastructure columns but are more earthquake-resistant. HSR columns are a series of individual concrete segments held together by steel cables that allow for controlled sliding and rocking. This allows the columns to shift without damage, while post-tensioning strands ensure that at the end of an earthquake the columns are pushed back to their original position. Conventional bridges are cast-in-place monolithic concrete elements that are strong but inflexible. Structural damage in these bridge columns, typically caused by a natural disaster, often forces a bridge to close until repairs are completed. But bridges with HSR columns can withstand large earthquakes with minimal damage and require minor repairs, likely without bridge closures. Such infrastructure helps with post-disaster response and recovery and can save thousands in taxpayer dollars. In an earthquake, HSR columns provide "multiple advantages to the public," Sideris said. "By preventing bridge damage, we can maintain access to affected areas immediately after an event for response teams to be easily deployed, and help affected communities recover faster. In mitigating losses related to post-event bridge repairs and bridge closures, more funds can be potentially directed to supporting the recovery of the affected communities." According to Joy Pauschke, NSF program director for natural hazards engineering, "NSF invests in fundamental engineering research so that, in the future, the nation's infrastructure can be more resilient to earthquakes, hurricanes, and other forces of nature."

Image credit: Texas A&M University

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