A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M−1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IIR filters, respectively. The M allpass IIR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

A system (200) and a method (100) of operating a computing device to perform memoization are disclosed. The method includes determining whether a result of a function is stored in a cache and, if so, retrieving the result from the cache and, if not, calculating the result and storing it in the cache. The method (100) includes transforming (104) by the computing device at least one selected from the input parameters and the output parameters of the function, the transforming being based on an analysis of the function and its input arguments to establish whether or not there is a possible relationship reflecting redundancy among the input parameters and output parameters of the function. The transforming may include at least one of: use of symmetry, scaling, linear shift, interchanging of variables, inversion, polynomial and/or trigonometric transformations, spectral or logical transformations, fuzzy transformations, and systematic arrangement of parameters.

Devices, systems, methods, and other embodiments associated with generating a moving average are described. In one embodiment, a method includes inputting a new data value, wherein the new data value is a most recent data value in a series of M prior sequential data values that are input to an accumulator for the purpose of calculating a moving average having a window size of M. The method also includes detecting an error in the new data value and correcting the moving average, based at least in part, on the error.

A method of generating a code sequence in a wireless communication system is disclosed. More specifically, the method includes recognizing a desired length of the code sequence, generating a code sequence having a length different from the desired length, and modifying the length of the generated code sequence to equal the desired length. Here, the step of modifying includes discarding at least one element of the generated code sequence or inserting at least one null element to the generated code sequence.

A method for generating multi-level (or multi-bit) pseudo-random sequences is disclosed. This embodiment relates to communication systems, and more particularly to generating multi-level pseudo random symbol sequence. Present day systems do not employ effective mechanisms for generation of multi level PRBS in order to increase the data communication rates. Further, these systems do not cover all the possible transitions for the outputs of the system. The proposed system employs mechanisms in order to generate PRBS signals for producing multi levels signals to the electronic components. The mechanism employs alternate bit tapping techniques. In the alternate bit tapping technique, bits are tapped alternatively to determine the current state and the next state of the system. In addition, the mechanism also covers all the possible states of the output vector with transitions between the output states. This ensures that high data rates are obtained for a given bandwidth of operation.

Examples disclose a computing system comprising a computing device with a display surface to detect a selection of functionality from a list of functionalities to be disabled on a calculator. Further, the computing device creates a custom configuration based on the selected functionality. Additionally, the examples also disclose a calculator with a processor to integrate the custom configuration, the custom configuration restricts the selected functionality on the calculator.

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

A data processing apparatus is provided for producing a randomized value. A cell in the data processing apparatus comprises a dielectric oxide layer and stress voltage circuitry is configured to apply a stress voltage across the dielectric oxide layer of the cell to cause an oxide breakdown process to occur. Oxide breakdown detection circuitry is configured to determine a current extent of the oxide breakdown process by measuring a response of the dielectric oxide layer to the stress voltage and randomized value determination circuitry is configured to determine a randomized value in dependence on the current extent of the oxide breakdown process.

A durable ambient light curable waterproof liquid rubber coating with volatile organic compound (VOC) content of less than 450 grams per liter made from ethylene propylene diene terpolymer (EPDM) in a solvent, a photoinitiator, an additive, pigments, and fillers, and a co-agent and a method for making the formulation, wherein the formulation is devoid of thermally activated accelerators.

A crosslinkable curing super-branched polyester and the cured product and the preparation method thereof are disclosed. The super-branched polyester has high refractive index and comprises a compound represented by the following structural formula (I). In the formula (I), HBP is the backbone of the super-branched polyester; both a and b are positive integers; the sum of a and b is less than or equal to n; n is more than or equal to 10 and less than 80. In the super-branched polyester, A is represented by formula (II) and N is represented by formula (III), wherein R is methyl or hydrogen atom; the mole ratio of N relative to the total mole of A and N is more than 30 mol %, and the ratio of the total mole of A and N relative to the product of the total mole of HBP backbone and n is more than 0.5 and less than or equal to 1.

A process for the preparation of polymer lattices comprising polymer nanoparticles by a photo-initiated heterophase polymerization includes preparing a heterophase medium comprising a dispersed phase and a continuous phase and at least one of at least one surfactant, at least one photoinitiator, and at least one polymerizable monomer. The at least one polymerizable monomer is polymerized by irradiating the heterophase medium with electromagnetic radiation so as to induce a generation of radicals. The at least one photoinitiator is selected from compounds comprising at least one phosphorous oxide group (P═O) or at least one phosphorous sulfide (P═S) group. The irradiating of the heterophase medium is effected so that a ratio of an irradiated surface of the heterophase medium to a volume of the heterophase medium is at least 200 m−1.

A radiation curable temporary laminating adhesive composition for use in temperature applications at 150° C. or greater, and typically at 200° C. or greater, comprises (A) a hydrogenated polybutadiene diacrylate; (B) a radical photoinitiator; and (C) a diluent.

The present invention relates to methods for making wear and oxidation resistant polymeric materials by high temperature melting. The invention also provides methods of making medical implants containing cross-linked antioxidant-containing tough and ductile polymers and materials used therewith also are provided.

A virtual machine (VM) migration from a source virtual machine monitor (VMM) to a destination VMM on a computer system. Each of the VMMs includes virtualization software, and one or more VMs are executed in each of the VMMs. The virtualization software allocates hardware resources in a form of virtual resources for the concurrent execution of one or more VMs and the virtualization software. A portion of a memory of the hardware resources includes hardware memory segments. A first portion of the memory segments is assigned to a source logical partition and a second portion is assigned to a destination logical partition. The source VMM operates in the source logical partition and the destination VMM operates in the destination logical partition. The first portion of the memory segments is mapped into a source VMM memory, and the second portion of the memory segments is mapped into a destination VMM memory.

Embodiments of the present invention relate to a method and an apparatus for obtaining equipment identification information, where the method includes: detecting, by using a first GPIO port, a first discharging duration for a capacitor to discharge through a resistor to be tested; detecting, by using a second GPIO port, a second discharging duration for the capacitor to discharge through a fixed value resistor; and obtaining a resistance of the resistor to be tested according to the first discharging duration, the second discharging duration, and a resistance of the fixed value resistor. The embodiments of the present invention are capable of increasing identification efficiency of the GPIO port.

An electronic data tablet has a controller and transition manager. The controller is to store in a memory of the tablet virtual configuration space information for a peripheral device of a computer, and the transition manager is to control the controller to operate in a first mode and a second mode. The virtual configuration space information is stored in the tablet memory when the first mode is to be switched to the second mode. When the second mode is switched to the first mode, the virtual configuration space information is accessed to control recognition of the peripheral device of the computer without performing a re-scanning operation.

Provided are a storage device, controller, and method for using host transfer rates to select a recording medium transfer rate for transferring data to a recording medium. A host transfer rate of data with respect to a buffer is measured. Provided are a plurality of recording medium transfer rates at which data is transferred between the buffer and the recording medium. A determination is made of an amount of decrease in the host transfer rate. The recording medium transfer rate is selected based on the amount of decrease in the host transfer rate. A transfer rate at which the storage device transfers data is set to the selected recording medium transfer rate.

A semiconductor memory device includes a selection signal generation unit configured to generate a plurality of selection signals that are sequentially activated, a path selection unit configured to select a transmission path of sequentially input information data in response to the plurality of selection signals, a plurality of first storage units, each configured to have a first storage completion time and store an output signal of the path selection unit, and a plurality of second storage units, each configured to have a second storage completion time, which is longer than the first storage completion time, and store a respective output signal of the plurality of first storage units.

A data storage device includes a first memory device configured to store data having a first property, a second memory device configured to store data having a second property, and a controller. The controller selects data stored in the first memory device, and transfers the selected data to the second memory device or stores the selected data in another physical location of the first memory device selectively depending on an update count (UC) of an address at which the selected data is stored.

Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.

An information processing apparatus includes a plurality of modules connected in a ring shape via a bus, and each module processes a packet flowing in a single direction on the ring in a predetermined order. The module includes a communication unit for transmitting a packet received from a first direction in the ring via the bus to a second direction, a discrimination unit for discriminating a packet from among the packets received from the first direction as a processing packet to be processed by the module, and a processing unit which is connected with the communication unit one by one and configured to process the processing packet. The communication unit transmits the packet processed by the processing unit at an interval equivalent to processing time or more for a processing packet processed by a module in a latter stage in the predetermined order among packets transmitted by the communication unit to the second direction.

A bus interconnect interfaces a host system to a radio frequency (RF) generator that is coupled to a plasma chamber. The bus interconnect includes a first set of host ports, which are used to provide a power component setting and a frequency component setting to the RF generator. The ports of the first set of host ports are used to receive distinct variables that change over time. The bus interconnect further includes a second set of generator ports used to send a power read back value and a frequency read back value to the host system. The bus interconnect includes a sampler circuit integrated with the host system. The sampler circuit is configured to sample signals at the ports of the first set at selected clock edges to capture operating state data of the plasma chamber and the RF generator.

Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.

A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

Various embodiments include apparatuses, stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.

A method for sharing peripheral devices in dual operating systems for an electronic device having at least one peripheral device is provided. The method includes: receiving a setting value for the peripheral device under the first operating system from a user; activating a second operating system; transmitting the setting value to the second operating system; and switching from the first operating system to the second operating system, wherein the second operating system sets the peripheral device with the setting value and enables the electronic device to operate under the second operating system.

A method and an apparatus for generating metadata for digital content are described, which allow to review the generated metadata already in course of ongoing generation of metadata. The metadata generation is split into a plurality of processing tasks, which are allocated to two or more processing nodes. The metadata generated by the two or more processing nodes is gathered and visualized on an output unit.

A system for protecting an electronic device against malware includes a memory, an operating system configured to execute on the electronic device, and a below-operating-system security agent. The below-operating-system security agent is configured to trap an attempted access of a resource of the electronic device, access one or more security rules to determine whether the attempted access is indicative of malware, and operate at a level below all of the operating systems of the electronic device accessing the memory. The attempted access includes attempting to write instructions to the memory and attempting to execute the instructions.

Some embodiments provide a method for managing a logical switching element that includes several logical ports. The logical switching element receives and sends data packets through the logical ports. The logical switching element is implemented in a set of managed switching elements that forward data packets in a network. The method provides a set of tables for specifying forwarding behaviors of the logical switching element. The method performs a set of database join operations on the tables to specify in the tables that the logical forwarding element drops a data packet received through a first logical port when the data packet is headed to a second logical port different than the first logical port.

A server computer system determines that configuring a first virtual machine in a cloud depends on a configuration result of configuring a second virtual machine. The server computer system configures the second virtual machine in the cloud and configures the first virtual machine in the cloud using the configuration result of the second virtual machine.

Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.

According to an embodiment, based on task border information, and first-type dependency relationship information containing N number of nodes corresponding to data accesses to one set of data, containing edges representing dependency relationship between the nodes, and having at least one node with an access reliability flag indicating reliability/unreliability of corresponding data access; task border edges, of edges extending over task borders, are identified that have an unreliable access node linked to at least one end, and presentation information containing unreliable access nodes is generated. According to dependency existence information input corresponding to the set of data, conversion information indicating absence of data access to the unreliable access nodes is output. According to the conversion information, the first-type dependency relationship information is converted into second-type dependency relationship information containing M number of nodes (0≦M≦N) corresponding to data accesses to the set of data and containing edges representing inter-node dependency relationship.

A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

Methods and apparatus are provided for evaluating potential resource capacity in a system where there is elasticity and competition between a plurality of containers. A dynamic potential capacity is determined for at least one container in a plurality of containers competing for a total capacity of a larger container. A current utilization by each of the plurality of competing containers is obtained, and an equilibrium capacity is determined for each of the competing containers. The equilibrium capacity indicates a capacity that the corresponding container is entitled to. The dynamic potential capacity is determined based on the total capacity, a comparison of one or more of the current utilizations to one or more of the corresponding equilibrium capacities and a relative resource weight of each of the plurality of competing containers. The dynamic potential capacity is optionally recalculated when the set of plurality of containers is changed or after the assignment of each work element.

A method and apparatus for method of continuously producing 1,1,1,2,3-pentafluoropropane with high yield is provided. The method includes (a) bringing a CoF3-containing cobalt fluoride in a reactor into contact with 3,3,3-trifluoropropene to produce a CoF2-containing cobalt fluoride and 1,1,1,2,3-pentafluoropropane, (b) transferring the CoF2-containing cobalt fluoride in the reactor to a regenerator and bringing the transferred CoF2-containing cobalt fluoride into contact with fluorine gas to regenerate a CoF3-containing cobalt fluoride, and (c) transferring the CoF3-containing cobalt fluoride in the regenerator to the reactor and employing the transferred CoF3-containing cobalt fluoride in Operation (a). Accordingly, the 1,1,1,2,3-pentafluoropropane can be continuously produced with high yield from the 3,3,3-trifluoropropene using a cobalt fluoride (CoF2/CoF3) as a fluid catalyst, thereby improving the reaction stability and readily adjusting the optimum conversion rate and selectivity.

A fluorographene and preparation method thereof are provided. For the said fluorographene, the fraction of F is 0.5

The present disclosure relates to a process for separating a fluoroolefin from a mixture comprising hydrogen fluoride and fluoroolefin, comprising azeotropic distillation both with and without an entrainer. In particular are disclosed processes for separating any of HFC-1225ye, HFC-1234ze, HFC-1234yf or HFC-1243zf from HF.

The present invention is directed to processes for the production of 1233zd from 240fa and HF, with or without a catalyst, at a commercial scale. The 240fa and HF are fed to a reactor operating at high pressure. The resulting product stream comprising 1233zd, HCl, HF, and other byproducts is treated to one or more purification techniques including phase separation and one or more distillations to provide purified 1233zd, which meets commercial product specifications, i.e., having a GC purity of 99.5% or greater.

The present invention relates to a process for separating chlorinated methanes utilizing a dividing wall column. Processes and manufacturing assemblies for generating chlorinated methanes are also provided, as are processes for producing products utilizing the chlorinated methanes produced and/or separated utilizing the present process(es) and/or assemblies.

The invention relates to a process for the preparation of formula (I) which process comprises pyrolyzing a compound of formula (II) wherein X is chloro or bromo, and to compounds which may be used as intermediates for the manufacture of the compound of formula I and to the preparation of said intermediates.

The subject of the invention is a process for the preparation of fluoroolefin compounds. It relates more particularly to a process for manufacturing a (hydro)fluoroolefin compound comprising (i) bringing at least one compound comprising from three to six carbon atoms, at least two fluorine atoms and at least one hydrogen atom, provided that at least one hydrogen atom and one fluorine atom are located on adjacent carbon atoms, into contact with potassium hydroxide in a stirred reactor, containing an aqueous reaction medium, equipped with at least one inlet for the reactants and with at least one outlet, in order to give the (hydro)fluoroolefin compound, which is separated from the reaction medium in gaseous form, and potassium fluoride, (ii) bringing the potassium fluoride formed in (i) into contact, in an aqueous medium, with calcium hydroxide in order to give potassium hydroxide and to precipitate calcium fluoride, (iii) separation of the calcium fluoride precipitated in step (ii) from the reaction medium and (iv) optionally, the reaction medium is recycled after optional adjustment of the potassium hydroxide concentration to step (i).

The present invention provides a method for separating halocarbons. In particular, the invention provides a method for separating halogenated olefin impurities from 2-chloro-1,1,1,2-tetrafluoropropane (HCFC-244bb) using a solid adsorbent, particularly activated carbon. More particularly the invention pertains to a method for separating 2-chloro-3,3,3-trifluoro-propene (HCFO-1233xf) from HCFC-244bb, which are useful as intermediates in the production of 2,3,3,3-tetrafluoropropene (HFO-1234yf).

A process for making a fluorinated olefin having the step of dehydrochlorinating a hydrochlorofluorocarbon having at least one hydrogen atom and at least one chlorine atom on adjacent carbon atoms, preferably carried out in the presence of a catalyst selected from the group consisting of (i) one or more metal halides, (ii) one or more halogenated metal oxides, (iii) one or more zero-valent metals/metal alloys, (iv) a combination of two or more of the foregoing.

A composition and method demulsify a produced emulsion from anionic surfactants and polymer (SP) and alkali, surfactants, and polymer (ASP). The produced emulsion is demulsified into oil and water. In one embodiment, the composition includes a surfactant. The surfactant comprises a cationic surfactant, an amphoteric surfactant, or any combinations thereof.

The invention relates to the use of polymers, containing between 1 and 100 mol % of structural units of the formula (1), wherein R1 means hydrogen or C1-C6 alkyl, A means C2-C4 alkylene groups, and B means C2-C4 alkylene groups, with the stipulation that A is different from B, and x and y mean an integer from 1 to 100 independent of each other, in amounts of 0.01 to 2 wt % relative to the water phase, as gas hydrate inhibitors.

The invention provides for the use of copolymers comprising 1 to 99 mol % of structural units of the formula (1) in which R1 is hydrogen or C1-C6-alkyl, A is C2-C4-alkylene groups and B is C2-C4-alkylene groups, with the proviso that A is different than B, and x, y are each independently an integer of 1-100, and 1 to 99 mol % of structural units of the formula (3) in which R6 is hydrogen or C1-C6-alkyl, D is C2-C4-alkylene groups and z is an integer of 1-50, in amounts of 0.01 to 2% by weight, based on the water phase, as gas hydrate inhibitors.

The invention is drawn to fluid concentrate formulations of fatty acid monoethanolamides comprising (a) about 71-76% by weight of one or more C8-C22 fatty acid monoethanolamides, (b) about 15-17% by weight of water, and (c) about 10-12% by weight of one or more hydrotropes, based on the fluid formulation, wherein the fluid formulation is homogeneous, pumpable and color stable at a temperature of less than 55° C. A preferred embodiment is drawn to fluid concentrate formulations of cocamide monoethanolamide (CMEA) consisting of (a) about 71-76% by weight of CMEA, (b) about 15-17% by weight of water, and (c) about 10-12% by weight of glycerol, based on the fluid formulation. Methods of preparing the fluid concentrate formulations mulations are also disclosed. The fluid concentrate formulations of fatty acid monoethanolamides are useful in the preparation of cosmetic and pharmaceutical compositions.

This invention provides a method related to the preparation of derivatives of poly(ethylene glycol), wherein the method comprises increasing the pH of an aqueous composition comprising a poly(ethylene glycol) bearing a —O—(CH2)n—CO2R3 functional group to result in an aqueous composition comprising a poly(ethylene glycol) bearing a —O—(CH2)n—CO2H functional group, wherein R3 is alkyl and (n) in each instance is 1-6.