There is disclosed a gate driver, a driving circuit, and a liquid crystal display (LCD), wherein the gate driver comprises input terminals for inputting a CPV signal, an OE signal, and an STV signal, and output terminals for outputting a CKV signal and a CKVB signal, and a processing circuit is connected between the input terminals and the output terminals for processing the CPV signal, the OE signal, and the STV signal such that a preset time interval is present between the falling edge of the CKV signal and the rising edge of the CKVB signal during one period of the CKV signal, or a preset time interval is present between the rising edge of the CKV signal and the falling edge of the CKVB signal during one period of the CKVB signal.

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.

The present invention relates to a method for downloading a binary configuration file in a programmable circuit implemented in a device. The device comprises at least one central processing unit, a plurality of connectors, and a programmable circuit enabling all or a part of the signals received by said connectors to be processed and transmitted to at least one other circuit of the device. The device analyzes the signals present on the connectors in order to define what other devices are connected and whether the connections are operational. Then, a configuration file is selected from among a set of configuration files according to the operational connections and is downloaded from a memory of the device into the programmable circuit. The invention also relates to a device having a component programmed according to the method previously described.

A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

According to one embodiment, a first oscillator has an oscillation frequency that is changed depending on a temperature. A second oscillator has different temperature characteristics from the first oscillator. An on-chip heater heats the first oscillator and the second oscillator. A counter counts a first oscillation signal of the first oscillator. An ADPLL generates a third oscillation signal on the basis of a second oscillation signal of the second oscillator and corrects the frequency of the third oscillation signal on the basis of a count value of the counter.

A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.

The present disclosure relates to nanoresonator oscillators or NEMS (nanoelectromechanical system) oscillators. A circuit for measuring the oscillation frequency of a resonator is provided, comprising a first phase-locked feedback loop locking the frequency of a controlled oscillator at the resonant frequency of the resonator, this first loop comprising a first phase comparator. Furthermore, a second feedback loop is provided which searches for and stores the loop phase shift introduced by the resonator and its amplification circuit when they are locked at resonance by the first loop. The first and the second loops operate during a calibration phase. A third self-oscillation loop is set up during an operation phase. It directly links the output of the controllable phase shifter to the input of the resonator. The phase shifter receives the phase-shift control stored by the second loop.

An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

An oscillator module includes a first MOS transistor and a capacitor. The capacitor is coupled between a gate and source of the first MOS transistor. The drain of the first MOS transistor receives a first bias current and generates an oscillating output signal. A switching circuit operates in response to the oscillating output signal to selective charge and discharge the capacitor. A current sourcing circuit is configured to generate the bias current. The current sourcing circuit includes a second MOS transistor which has an identical layout to the first MOS transistor and receives a second bias current. A resistor is coupled between a gate and source of the second MOS transistor. The current sourcing circuit further includes a current mirror having an input configured to receive a reference current passing through the resistor and generate the first and second bias currents.

The invention relates to a method for operating control equipment (1) of a resonance circuit (2), wherein the control equipment (1) comprises at least two circuit elements (8, 9) connected in series, in particular each comprising a recovery diode (13, 14) connected in parallel, between which a connection (6) of the resonance circuit (2) is connected. According to the invention, the circuit elements (8, 9) are actuated as a function of the voltage detected at the connection (6). The invention further relates to control equipment (1) of a resonance circuit (2).

A ring oscillator circuit causing a pulse signal to circulate around a circle to which an even number of inverting circuits are connected in a ring, wherein one of the inverting circuits is a first starting inverting circuit, which drives a first pulse signal according to a control signal, another of the inverting circuits is a second starting inverting circuit, which drives a second pulse signal based on a leading edge of the first pulse signal, still another is a third starting inverting circuit, which drives a third pulse signal based on the leading edge of the first pulse signal after the second pulse signal is driven, and the first to third starting inverting circuits are arranged within the circle of the inverting circuits in order of the third, second, and first pulse signals in traveling directions of the pulse signals.

A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack. A feedback connection is from an output of the last stage to an input of the first stage. At least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device is coupled between the first gate stack and a ground pad, and/or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device is coupled between the second gate stack a power supply pad.

An electronic oscillator circuit has a first oscillator, for supplying a first oscillation signal, a second oscillator, for supplying a second oscillation signal, a first controller for delivering the first control signal as a function of a phase difference between a first controller input and a second controller input of the first controller; a second controller for delivering the second control signal as a function of a phase difference between a first controller input of the second controller and a second controller input of the second controller; a resonator; at least a second resonance frequency, with a first phase shift dependent on the difference between the frequency of a second exciting signal and the second resonance frequency and processing means, for receiving the first oscillator signal and the second oscillator signal, determining their mutual proportion, looking up a frequency compensation factor in a prestored table and outputting a compensated oscillation signal.

A circuit includes first and second transconductance stages that generate first and second currents, respectively, in response to an input signal. A current combiner circuit selectively couples the first current to a first output, selectively couples the second current to the first output, selectively couples the first current to a second output, and selectively couples the second current to the second output. In response to the first current being coupled to both the first and second outputs, the current combiner circuit couples the second current to both the first and second outputs. In response to the first current being decoupled from the second output, the current combiner circuit decouples the second current from both the first and second outputs. In response to the first current being decoupled from the first output, the current combiner circuit decouples the second current from both the first and second outputs.

In a method for operating a fluid valve for controlling or regulating a fluid, having at least one movable valve component is displaceable with the aid of at least one electrical actuating signal which contains at least one first actuating signal portion which causes an oscillating valve motion of the valve component. Pressure oscillations generated in the fluid due to the oscillating valve motion are detected, and are used for regulation of the oscillating valve motion caused by the first actuating signal portion.

A fluid control valve includes an inflow channel for introducing fluid, an outflow channel for discharging the fluid, a valve seat, a valve body for blocking/allowing communication between the inflow channel and the outflow channel in association with a movement thereof into contact with or away from the valve seat, and a solenoid configured to apply a magnetic force to the valve body, the magnetic force being generated in response to supply of electric power to the solenoid. The inflow channel is formed through the core of the solenoid so that the core and the fluid comes into contact with each other in the inflow channel.

An embodiment is an integrated circuit structure including a first die attached to a second die by a first connector. The first connector includes a solder joint portion between a first nickel-containing layer and a second nickel-containing layer, a first copper-containing layer between the first nickel-containing layer and the solder joint portion, and a second copper-containing layer between the second nickel-containing layer and the solder joint portion.

In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

A protective film to a polarizer including a cellulose acylate and satisfying the following requirement (1) or (2): (1): The surface of the film has a pH of from 3.0 to 4.5.(2): The surface of the film has a pH of more than 4.5 and at most 6.0, and the film has a moisture permeability of at least 2800 g/m2·day.

In a semiconductor device, where, with respect to a parasitic resistor in a current mirror circuit, a compensation resistor for compensating the parasitic resistor is provided in the current mirror circuit, the current mirror circuit includes at least two thin film transistors. The thin film transistors each have an island-shaped semiconductor film having a channel formation region and source or drain regions, a gate insulating film, a gate electrode, and source or drain electrodes, and the compensation resistor compensates the parasitic resistor of any one of the gate electrode, the source electrode, and the drain electrode. In addition, each compensation resistor has a conductive layer containing the same material as the gate electrode, the source or drain electrodes, or the source or drain regions.

Provided is a switching liquid crystal panel and a display device that have novel structures that are capable of preventing luminous regions from appearing in the light transmitting parts, in the vicinities of boundaries thereof with the light shielding parts. The switching liquid crystal panel includes a pair of substrates (26a, 26b) having a twisted nematic type liquid crystal layer (24) interposed therebetween, and a plurality of light shield forming electrodes (30) that are formed on at least one of the pair of the substrates (26a, 26b) and that form light shielding parts (40) of a parallax barrier (16) in cooperation with a counter electrode (34) when a voltage is applied, the counter electrode (34) being is opposed to the light shield forming electrodes (30) with the liquid crystal layer (24) interposed therebetween. A rubbing direction for an alignment film (36a) provided on the substrate (26a) side on which the light shield forming electrodes (30) are formed is at an angle of 45° or less to a lengthwise direction of the light shield forming electrodes (30).

A liquid crystal display element disclosed includes: a first substrate; a second substrate; a liquid crystal layer sandwiched between the first substrate and the second substrate; a first transparent electrode provided at a display region of the first substrate; and a second transparent electrode provided at a display region of the second substrate, at least one of d1 and d2 being not larger than 60 nm, where d1 represents a thickness of the first transparent electrode and d2 represents a thickness of the second transparent electrode.

Provided is a liquid crystal display including, on an insulation substrate having a polygonal display area and a peripheral area surrounding the display area a first signal line, a second signal line crossing the first signal line, a plurality of switching elements connected to the first signal line and the second signal line and disposed in the display area, a plurality of pixel electrodes each connected to the switching element and disposed in the display area, and a shielding conductor disposed in the peripheral area and extending along at least one side of the polygonal display area.

Provided is a back plate component having reflective sheet reinforcing structure. The back plate component includes: a frame, a reflective sheet and a plurality of supporting film sheets. The frame includes a plurality of lateral beams and vertical beams, and at least one hollow part is included between the lateral beams and the vertical beams. The reflective sheet is attached to the frame, and includes a reflective surface and a back surface corresponding to the reflective surface. A portion of the back surface covers the whole hollow part. The plurality of supporting film sheets is attached to the back surface at a region corresponding to the hollow part, and includes a material the same as that of the reflective sheet. A liquid crystal display device is further disclosed herein.

A liquid crystal display device includes a first substrate, a first electrode on the first substrate, a second substrate opposed to the first substrate, and a second electrode on the second substrate. The second electrode corresponds to the first electrode. The liquid crystal display device also includes a liquid crystal structure between the first electrode and the second electrode. The liquid crystal structure includes a plurality of liquid crystal molecules and at least one movement control member. The movement control member in the liquid crystal structure restricts a movement of the liquid crystal molecules.

The present invention provides an optical compensated bending (OCB) mode liquid crystal display (LCD) panel and a method for manufacturing the same. The method comprises the following steps: forming alignment layers on substrate, respectively; forming a liquid crystal layer between the alignment layers to form a liquid crystal cell; applying an electrical signal across the liquid crystal cell; and irradiating light rays to or heating the liquid crystal cell, so as to form a first polymer alignment layer and a second polymer alignment layer, respectively. The present invention can reduce a phase transition time of liquid crystal molecules from a splay state to a bent state.

A liquid crystal display being capable of improving the contrast ratio in the front direction thereof is provided. A liquid crystal display 100 of the present invention includes, in sequence: a light source device 14 that emits a parallel light beam; a back surface-side polarizer 16; a liquid crystal cell 13; a display surface-side polarizer 11; and a light diffusion layer 15. The liquid crystal display 100 further includes: a selective light-shielding layer 12 between the display surface-side polarizer 11 and the light diffusion layer 15 so that the selective light-shielding layer 12 shields light that is generated by being depolarized and scattered in the liquid crystal cell 13 and travels in a direction that is different from a direction in which the parallel light beam travels.

There is provided an optical laminate which comprises: a polarizing film wherein a thin polarizing layer is laminated on one main surface of a substrate; and an optical element (lens array). The thin polarizing layer has a thickness of 8 μm or less. The substrate has a thickness of 20 μm to 80 μm. The optical element is a pattern retardation plate including a plurality of regions having different slow axis directions.

A counter substrate for liquid crystal display includes a transparent substrate, a black matrix, and stripe transparent electrodes. The black matrix divides a plane surface of the transparent substrate into pixel or sub-pixel unit to form a light-shielded area and openings above the plane surface. The stripe transparent electrodes are formed into the pixel unit or the sub-pixel unit above the plane surface. The black matrix includes a frame pattern including two sides facing each other in parallel in the pixel or the sub-pixel unit, and a linear central pattern which is parallel to the two sides of the frame pattern and is formed at a midsection of the pixel or the sub-pixel unit. The transparent electrodes are each parallel to the two sides of the frame pattern and the central pattern and are located symmetrically to the central pattern.

A transverse electric field type liquid crystal display panel includes a pair of substrates opposed with a liquid crystal layer interposed therebetween. A plurality of sub-pixels having at least one curved portion in a display area are provided in a matrix on one side of the pair of substrates, and a pair of electrodes having at least one curved portion are formed in the plurality of sub-pixels. A light shield layer shielding a non-display area positioned on an outer peripheral side of the display area and between the plurality of sub-pixels is formed on the other side of the pair of substrates. The light shield layer of the non-display area is formed in a shape in which the outermost peripheral side of the display area is rectangular.

Disclosed herein is a liquid crystal display device including a plurality of pixels each having a reflecting section and a transmitting section, the pixels each including a plurality of sub-pixels resulting from alignment division, the liquid crystal display device including: an element layer formed on a substrate; an insulating film formed on the substrate so as to cover the element layer; a pixel electrode formed on the insulating film so as to be connected to the element layer; a gap adjusting layer formed on the insulating film on the element layer including a region of connection between the element layer and the pixel electrode; and a dielectric formed on a connecting part for making an electric connection between the sub-pixels.

A liquid crystal display device includes a liquid crystal display element including a first alignment film and a second alignment film and a liquid crystal layer that is provided between the first alignment film and the second alignment film, wherein the first alignment film includes a compound in which a polymer compound that includes a cross-linked functional group or a polymerized functional group as a side chain is cross-linked or polymerized, the second alignment film includes the same compound as the compound that configures the first alignment film, and the formation and processing of the second alignment film is different from the formation and processing of the first alignment film and when a pretilt angle of the liquid crystal molecules which is conferred by the first alignment film is θ1 and a pretilt angle of the liquid crystal molecules which is conferred by the second alignment film is θ2, θ1>θ2.

The present invention provides a display device substrate, a display device substrate manufacturing method, a display device, a liquid crystal display device, a liquid crystal display device manufacturing method and an organic electroluminescent display device that allow suppressing faults derived from occurrence of gas and/or bubbles in a pixel region. The present invention is a display device substrate that comprises: a photosensitive resin film; and a pixel electrode, in this order, from a side of an insulating substrate. The display device substrate has a gas-barrier insulating film, at a layer higher than the photosensitive resin film, for preventing advance of a gas generated from the photosensitive resin film, or has a gas-barrier insulating film, between the photosensitive resin film and the pixel electrode, for preventing advance of gas generated from the photosensitive resin film.

The disclosed technology discloses an array substrate and a liquid crystal display panel. The array substrate comprises: a base substrate; a gate line and a data line formed on the base substrate, the gate line and the data line defining a plurality of pixel regions; and a first electrode layer and a second electrode layer formed in each pixel region; and an insulating layer provided between the first electrode layer and the second electrode layer. The first electrode layer, the insulating layer and the second electrode layer are laminated on the base substrate in this order. The first electrode layer is provided with a plurality of first apertures therein, and the first electrode layer comprises a plurality of first electrode portions located between the plurality of first apertures.

A pixel structure comprises a plurality of pixel regions, and each of the pixel regions includes first and second electrodes that are overlapped with each other, the first electrode is disposed above the second electrode, and each of the pixel regions is divided at least into a first to fourth domain display regions; strip-shaped first electrodes in the first to fourth domain display regions make first to fourth angles with a reference direction; the sum of the first angle and the second angle is 180 degrees, the sum of the third angle and the fourth angle is 180 degrees, and the first, the second, the third and the fourth angles are different from one another.

Apertures are formed in the common electrode or in the pixel electrode of a liquid crystal display to form a fringe field. Storage capacitor electrodes are formed at the position corresponding to the apertures to prevent the light leakage due to the disclination caused by the fringe field. The apertures extend horizontally, vertically or obliquely. The apertures in adjacent pixel regions may have different directions to widen the viewing angle.

The present invention discloses a tape substrate for chip on film structure of a liquid crystal panel. The tape substrate is provided with plural package units of chip on film structures arranged along its longitudinal direction, and the package unit has a driver chip, input leads and output leads. The longitudinal direction of the driver chip is parallel to the longitudinal direction of the tape substrate, and the input leads and the output leads are located at the two opposite sides of the driver chip. Each package unit is set up with a short side and a long side, and the input leads are formed at the short side, while the output leads are formed at the long side. In the package units adjacent to each other, the short side of one package unit joins the long side of a next package unit. This invention further discloses a liquid crystal panel having the tape substrate.

A liquid crystal display device includes a TFT substrate having a display region with first and second electrodes, TFTs, scanning signal lines connected to the TFTs, a counter substrate, a liquid crystal layer sandwiched between the TFT and counter substrates, and sealed by a sealant, scanning line leads connected to the scanning signal lines and formed outside of the display region, video signal line leads connected to the video signal lines and formed outside of the display region and a shield electrode formed on the TFT substrate covering the scanning line leads but not the video signal line leads. The second electrode is connected to one of the TFTs, and liquid crystal molecules of the liquid crystal layer are driven by an electric field, which is generated between the first and second electrodes. The shield electrode is electrically connected to the first electrode and overlapped with the sealant in plan view.

One of the objects of the present invention is to provide a liquid crystal display device with high transmittance or viewing angle characteristics. A liquid crystal display device of the present invention includes: a first substrate (10) which includes a pixel electrode (30); a second substrate (20) which includes a counter electrode (25); and a liquid crystal layer (21) and a spacer (40) which are provided between the first substrate (10) and the second substrate (20). The pixel electrode (30) includes a first portion which is formed by a plurality of first branch portions (34A) extending in a first direction, a second portion which is formed by a plurality of second branch portions (34B) extending in a second direction, a third portion which is formed by a plurality of third branch portions (34C) extending in a third direction, and a fourth portion which is formed by a plurality of fourth branch portions (34D) extending in a fourth direction. The spacer (40) is provided at a position in the pixel (50) which is surrounded by the first to fourth portions of the pixel electrode (30) when viewed from a direction perpendicular to a plane of the first substrate (10).

In a conventional bistable liquid crystal device, switching characteristics fluctuate among panels and there is a problem in mass productivity. As an intermediate layer, an uneven film is inserted between a low anchoring layer and ITO. The uneven film has an average surface roughness of 2 nm or less, which is measured by an atomic force microscope. In this manner, the low anchoring layer is not affected by the surface shape of the ITO film which differs among panels, and the switching characteristics are stabilized.

An optical switch for performing high extinction ratio switching of an optical signal includes a beam polarizing element and one or more optical elements. The optical elements are configured to direct an optical signal along a first or second optical path based on the polarization state of the optical signal as it passes through the optical elements. The optical switch performs high extinction ratio switching of the optical signal by preventing unwanted optical energy from entering an output port by using an absorptive or reflective optical element or by directing the unwanted optical energy along a different optical path.

A liquid crystal display panel, including: a pixel electrode formed on a first substrate; an alignment layer formed on the pixel electrode, wherein the alignment layer includes an alignment layer material and aligns first liquid crystal molecules in a direction substantially perpendicular to the pixel electrode; and a photo hardening layer formed on the alignment layer, wherein the photo hardening layer includes a photo hardening layer material and aligns second liquid crystal molecules to be tilted with respect to the pixel electrode, wherein the alignment layer material and the photo hardening layer material have different polarities from each other.

It is an object of the present invention to provide a liquid crystal display device which has a wide viewing angle and less color-shift depending on an angle at which a display screen is seen and can display an image favorably recognized both outdoors in sunlight and dark indoors (or outdoors at night). The liquid crystal display device includes a first portion where display is performed by transmission of light and a second portion where display is performed by reflection of light. Further, a liquid crystal layer includes a liquid crystal molecule which rotates parallel to an electrode plane when a potential difference is generated between two electrodes of a liquid crystal element provided below the liquid crystal layer.

A liquid crystal display capable of realizing a high transmittance while maintaining favorable voltage response characteristics, and a method of manufacturing the same are provided. The liquid crystal display includes: a liquid crystal layer; a first substrate and a second substrate arranged to face each other with the liquid crystal layer in between; a plurality of pixel electrodes provided on a liquid crystal layer side of the first substrate; and an opposite electrode provided on the second substrate to face the plurality of pixel electrodes. One or both of a face on the liquid crystal layer side of the pixel electrode, and a face on the liquid crystal layer side of the opposite electrode includes a concavo-convex structure.

The present invention provides a backlight module and a liquid crystal display device using the backlight module. The backlight module includes: a backplane (2), a light guide plate (4) arranged in the backplane (2), a backlight source (6) arranged in the backplane (2), an optic film assembly (8) arranged above the light guide plate (4), and a reflection plate (9) arranged between the backplane (2) and the light guide plate (4). The backlight source (6) includes a PCB (62) and a plurality of LED lights (64) mounted on and electrically connected to the PCB (62). The backplane (2) includes a bottom plate (22) and a plurality of side plates (24) perpendicularly connected to the bottom plate (22). The bottom plate (22) of the backplane (2) includes a snap-engagement structure (220) formed thereon. The PCB (62) is snap-fit into and retained by the snap-engagement structure (220). The reflection plate (9) is directly positioned on and supported by the PCB (62).

The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.

The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.