A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width.

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.

An embodiment is an integrated circuit structure including a first die attached to a second die by a first connector. The first connector includes a solder joint portion between a first nickel-containing layer and a second nickel-containing layer, a first copper-containing layer between the first nickel-containing layer and the solder joint portion, and a second copper-containing layer between the second nickel-containing layer and the solder joint portion.

In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

In a semiconductor device, where, with respect to a parasitic resistor in a current mirror circuit, a compensation resistor for compensating the parasitic resistor is provided in the current mirror circuit, the current mirror circuit includes at least two thin film transistors. The thin film transistors each have an island-shaped semiconductor film having a channel formation region and source or drain regions, a gate insulating film, a gate electrode, and source or drain electrodes, and the compensation resistor compensates the parasitic resistor of any one of the gate electrode, the source electrode, and the drain electrode. In addition, each compensation resistor has a conductive layer containing the same material as the gate electrode, the source or drain electrodes, or the source or drain regions.

Provided is a back plate component having reflective sheet reinforcing structure. The back plate component includes: a frame, a reflective sheet and a plurality of supporting film sheets. The frame includes a plurality of lateral beams and vertical beams, and at least one hollow part is included between the lateral beams and the vertical beams. The reflective sheet is attached to the frame, and includes a reflective surface and a back surface corresponding to the reflective surface. A portion of the back surface covers the whole hollow part. The plurality of supporting film sheets is attached to the back surface at a region corresponding to the hollow part, and includes a material the same as that of the reflective sheet. A liquid crystal display device is further disclosed herein.

A premium class passenger suite that includes a main seat positioned in the suite together with separate bed. The bed has a flexible mattress of predetermined dimensions and is movable between a stowed position to one side of the main seat and a deployed position above and separate from the main seat. A drive apparatus is provided for driving the bed between the stowed and deployed positions. The main seat is configured to be movable between a seating position when the bed is stowed, and a stowed position with a lowered seat back when the bed is deployed for use.

A seat cushion, in particular for an aircraft seat, the seat cushion comprising a seat part having a receiving surface adapted to receive a person and a reinforcing part supporting the seat part, wherein at least the reinforcing part contains expanded polypropylene (EPP), preferably comprising fire retardant properties. The invention further relates to a method for manufacturing such a seat cushion, a seat comprising such a seat cushion and a vehicle comprising such a seat.

An operating unit (1) for installation in an aircraft cabin comprises an operating unit front side (10) and an operating unit rear side (20), at least one operating element (12, 14) attached in the region of the operating unit front side (10) and accessible to a user, and a holding device (40) for attaching the operating unit (1) to a monument (30) accommodating the operating unit (1) in its state mounted in the aircraft cabin. The holding device (40) is designed to attach the operating unit (1) in its state mounted in the aircraft cabin to the monument (30), in a first position or in a second position, as desired, the operating element (12, 14) in the second position of the operating unit (1) being situated in a spatial position which is lowered with respect to the spatial position of the operating element (12, 14) in the first position of the operating unit (1) and/or is displaced in a direction parallel to an imaginary straight line connecting the operating unit rear side (20) to the operating unit front side (10).

A resistance having a high impedance is connected between anode terminals of two variable capacitance diodes sharing a cathode, and the components described above are sealed in one package. The resistance can be formed of a diffusion region between p-regions of the variable capacitance diodes or can be formed of polysilicon and disposed on a chip. Thus, the resistance can be mounted while a chip size of the variable capacitance diode is maintained. Accordingly, it is not required that a bias resistance having a high impedance is additionally provided, whereby achieving reduction in the substrate mounting area and reduction in costs of the set.

The present invention provides an apparatus for enhancing Q factor of an inductor. The apparatus includes a negative resistance generator coupled to the inductor for providing a negative resistance, and a bias circuit coupled to the negative resistance generator for biasing the negative resistance generator.

The invention provides a variable tuning circuit capable of extending a variable range in a high frequency band, ensuring the value of L of an inductor to increase the value of Q of a circuit in a low frequency band, and preventing a reduction in gain, an increase in noise, and unstable oscillation. A variable tuning circuit includes: a first parallel resonance circuit that includes a varactor diode, a capacitor connected in series to the varactor diode, and a first inductor connected in parallel to the varactor diode and the capacitor; and a second parallel resonance circuit that includes a second inductor connected in parallel to the varactor diode with a direct current cut-off capacitor interposed therebetween. When the varactor diode has a maximum capacitance, a resonant frequency of the second parallel resonance circuit is set about a lowest frequency in a variable frequency range.

In a double-tuning circuit including a primary tuning circuit having a first inductor and a first variable capacitive element connected in parallel and a secondary tuning circuit having a second inductor and a second variable capacitive element connected in parallel, a fixed part of a copper-foil pattern is connected to a connection point at which the double-tuning circuit is connected to an input terminal of a frequency mixing circuit, and a tip part of the copper-foil pattern extends to near the first inductor, whereby a trap circuit for attenuating an image frequency component is formed. A pattern is formed between a ground-side terminal of the first inductor and the ground, and a capacitor is connected between a connection point at which the first inductor is connected to one terminal of the pattern and a ground-side terminal of the second variable capacitive element.

A tuner and a transformer formed by printed circuit board thereof are provided. The transformer includes a first winding and a second winding. In which, the first winding forms a first inductor and the second winding forms a second inductor. The transformer is formed by the first and the second inductors, wherein the first winding and the second winding are formed by conducting wires of a printed circuit board.

A method applied in a tuning circuit comprising a plurality of turning cells is disclosed. the method comprises: laying out a array of tuning cells in a matrix configuration, the matrix comprising a first dimension and a second dimension; assigning a first index associated with the first dimension and a second index associated with the second dimension to each tuning cell; controlling each tuning cell using a word line and a bit line; and summing up outputs from all tuning cells to form a combined output. The tuning cell provides a first circuit value or a second circuit value according to the logical value of the bit line, and the difference between the first circuit value and the second circuit value is determined such that a turning resolution of the tuning circuit is determined.

The tuner circuit comprises a HF input and a HF output with a loop through function, wherein a variable capacitance diode is coupled with a first terminal to the HF input and with a second terminal to the HF output for providing a passive loop through function. The variable capacitance diode is in particular in a passing mode, when no DC reverse voltage is applied, for providing a passive loop through function. In a preferred embodiment, the tuner circuit is designed for reception of television channels, and for the variable capacitance diode one or two tuning variable capacitance diode is used being designed for satellite tuners with a frequency range of 1-2 GHz, or a specially designed variable capacitance diode with a capacitance ratio C1/C25>18 at a frequency of 1 MHz for DC reverse voltages of 1 and 25 Volts is used.

A circuit (C1-C4) is employed in a TWACS transponder (T) installed in an electric meter (M). The transponder generates inbound signals (IB) transmitted from the location of the electric meter to a central location (R). Firmware (F) within the transponder controls the flow of current for each pulse through the circuit by triggering a semi-conductor device such as a SCR (X1) or TRIAC (X2). The resulting current flow through the inductor for a subsequent pulse, regardless of the pulse's polarity, will be in the opposite direction to that of the previous pulse. The result is to maintain a constant level of magnetization of the inductor core which does not have to be overcome by energy in the subsequent pulse resulting in amplitude of all the pulses imposed on an AC waveform being substantially the same.

A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Alloys and methods for preparing the same are provided. The alloys are represented by the general formula of (ZraAlbCucNid)100-e-fYeMf, wherein a, b, c, and d are atomic fractions, in which: 0.472≦a≦0.568; 0.09≦b≦0.11; 0.27≦c≦0.33; 0.072≦d≦0.088; the sum of a, b, c, and d equals 1; e and f are atomic numbers of elements Y and M respectively, in which 0≦e≦5 and 0.01≦f≦5; and M is selected from the group consisting of Nb, Ta, Sc, and combinations thereof.

A zirconium alloy nuclear reactor cylindrical cladding has an inner Zr substrate surface (10), an outer volume of protective material (22), and an integrated middle volume (20) of zirconium oxide, zirconium and protective material, where the protective material is applied by impaction at a velocity greater than 340 meters/second to provide the integrated middle volume (20) resulting in structural integrity for the cladding.

Disclosed is a zirconium alloy material having high corrosion resistance regardless of thermal history during its manufacturing process. The zirconium alloy material is obtained by providing a zirconium alloy containing on the mass basis: 0.001% to 1.9% of Sn, 0.01% to 0.3% of Fe, 0.01% to 0.3% of Cr, 0.001% to 0.3% of Ni, 0.001% to 3.0% of Nb, 0.027% or less of C, 0.025% or less of N, 4.5% or less of Hf and 0.16% or less of O with the remainder being inevitable impurities and zirconium, being formed of a bulk alloy and a surface layer, in which the surface layer has a plastic strain of 3 or more or a Vickers hardness of 260 HV or more and an arithmetic mean surface roughness Ra of 0.2 μm or less.

A method and apparatus for the display and transport of war gaming models, and more specifically a modular display system having interchangeable display and design panels to present and configure gaming figurines for competition and exhibition.

A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.

A quantum information processing system includes a waveguide having an aperture, a non-linear quantum circuit disposed in the waveguide and an electromagnetic control signal source coupled to the aperture.

To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.

A sequence circuit includes first through third signal terminals, first through ninth resistors, and first through fifth electronic switches. The sequence circuit receives a first signal through the first signal terminal. The sequence circuit receives a second signal through the second signal terminal. The sequence circuit outputs a third signal through the third signal terminal. The sequence circuit is used to ensure the sequence of the first through third signals.

A receiver circuit includes a first amplification unit, a second amplification unit, a first equalizing unit, and a second equalizing unit. The first amplification unit is configured to differentially amplify an input signal and a reference signal and generate a first intermediate output signal and a second intermediate output signal. The second amplification unit is configured to differentially amplify the first and second intermediate output signals and generate an output signal. The first equalizing unit is configured to control the level of the second intermediate output signal in response to the output signal. And the second equalizing unit is configured to control the level of the first intermediate output signal in response to the output signal.

Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

A storage cell having a pulse generator and a storage element is proposed. The storage element input is connected to receive a data input signal. The storage element output is connected to provide a data output signal. The storage element is operable in one of a data retention state and a data transfer state in response to a storage control signal received from the pulse generator. The pulse generator is connected to receive a clock signal with rising and falling clock signal edges and is adapted to provide control pulses in the storage control signal. Each control pulse has a leading edge and a trailing edge. The control pulses have a polarity suited to invoke the data transfer state on their leading edges. The novel feature is that the pulse generator is adapted to initiate a rising-edge control pulse when receiving a rising clock signal edge and to initiate a falling-edge control pulse when receiving a falling clock signal edge. In this way, a dual-edge-triggered flip-flop may be made using only combinatorial logic circuitry and one level- or single-edge-triggered storage element. The storage cell has low power consumption, facilitates scan testing and can be used by existing design tools and test equipment.

A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.

Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.

A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter. The first voltage clamp is configured to couple to a control terminal of the switch and limit a voltage of the control terminal relative to the first terminal to within a first clamping range. The circuit includes a second voltage clamp coupled to an input terminal of the switch control circuit. The second voltage clamp is configured to couple to the control terminal of the switch. The second voltage clamp is further configured to reduce a level of a control voltage coupled to the second voltage clamp. The circuit includes a bias device configured to couple to the control terminal of the switch and to impress a biasing voltage to the control terminal.

A semiconductor device prevents recognition failure in mutual recognition between a host and a device compliant with USB Specifications. The semiconductor device includes: an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded, in which the source or drain of a first-stage MOS transistor among the cascaded MOS transistors is used as a first terminal, the source or drain of a final-stage MOS transistor among the cascaded MOS transistors is used as a second terminal, and the respective gates of the cascaded MOS transistors receive a control signal for controlling the opening or short-circuiting between the first and second terminals; and a current bypass section that reduces a current flowing into either one connection node coupling the respective sources or drains of the cascaded MOS transistors.

The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

An electrical short circuit protection device for an electric trailer brake controller includes a fuse connected between the controller and the trailer brakes and an acoustic piezoelectric transducer connected across the fuse. Upon a short circuit fault developing in the trailer brakes, the fuse opens and the transducer generates an audio warning signal.

Disclosed is an organic light-emitting display device in which the substrate and the encapsulation substrate are attached to each other by using a frit. The organic light-emitting display device includes a first substrate including a pixel region in which an organic light-emitting diode is formed, and a non-pixel region. The organic light-emitting diode includes an organic light-emitting layer between a first electrode and a second electrode. A second substrate attached to the first substrate. A frit is provided between the non-pixel region of the first substrate and the second substrate to attach the first substrate and the second substrate. A reinforcement material of resin is formed outside the frit.

The present invention relates to a method of and a vertical pumping device (1) for internally distributing Hg in a fluorescent tube body (3). The bottom (7) of the fluorescent tube body (3) is closed. The device (1) arranges, in a first position, a first solid body (9') comprising a predetermined first amount of bound Hg. The device (1) arranges, in a second position, a second solid body (9″) comprising a predetermined second amount of bound Hg. A first release (E1) of the first amount of Hg is achieved in the fluorescent tube body (3) by gasification with heat and under pressure for purification of contaminant particles in the fluorescent tube body. A second release (E2) of the second amount of Hg is achieved in the fluorescent tube body (3) by gasification attained for the occluded mercury vapour of the fluorescent tube body (3).

An electron emission source includes nano-sized acicular materials and a cracked portion formed in at least one portion of the electron emission source. The acicular materials are exposed between inner walls of the cracked portion. A method for preparing the electron emission source, a field emission device including the electron emission source, and a composition for forming the electron emission source are also provided in the present invention.

A ferrous sulfide suspension that includes at least FeSm and Al(OH)3 and which can be used to reduce mercury emissions in flue gases. Through a combination of complex chemical reactions, precipitation, co-precipitation, and surface adsorption the ferrous sulfide suspension of the present invention effectively removes mercury from gaseous streams while concurrently preventing mercury re-emission.

System and method for sustainable economic development which includes hydrogen extracted from substances, for example, sea water, industrial waste water, agricultural waste water, sewage, and landfill waste water. The hydrogen extraction is accomplished by thermal dissociation, electrical dissociation, optical dissociation, and magnetic dissociation. The hydrogen extraction further includes operation in conjunction with energy addition from renewable resources, for example, solar, wind, moving water, geothermal, or biomass resources.

A system and methods for providing variable distribution and access control for purchased event tickets are described. In one embodiment, a network-based system receives an order for electronic tickets purchased by a buyer, receives one or more recipients other than the buyer for one or more of the electronic tickets, receives delivery options for the recipients from the buyer, receives delivery information for the recipients from the buyer, and delivers electronic ticket information to the recipients. Other embodiments are described and claimed.

A magnetic latch for industrial environments includes fixed magnetic pole pieces that may be sealed within a housing to resist environmental contamination and which provide for perpendicular engagement faces for use with gates having a rolling or swinging configuration. An RFID tag reader may be incorporated into the magnet assembly of the latch for reading a specially encoded RFID tag in a keeper portion of the magnetic latch.

Medical imaging equipment is provided. The medical imaging equipment comprises a support assembly, an arc-shaped member slidably mounted on the support assembly, a radiation source mounted on the arc-shaped member in the vicinity of a first distal end of the arc-shaped member and being oriented to radiate along the direction of an imaging axis, and a detector mounted on the arc-shaped member in the vicinity of the second distal end of the arc-shaped member and being oriented to face the source along the imaging axis, wherein the radiation source and the detector are respectively mounted on one side and the other of the mid plane of the arc-shaped member.

In a high-voltage apparatus according to this invention, a predetermined voltage is applied to a rotating anode after waiting until the number of rotations increases to such an extent that the rotating anode is not damaged. That is, X-rays of desired intensity are already outputted from a point of time when the voltage is applied to the rotating anode. Therefore, diagnosis can be performed immediately after the voltage is applied to the rotating anode. That is, unlike the prior art, there is no need to wait until X-ray intensity becomes suitable for diagnosis after X-ray emission is started, and there is no need to irradiate the patient with unnecessary X-rays. Therefore, the patient can be inhibited from being irradiated with excessive X-rays (with an improvement made in a response from when the operator gives instructions for starting fluoroscopy until emission of X-rays suitable for diagnosis).

A method is disclosed for energy calibrating quantum-counting x-ray detectors in an x-ray installation including at least two x-ray systems turnable around a center of rotation. A target, for producing x-ray fluorescence radiation, is positioned between the first x-ray source and first x-ray detector and irradiated with x-radiation of the first x-ray source in such a way that x-ray fluorescence radiation which strikes the second x-ray detector from the target is produced by the x-radiation of the first x-ray source. The second x-ray detector is then energy calibrated by way of the x-ray fluorescence radiation of the target. The first x-ray detector can be energy calibrated in the same way with the aid of the x-radiation of the second x-ray source. With the proposed method, the x-ray detectors of a dual-source CT x-ray installation can be calibrated with little expenditure under conditions close to those of the system.