Processing metadata includes storing, in a data storage system, a specification for each of multiple sources, each specification including information identifying one or more data elements of the corresponding source; and processing, in a data processing system coupled to the data storage system, data elements from the sources, including generating a set of rules for each source based on a corresponding one of the stored specifications, and matching data elements of different sources and determining a quality metric characterizing a given match between a first data element of a first source and a second data element of a second source according to the set of rules generated for the first source and the set of rules generated for the second source.

A system and method that facilitates urban traffic state detection based on support vector machine (SVM) and multilayer perceptron (MLP) classifiers is provided. Moreover, the SVM and MLP classifiers are fused into a cascaded two-tier classifier that improves the accuracy of the traffic state classification. To further improve the accuracy, the cascaded two-tier classifier (e.g., MLP-SVM), a single SVM classifier and a single MLP classifier are fused to determine a final decision for a traffic state. In addition, fusion strategies are employed during training and implementation phases to compensate for data acquisition and classification errors caused by noise and/or outliers.

Methods and arrangements for conducting a search using query logs. A query log is consulted and query rewrite rules are learned automatically based on data in the query log. The learning includes obtaining click-through data present in the query log.

Methods, systems, and computer-readable media for providing topical search suggestions are provided. Topical search suggestions allow a user to receive search results related to the designated topic or subject matter. The present invention may generate multiple topics based on search input provided by a user. The search input may be a search prefix that includes one or more words entered into the search query box before the completed search query is submitted to the search engine. A search interface then presents the topics derived from the search prefix to a user before the user submits the query. In another embodiment, the user designates multiple search inputs. The present invention generates search results based on the search inputs and then presents topics extracted from the search results. In one embodiment, the topics are extracted by performing a natural language analysis of search result metadata.

Disclosed is a process for reducing the amount of sterol in a sterol-containing microbial oil composition, including distilling, under short path distillation conditions, a sterol-containing microbial oil wherein said distillation produces a distillate fraction containing the sterol and a triacylglycerol-containing fraction having a reduced amount of the sterol when compared to the amount of sterol in the sterol-containing microbial oil composition that has not been subjected to short path distillation.

A long-fiber-reinforced resin composition including (A) a long-fiber-reinforced thermoplastic resin pellet including a thermoplastic resin, a modified polyolefin-based resin modified with an unsaturated carboxylic acid or its derivative and reinforcing fiber and satisfying (A-1) the melt index of the thermoplastic resin is 100-250 g/10 min, (A-2) the relaxation time λ of the thermoplastic resin is 0.1 (sec) or less, (A-3) the content of the reinforcing fiber is 40-70 wt %, and (A-4) the content of the modified polyolefin-based resin is 1-5 wt %; and (B) a polyolefin-based resin satisfying (B-1) the melt index of the polyolefin-based resin is 20-70 g/10 min, and (B-2) the relaxation time λ of the polyolefin-based resin is 0.23 (sec) or less; wherein the content of reinforcing fiber contained in (A) is 20-60 wt % relative to the total amount of the fiber-reinforced resin composition.

A process for producing an alkali metal cyclopentadienylide is disclosed which comprises reacting in a solvent an alkali metal hydride with a disubstituted or trisubstituted 1,3-cyclopentadiene. Further, a process for producing a dihalobis(η-substituted-cyclopentadienyl)zirconium is disclosed which comprises reacting a zirconium halide with the above alkali metal cyclopentadienylide. The former process enables performing the reaction between the disubstituted or trisubstituted 1,3-cyclopentadiene and the alkali metal hydride at an easily controllable temperature of room temperature to about 150° C. and also enables obtaining the alkali metal cyclopentadienylide in high yield. The latter process enables obtaining the dihalobis(η-substituted-cyclopentadienyl)zirconium in high yield.

Methods for forming lead zirconate titanate (PZT) nanoparticles are provided. The PZT nanoparticles are formed from a precursor solution, comprising a source of lead, a source of titanium, a source of zirconium, and a mineralizer, that undergoes a hydrothermal process. The size and morphology of the PZT nanoparticles are controlled, in part, by the heating schedule used during the hydrothermal process.

The invention relates to a granulated powder intended, in particular, for the production of ceramic sintered parts, said powder having the following chemical weight composition, based on dry matter, namely: a zirconia stabiliser selected from the group containing Y2O3, Sc2O3, MgO, CaO, CeO2, and mixtures thereof, the weight content of stabiliser, based on the total zirconia and stabiliser content, being between 2% and 20% and the MgO+CaO content being less than 5% based on the total zirconia and stabiliser content; at least 1% of a first binder having a glass transition temperature less than or equal to 25° C.; 0-4% of an additional binder having a glass transition temperature greater than 25° C.; 5-50% alumina; 0-4% of a temporary additive different from the first binder and the additional binder, the total content of the first binder, the additional binder and the temporary additive being less than 9%; less than 2% impurities; and ZrO2 to make up 100%. According to the invention, the median diameter D50 of the powder is between 80 and 130 μm, the percentile D99.5 is less than 500 μm and the relative density of the granules is between 30% and 60%.

A facile synthesis of amphiphilic hyperbranched polymers consisting of poly(amic acid) and polyimide was developed via “A2+B3” approach from difunctional anhydride and trifunctional hydrophilic poly(oxyalkylene)triamine. Various amphiphilic hyperbranched poly(amic acid)s (HBPAAs) with terminal amine functionalities and amic acid structures were prepared through ring-opening polyaddition at room temperature, followed by thermal imidization process for the formation of hyperbranched polyimides (HBPIs), accordingly. The resulting HBPIs were analyzed by GPC, indicating the molecule weights of 5000˜7000 g/mol with a distribution of polydispersity between 2.0 and 3.8. The amine titration for HBPIs indicated the peripheral total-amine contents to be 8.32˜18.32 mequiv/g dependent on compositions.

A computing system resource recovery method can include identifying a resource manager associated with a computing transaction, classifying the computing transaction to determine a predetermined metric, measuring an actual metric of the computing transaction, comparing the predetermined metric to the actual metric to detect abnormal behavior in the transaction and modeling the abnormal behavior to determine how the resource manager is affected by the abnormal behavior.

Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. Test wrappers may also be configured to test multiple IP blocks comprising a test partition.

Data is compressed using content addressable memory without disruption despite error using a plurality of content addressable memories to detect sequentially repeating data elements of the data. Compression information is generated for each sequence of repeating data elements that repeat for at least a compression threshold without any one of the plurality of content addressable memories generating an indication of an error for a matching content addressable memory entry. Individual data elements are output for each of the data elements that do not repeat for the compression threshold. Compression information is generated for each sequence of repeating data elements that repeat for at least the compression threshold and then generating a currently searched data element that matches the repeating data elements when any one of the plurality of content addressable memories generates an indication of an error for a content addressable memory entry that matches the currently searched data element.

A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.

A two step process for the destruction of a precursor material using a steam plasma in a three zone reactor wherein the precursor material is hydrolyzed as a first step in the high temperature zone of the reactor, followed by a second step of medium temperature oxidation of the reactant stream in the combustion zone of the reactor where combustion oxygen or air is injected and immediate quenching of the resulting gas stream to avoid the formation of unwanted by-products. A related apparatus includes a non transferred direct current steam plasma torch, an externally cooled three zone steam plasma reactor means for introducing the precursor material into the plasma plume of the plasma torch, means for introducing the combustion air or oxygen into the combustion zone, means for exiting the reactant mixture from the reactor and means for quenching the reactant mixture located at the exit end of the reactor.

A treatment system and a method for removal of at least one halogenated compound, such as PCBs, found in contaminated systems are provided. The treatment system includes a polymer blanket for receiving at least one non-polar solvent. The halogenated compound permeates into or through a wall of the polymer blanket where it is solubilized with at least one non-polar solvent received by said polymer blanket forming a halogenated solvent mixture. This treatment system and method provides for the in situ removal of halogenated compounds from the contaminated system. In one embodiment, the halogenated solvent mixture is subjected to subsequent processes which destroy and/or degrade the halogenated compound.

Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

Systems and methods are provided for generating at least one high fidelity resource state. A classical code and punctured to provide a first set of generators and a second set of generators. The first set of generators is mapped to a set of stabilizer generators, and the second set of generators is mapped to a set of logical operators. A set of resource states are prepared in physical qubits. A decoding process is performed on the resource states according to a quantum code represented by the set of stabilizer generators and the set of logical operators, and qubits corresponding to the stabilizers are measured.

A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. This encoding scheme allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for an implementation adapted to shift a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.

A communication device includes a storage unit to store quotients and remainders associated with multiplication values obtained by multiplying a specified integer number, which is expressed in a form of (2β+α) where β is a positive integer number and α is a positive integer number other than integral multiples of 2, respectively, the quotients and the remainders being obtained by dividing the multiplication values by 2β, respectively, a first unit to divide a dividend by 2βand calculate a quotient and a remainder, a second unit to obtain a quotient, which corresponds to the remainder from the storage unit, and a third unit to determine that the data length of the packet data is normal, when a combination of the quotient and the remainder calculated by the first unit is in the storage unit.

A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.

An electronic device, including: one or more hardware interfaces each for connecting to a signal source to receive at least one type of application resources; a control chip electrically connected to the one or more hardware interfaces, the control chip being configured to classify and integrate one or more types of application resources received through the one or more hardware interfaces, and generate a display signal for a main interface including a number of areas arranged according to a predetermined layout, wherein each area is configured to display information regarding a same type of the classified and integrated application resources, and different areas are configured to display information regarding different types of the classified and integrated application resources; and a display screen electrically connected to the control chip to display the main interface according to the display signal.

A bridge circuit of an embodiment includes: a command transfer portion which is configured by wired logic into which a host controller capable of sending a command that corresponds to each of a plurality of devices inputs the command, and which is configured to transfer the inputted command to the plurality of devices; a command analysis portion which is configured by wired logic, and which is configured to analyze the command from the host controller; and a response reply portion which is configured by wired logic, and which is capable of reading out a response based on an analysis result of the command analysis portion from a register that holds a response corresponding to the command and sending the response to the host controller.

A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane.

Embodiments of the invention provide systems and methods for managing an enabler and dependencies of the enabler. According to one embodiment, a method of managing an enabler can comprise requesting a management function via a management interface of the enabler. The management interface can provide an abstraction of one or more management functions for managing the enabler and/or dependencies of the enabler. In some cases, prior to requesting the management function metadata associated with the management interface can be read and a determination can be made as to whether the management function is available or unavailable. Requesting the management function via the management interface of the enabler can be performed in response to determining the management function is available. In response to determining the management function is unavailable, one or more alternative functions can be identified based on the metadata and the one or more alternative functions can be requested.

A cloud system may create physical resource tags to store relationships between cloud computing offerings, such as computing service offerings, storage offerings, and network offerings, and the specific physical resources in the cloud computing environment. Cloud computing offerings may be presented to cloud customers, the offerings corresponding to various combinations of computing services, storage, networking, and other hardware or software resources. After a customer selects one or more cloud computing offerings, a cloud resource manager or other component within the cloud infrastructure may retrieve a set of tags and determine a set of physical hardware resources associated with the selected offerings. The physical hardware resources associated with the selected offerings may be subsequently used to provision and create the new virtual machine and its operating environment.

A system and method for reordering storage levels in a virtualized environment includes identifying a virtual machine (VM) to be transitioned and determining a new storage level order for the VM. The new storage level order reduces a VM live state during a transition, and accounts for hierarchical shared storage memory and criteria imposed by an application to reduce recovery operations after dynamic resource allocation actions. The new storage level order recommendation is propagated to VMs. The new storage level order applied in the VMs. A different storage-level order is recommended after the transition.

An electronic device for using pause to manage resources is described. The electronic device includes a processor and instructions stored in memory. The electronic device monitors a pause duration and determines whether to perform a resource management operation based on the pause duration. The electronic device performs the resource management operation based on the pause duration.

A usage allocation of a hardware resource to each of a number of workloads over time is determined using a demand model. The usage allocation of the resource includes a current and past actual usage allocation of the resource, a future projected usage allocation of the resource, and current and past actual usage of the resource. A capacity allocation of the resource is determined using a capacity model. The capacity allocation of the resource includes a current and past capacity and a future projected capacity of the resource. Whether a gap exists between the usage allocation and the capacity allocation is determined using a mapping model. Where the gap exists between the usage allocation of the resource and the capacity allocation of the resource, a user is presented with options determined using the mapping model and selectable by the user to implement a remediation strategy to close the gap.

The technology of the present application provides a networked computer system with at least one workstation and at least one shared resource such as a database. Access to the database by the workstation is managed by a database management system. An access engine reviews job requests for access to the database and allows job requests access to the resource based protocols stored by the system.

Policy enforcement in an environment that includes virtualized systems is disclosed. Virtual machine information associated with a first virtual machine instance executing on a host machine is received. The information can be received from a variety of sources, including an agent, a log server, and a management infrastructure associated with the host machine. A policy is applied based at least in part on the received virtual machine information.

Methods and apparatus are provided for evaluating potential resource capacity in a system where there is elasticity and competition between a plurality of containers. A dynamic potential capacity is determined for at least one container in a plurality of containers competing for a total capacity of a larger container. A current utilization by each of the plurality of competing containers is obtained, and an equilibrium capacity is determined for each of the competing containers. The equilibrium capacity indicates a capacity that the corresponding container is entitled to. The dynamic potential capacity is determined based on the total capacity, a comparison of one or more of the current utilizations to one or more of the corresponding equilibrium capacities and a relative resource weight of each of the plurality of competing containers. The dynamic potential capacity is optionally recalculated when the set of plurality of containers is changed or after the assignment of each work element.

Methods of increasing the solubility of a base in supercritical carbon dioxide include forming a complex of a Lewis acid and the base, and dissolving the complex in supercritical carbon dioxide. The Lewis acid is soluble in supercritical carbon dioxide, and the base is substantially insoluble in supercritical carbon dioxide. Methods for increasing the solubility of water in supercritical carbon dioxide include dissolving an acid or a base in supercritical carbon dioxide to form a solution and dissolving water in the solution. The acid or the base is formulated to interact with water to solubilize the water in the supercritical carbon dioxide. Some compositions include supercritical carbon dioxide, a hydrolysable metallic compound, and at least one of an acid and a base. Some compositions include an alkoxide and at least one of an acid and a base.

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

In a multiprocessor system, in general, a processor assigned with a larger amount of tasks is apt to perform a larger amount of communication with other processors assigned with tasks, than a processor assigned with a smaller amount of tasks. Thus in order for each processor to be able to perform the routing process efficiently, tasks are assigned such that, when there are a first processor and a second processor, the number of processors each assigned with one or more tasks and directly connected with the second processor being smaller than the number of processors each assigned with one or more tasks and directly connected with the first processor, the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.

A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction.

A framework for implementing multitenant architecture is provided. The framework comprises a framework services module which is configured to provide framework services that facilitate abstraction of Software-as-a-Service (SaaS) services and crosscutting services for a Greenfield application and a non SaaS based web application. Further the abstraction results in a SaaS based multitenant web application. The framework further comprises a runtime module configured to automatically integrate and consume the framework services and APIs to facilitate monitoring and controlling of features associated with the SaaS based multitenant web application. The framework further comprises a metadata services module configured to provide a plurality of metadata services to facilitate abstraction of storage structure of metadata associated with the framework and act as APIs for managing the metadata. The framework further comprises a role based administration module that facilitates management of the metadata through a tenant administrator and a product administrator.

Systems and methods for static code scheduling are disclosed. A method can include receiving an intermediate representation of source code, building a directed acyclic graph (DAG) for the intermediate representation, and creating chains of dependent instructions from the DAG for cluster formation. The chains are merged into clusters and each node in the DAG is marked with an identifier of a cluster it is part of to generate a marked instruction DAG. Instruction DAG scheduling is then performed using information about the clusters to generate an ordered intermediate representation of the source code.

An aspect of the present invention identifies differences between source codes (e.g. of different versions of a software), when each source code is organized using incorporated files. In one embodiment, in response to receiving identifiers of a first and second source codes (each source code being organized as a corresponding set of code files), listings of the instructions in the first and second source codes are constructed. Each listing is constructed, for example, by replacing each incorporate statement in the source code with instructions stored in a corresponding one of code files. The differences between the first and second source codes are then found by comparing the constructed listings of instructions.

An information processing system, computer readable storage medium, and method for automatically generating human readable and meaningful documentation for one or more source code files. A processor of the information processing system receives one or more source code files containing source code artifacts (SCA) and infers semantics therefrom based on predefined rules. The processor, based on the inferred semantics, extracts documentation from another source code file. The extracted documentation and the inferred semantics are used to generate new human readable and meaningful documentation for the SCA, such new documentation being previously missing from the SCA. The generated new documentation is included with the SCA in one or more source code files.

The present invention relates generally to client-server architectures for allowing generic upload and download functionality between a web application at a server and a client. One exemplary method includes sending a download/upload request to a web application at the server, where the download/upload request specifies at least one file to download/upload; receiving a transmission from the server; parsing the transmission to identify a download/upload command and an associated download/upload manifest, where the download/upload manifest includes executable code that, when executed on the client, will perform the download/upload of the at least one file.

A navigation system and various methods of using the system are described herein. Search query results are refined by the system and are prioritized based at least in part upon sub-search categories selected during the searching process. Sub-searches can be represented by graphical icons displayed on the user interface.

A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.

This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.