A transport stream (TS) generating apparatus, a transmitting apparatus, a receiving apparatus, a digital broadcast system having the above, and a method thereof are provided. The digital broadcast system includes a transport stream (TS) generating apparatus which generates a multi transport stream (TS) by multiplexing a normal stream and a turbo stream having a variable coding rate, a transmitting apparatus which re-constructs the multi TS by processing the turbo stream, and transmits the re-constructed multi TS, and a receiving apparatus which receives the re-constructed multi TS, and decodes the normal stream and the turbo stream respectively, to recover normal data and turbo data. Accordingly, a multi TS, which includes normal stream and a turbo stream of various coding rates, can be transmitted and received efficiently.

Generating a digital-media-enhanced electronic record of a locate and/or marking operation performed by a locate technician. The locate and/or marking operation comprises locating and/or identifying, using at least one physical locate mark, a presence or an absence of at least one underground facility within a dig area, wherein at least a portion of the dig area may be excavated or disturbed during excavation activities. A location of the at least one underground facility and/or the at least one physical locate mark is electronically rendered on a display device so as to generate an electronic visual representation of the locate and/or marking operation. At least one digital media file representation of a corresponding digital media file relating to at least one aspect of the locate and/or marking operation or an environment of the dig area is also electronically rendered on the display device, so as to generate a digital-media-annotated representation of the locate and/or marking operation. Information relating to the digital-media-annotated representation of the locate and/or marking operation is electronically transmitted and/or stored so as to generate the digital-media-enhanced electronic record of the locate and/or marking operation.

The rotary electrical machine is capable of functioning as a generator and outputs a continuous output voltage (Ub+) that is adjustable by an excitation current. The digital regulator (2) of the machine comprises an excitation current control means (7) and a control loop (6) that includes a device (10) for measurement, by sampling, of the output voltage (Ub+), the measurement device generating a signal sampled at a predetermined first sampling frequency (F1 e). The machine has a bandwidth that is limited by a predetermined first cutoff frequency (F1 c). The measurement device includes an apparatus for oversampling such that the first sampling frequency (F1 e) is greater than twice the first cutoff frequency (F1 c), and the control loop also includes an apparatus (12) for decimating the sampled signal.

An amplifier receives an amplitude signal of a polar modulated signal at a base terminal of a transistor and receives a phase modulated carrier signal of the polar modulated signal at the base terminal of the transistor. The amplifier combines the amplitude signal and the phase modulated signal to produce a full complex waveform at a collector terminal of the transistor.

A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.

A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one resistance-capacitance (RC) detection result, wherein the digital compensation filter includes an RC compensation module; and tuning the digital compensation filter by inputting the RC detection result into the RC compensation module. For example, the RC detection result may correspond to a detected value representing a product of a resistance value and a capacitance value. In another example, the at least one RC detection result may be obtained by performing RC detection on at least a portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein. An associated digital compensation filter and an associated calibration circuit are also provided.

A digital pulse width modulation controller includes a pulse width modulation controller, a selection unit having at least one selector, a comparison unit having at least one comparator, and a signal conversion unit having at least one digital-to-analog converter. The digital-to-analog converter generates a reference current and/or voltage. The comparator receives the reference current and/or voltage, and performs a comparison operation to generate a comparison signal based on a feedback signal. The selector selects one selection signal to input into the pulse width modulation controller, which receives other parameters set by a user or the system at the same time so as to control characteristics of the digital pulse width modulation signals, thereby improving the electric properties of a loading circuit.

A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

Embodiments of digital high-speed bi-phase modulator and method for bi-phase modulation are generally described herein. In some embodiments, the digital high-speed bi-phase modulator comprises a high-speed digital divider, a high-speed digital multiplexer, and matched signal paths provided between the divider and the multiplexer. The high-speed digital divider is configured to receive a carrier signal and generate complementary output signals. The high-speed digital multiplexer is configured to switch between the complementary output signals and generate a bi-phase modulated output at a carrier frequency (fc) modulated with a bi-phase code. The bi-phase code may be provided to control inputs of the multiplexer.

The present invention relates to a digital modulation method and a corresponding modulator. The modulator comprises a transcoder (110) followed by a FIFO register (120) and a 2-PSK modulator (130). The transcoder codes a binary word of fixed size into a code word of variable size using a transcoding table. The transcoding table codes at least one first binary word, leading to a first number of phase transitions at the output of the modulator, into a second word of size greater than that of the first word, leading to, at the output of the modulator, a second number of phase transitions less than the first number of phase transitions.

The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.

A memristor-based emulator including a memristor circuit for use in digital modulation that includes a first current feedback operational amplifier (CFOA) having multiple terminals in communication with a capacitor Cd and in further communication with a resistor Ri. A second CFOA having multiple terminals is in communication with the first CFOA and is adapted to be in further communication with a voltage vM to provide an input current iM for integration by a capacitor Ci. A nonlinear resistor is in communication with the second CFOA. A third CFOA having multiple terminals is in communication with the nonlinear resistor and is in further communication with the first CFOA and a resistor Rd. The third CFOA and the resistor Rd act as an inverting amplifier associated with the nonlinear resistor to increase a current gain to increase a difference between ON and OFF values of a resistance of a realized memristor.

An analog-to-digital converter can use a variable sampling rate. By using a variable sampling rate analog-to-digital converter and an anti-aliasing filter lower sampling rates, and accordingly, generally lower power consumption may be achieved. For example, a lower sampling rate can be used when it is determined that no undesirable signals are present and a higher sampling period can be used when an undesirable signal is present. Determining the presence of an undesired signal can be based on signal-to-noise ratio, over-sampling, bit error rate, using a detector, etc. An undesirable signal can be any signal that is close in frequency to a signal of interest or a signal farther away in frequency that has a relatively high amplitude. Sampling rate can be varied in a binary fashion, stepwise, continuously, etc.

Circuits and processes for detecting a peak value of an input signal are disclosed. In one example, a peak detector circuit may sample a line sense signal, determine the peak value of the line sense signal during a search window, and output a peak detection signal representative of the determined peak value. In a first mode, the peak detector circuit may cause the peak detection signal to be representative of the determined peak value from an immediately preceding search window. In a second mode, the peak detector circuit may cause the peak detection signal to follow the sampled line sense signal. The peak detector circuit may operate in the second mode in response to the sample of the line sense signal being greater than a peak value of the line sense signal from an immediately preceding search window by more than a threshold amount.

A system and method for interactively producing a 3D representation of a vector graphic is disclosed. A vector graphic representing a 2D graphic having a number of endpoints joined by vector segments is automatically or interactively converted into a triangulated mesh in a form readable by a 3D printer. The conversion from vector graphic to a triangulated mesh is accomplished by generating an n-sided polygon in the vicinity of each endpoint of the vector graphic. Each of the vertices of the polygon are then be joined by a line to a corresponding vertex on the next adjacent polygon. Each vertex is also joined to an adjacent vertex on the next adjacent polygon. The process is continued until all polygons are joined, resulting in a triangulated mesh, which is then converted into a format readable by a 3D printer and sent to a 3D printer to produce the 3D representation.

A communication system for communicating with at least one loudspeaker is described where the loudspeaker is connected to audio equipment over standard two-wire speaker wire operable to carry an audio signal. The communication system includes a master node in electrical communication with a signal path carrying the audio signal between the audio equipment and the loudspeaker, the master node also including an interface with the audio equipment, a data encoder operable to encode data signals, a data transceiver operable to place the data signals onto the audio signal at frequencies above audio frequencies. The communication system also includes at least one slave node in electrical communication with the audio signal and each loudspeaker, the slave node including a data transceiver operable to receive data signals from the master node, a data decoder, and an interface able to communicate with the loudspeaker.

A digital sheet-fed printing method includes providing one cycle of printing to print on a series of sheets of paper whose number is equal to the least common multiple of respective numbers of allocated positions; producing a reference signal on the basis of which an image in each color is printed on the sheet of paper; detecting with an image detection sensor means a mutual out of register between images in different colors printed on each sheet of paper in the series, furnishing the printing control means with a detection signal for each sheet of paper from the image detection sensor, and correcting the timing at which each image is printed on each sheet of paper in one cycle of printing so that timings to print the images in different colors on each sheet of paper coincide with one another; and printing images in the different colors.

A system for dampening fluid recovery in an ink-based digital printing system includes a seal manifold having a front seal portion, the front seal portion having an upper wall facing the imaging surface, the upper wall being configured to define an air flow channel with the imaging surface, the upper wall being contoured to form a distance between the upper wall and the imaging surface at an evaporation location that is less than distance between the upper wall and the imaging surface at locations interposing the evaporation location and a vacuum inlet channel of the seal manifold.

A system and corresponding methods are disclosed for depositing of a layer of dampening fluid to a reimageable surface of an imaging member in a variable data lithography system by way of condensation. Dampening fluid in an airborne state is introduced proximate the reimageable surface in a condensation region. Conditions in the condensation region are such that the airborne dampening fluid preferentially condenses on the reimageable surface in a precisely controlled quantity, to thereby form a precisely controlled layer of dampening fluid of desired thickness over the reimageable surface. Among other advantages, improved print quality is obtained.

The embodiments herein disclose a method and a system for creating a singular platform to harness a plurality of technical capabilities in order to deliver multiple digital services such as end user device management, analytics, enterprise mobility, digital identity management, smart device management and so on by orchestrating certain service related support capabilities. The embodiments function as an interface between the user equipment and the applications that are running on several operating systems. Further, an enablement platform is created and modified for a digital ecosystem that sits on the network and user equipment to act as an interface. Essentially, a flexible and extensible API driven platform capable of seamlessly integrating multiple platforms spanning across network services and functions, analytics, device management and orchestration platforms in enabled.

Disclosed is a digital frame cover comprised of two basic components which are utilized in conjunction with each other to decorate the front perimeter of a digital frame. The two primary components of the digital frame cover being (1) a hollow rectangular cover comprising cutouts at various locations, and (2) a “decorative wrap” of interior dimensions which allow the decorative wrap to fit snugly over the exterior of the cover. The cover slides/snaps onto the digital frame. The decorative wrap adheres to, or is magnetically attached to the cover. At the user's prerogative, the decorative wrap may be configured to display one or more of a selection of user-selected designs (i.e., wording, pictures, or appliqués).

A control and measurement system for a coriolis flowmeter having a flowtube, a driver adapted to vibrate the flowtube, and a pair of sensors adapted to generate signals indicative of movement of the flowtube when it is being vibrated by the driver, wherein the sensors are positioned relative to one another so the signals from the sensors are indicative of a mass flow rate of fluid through the flowtube. A digital drive signal generator is adapted to generate a variable digital drive signal for controlling operation of the driver. The digital drive signal generator can be adapted to cause the driver to resist motion of the flowtube during a first time period and amplify motion of the flowtube during a second time period. The digital drive signal generator can also be adapted to initiate motion of the flowtube by sending one or more square wave signals to the driver.

In one example, a method for controlling a display with a digital signal includes detecting a binary value from a timing controller, the binary value corresponding to a portion of an image to be displayed. The method can also include determining a previous binary value from the timing controller and calculating a difference between the binary value from the timing controller and the previous binary value from the timing controller. Furthermore, the method can include generating an encoded signal based on the difference and transmitting the encoded signal to a display panel.

A shock absorber is disclosed having a pressure tube forming a working chamber, and a piston assembly slidably disposed within the pressure tube. The piston assembly may divide the working chamber into upper and lower working chambers. The piston assembly may have a piston body defining a first fluid passage extending therethrough and a first valve assembly controlling fluid flow through the first fluid passage. A second fluid passage, separate from the first fluid passage, extends from one of the upper and lower working chambers to a fluid chamber defined at least in part by the pressure tube. A plurality of digital valve assemblies are included and configured to exclusively control all fluid flow through the second fluid passage, and thus all fluid flow between the one of the upper and lower working chambers to the fluid chamber.

An angle measuring device or system can include a wrench and a digital angle meter. The wrench can include a head for engaging a fastening device, a central axis about which the wrench or bracket rotates during use, and a longitudinal axis perpendicular to the central axis. The digital angle meter can be attached to the wrench or bracket and include a housing, a processor, and at least one gyrometer. The at least one gyrometer including a first axis extending parallel to the longitudinal axis for determining the rotational orientation of the wrench or bracket relative to a reference position. A sensor of the digital angle meter allows for an automated and accurate calculation of a total angle of rotation of the nut or bolt about the central axis using a ratcheting wrench.

A digital down converter with an equalizer translates an ADC output signal to a low frequency spectral region, followed by decimation. All operations of correction of the processed signal are carried out with a reduced sampling rate compared with sampling rates of the prior art. Equalization is performed only in a frequency pass band of the down converter. The achieved reduction of the required computation resources is sufficient to enable the down converter with equalization to operate in a real time mode.

A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.

A method for adaptively regulating a coding mode and a digital correction circuit thereof are provided. The method is for a successive-approximation-register analog-to-digital converter (SAR ADC). In the method, whether to regulate a binary weight corresponding to each of digital bits is determined according to the number of completed comparison cycles to provide a first coding sequence. The first coding sequence is directly compensated according to uncompleted comparison cycles to provide a correct digital output code.

An input buffer for an ADC is provided. The input buffer includes a receiving circuit and an impedance circuit. The receiving circuit is coupled between a power supply and a sample-and-hold circuit of the ADC, and receives an analog input signal and generating an analog signal. The impedance circuit is coupled to the receiving circuit, and selectively provides a variable impedance. When the sample-and-hold circuit of the ADC is operated in a first phase, the impedance circuit provides a small impedance, and when the sample-and-hold circuit of the ADC is operated in a second phase, the impedance circuit provides a large impedance.

A digital-to-analog converter (DAC) and a high-voltage tolerance circuit are provided. The DAC includes a high-voltage tolerance circuit. The high-voltage tolerance circuit is configured to generate a reference voltage, and select the reference voltage or a first power-source voltage to control the node voltage of each branch of an operational amplifier circuit of the high-voltage tolerance circuit according the logical signal level of an input signal.

An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine timing mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology utilizes cross-correlation of each DAC unit elements (UEs) output to the entire modulator output to measure its timing mismatch error respectively. Specifically, the timing mismatch error is estimated using a ratio based on a peak value and a value for the next tap in the cross-correlation function. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine switching mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology forces each DAC unit elements (UEs) to switch a certain amount times and then use the modulator itself to measure the errors caused by those switching activities respectively. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

Typically, complex systems require a separate and expensive equalizer at the output of an analog-to-digital converter (ADC). Rather than providing a separate equalizer, the effective Signal Transfer Function (STF) of a Multi-stAge noise SHaping (MASH) ADC can be modified by leveraging available digital filtering hardware necessary for quantization noise cancellation. The modification can involves adding calculations in the software previously provided for computing digital quantization noise cancellation filter coefficients, where the calculations are added to take into account equalization as well. As a result, the signal transfer function can be modified to meet ADC or system-level signal-chain specifications without additional equalization hardware. The method is especially attractive for high-speed applications where magnitude and phase responses are more challenging to meet.

For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.

An analog-to-digital converter (ADC) is a device that can include a reference shuffler and a loop filter. An ADC can achieve better performance with incremental adjustment of a pointer of the reference shuffler, changing coefficients of the loop filter, and storing calibration codes of the ADC in a non-volatile memory. By incrementally adjusting a pointer of the reference shuffler, a calibration can be performed more efficiently than with a random adjustment of the pointer. By temporarily changing the loop filter coefficients, a greater amount of activity can be introduced into the loop filter. This activity can allow the calibration to proceed more efficiently. By storing the calibration codes in a non-volatile memory, a search space for calibration codes can be reduced. Thus, a calibration can occur more quickly, and the calibration itself can be improved.

An analog to digital converter includes an error integration circuit configured to receive an input charge from a detector and to integrate a difference between the input charge and one or more feedback charge pulses to create an error voltage. A quantizer is in operable communication with the error integration circuit and is responsive to the created error voltage. An accumulator having a mantissa component and a radix component is in operable communication with the quantizer. A charge feedback device in operable communication with the quantizer and the radix component of the accumulator. The charge feedback device is configured to generate the one or more feedback charge pulses proportional to the radix component of the accumulator and an output of the quantizer. Digital focal plane read out integrated circuits including the analog to digital converter are also disclosed.

The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

A circuit and a method for converting an analog signal to a digital value representation is disclosed. In one aspect, the circuit includes an incremental sigma-delta analog-to-digital converter (ADC). The circuit further includes a first input line for providing a primary analog signal representing a sensor measurement to the incremental sigma-delta ADC. The circuit further includes a second input line for providing a secondary analog signal to the incremental sigma-delta ADC. The incremental sigma-delta ADC receives the primary and secondary analog signals during a first period (TADC1) and a second period (TADC2), respectively. The circuit further includes a filter configured to weight the digital values in a sequence of digital values output by the incremental sigma-delta ADC, and to output a single digital value representing the sensor measurement.

System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

A potentiostat/galvanostat employs a controller for providing digital control signals to a digital-to-analog converter (DAC) that generates an analog output signal in response to digital control signals. A high current driver produces a high current output in response to the analog output signal from the DAC. A high current monitor monitors the output from the high current driver to produce a feedback signal for the high current driver to control the current produced by the high current driver and to produce an output dependent on the current supplied from the high current driver for monitoring by the controller. A counter electrode contact for a counter electrode is connected with the output of the high current monitor. A working electrode contact for a working electrode is electrically connected with a fixed stable voltage potential to enable electrochemical analysis of material between the counter electrode and the working electrode. A low current driver produces a low current range output in response to an analog output signal from the DAC. A low current monitor monitors the working electrode contact to detect current at the working electrode contact to supply an output dependent on the current detected for monitoring by the controller and for providing a feedback signal to the low current driver in order to control the output of the low current driver to control current between the counter electrode contact and the working electrode contact.

An assay system and method for use in the field of chemical testing is disclosed. The assay system can be used for filtering whole blood for testing on an integrated circuit containing digital control functionality.

A NEW digital publication will allow Hampshire Cultural Trust to keep its doors open online.

Slate Digital just released the Virtual Mix Rack plugin and while I was trying it out I made a quick demo video. I’m using presets…

The actor playing Neal Caffrey in the crime drama series has reconnected with castmates, including Tim DeKay, Hilarie Burton, Willie Garson and Tiffani Thiessen, and creator Jeff Eastin, in a livestream.

The actor playing Neal Caffrey in the crime drama series has reconnected with castmates, including Tim DeKay, Hilarie Burton, Willie Garson and Tiffani Thiessen, and creator Jeff Eastin, in a livestream.

Richard Lutz rifles through his electronic life to find out who he is.

Imagine a 30 foot high Ariel towering above Propero - that’s what you get in this groundbreaking performance, says Richard Lutz

Updates Media move into social first media, content & publishing.