Today, we are living in the era where whatever we think of as an idea is not far from being implemented…thanks to machine learning (ML) and artificial intelligence (AI) entering into the...

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Complexity is driving the urgency for advanced artificial intelligence systems more than ever—and that means someone has to supply the tools to create those systems. Cadence is up to the task: we’ve been expanding our AI offerings. If you haven’t already seen what Cadence can do for your AI needs, or if you’re not quite up-to-date on this whole AI boom, let this presentation given by K.T. Moore at the Cadence Theater at DAC bring you up to speed.

The technology behind AI isn’t as new as you’d think—the principles that govern how AI learns have been in development since 1959, when Arthur Samuel defined the concept of “machine learning.” At the time, there was nothing even resembling the necessary compute power to put Samuel’s concepts into practice—but now we can. AI designs are huge, and they’re massively parallel—simulating them on older computers and simulators would have taken ages; never mind how long it would take to do some by-hand measure like they had to do in the '60s.

But with advancements in server technology and the parallelization technology in products like Xcelium Parallel Logic Simulator and JasperGold smart technology, plus hardware-based engines like the Palladium and Protium platforms, verifying AI designs is not only possible—it’s easy.  But, read on, its not just about simulation technology.

AI tech is flooding the industry. It’s applicable to almost every vertical—cloud computing can use AI to intelligently manage a user’s required resources, consumer electronics are using it to tailor a user experience based on a whole host of collected data, automotive companies want to use AI to drive cars, healthcare to assist in diagnoses given a set of symptoms and a database of other, similar patients—and that’s saying nothing of the multitude of industrial applications. AI is also useful in the creation of developers’ tools themselves. Part of what’s causing the semiconductor industry boom is just this—an exploding interest in AI chips. And with 5G technology imminent, and with the looming billion-gate plus sizes of the SoCs that implement 5G, AI-assisted developers' tools might need to become the norm, not an outlier.

So: in all of this, where is Cadence?

Cadence is focusing its efforts on two areas, dubbed “machine learning inside” and “machine learning outside.” ML inside in the digital design flow refers to improving PPA, faster engines, and better testing and diagnostics. None of this physically affects how you use a tool, but it makes using that tool a much better experience. ML outside talks about the design flow in general, working toward an automated design flow, as well as productivity improvements across the flow. These things do change how you use a tool, but don’t worry, it’s all for the better.

Additionally, Cadence is working to improve design enablement; that is, hardware and software co-design. Smart Genus and Innovus solutions make designing your SoC easier than ever—using the full flow can result in up to a 21% PPA gain.

If you’re looking specifically for IP to enable AI on your SoC, the Tensilica DNA 100 processor has you covered, too. It’s great for companies designing edge or AI chips, offers great compression rates and efficient power usage, and has 4.7X the performance of other AI SoC IP on similar array sizes.

Cadence has you covered no matter where you’re going in this new world of AI systems—with our AI-enabled tools, IP,  and our strong partner ecosystem, you can be at ease knowing you’ll be supported no matter how complex your needs are.

Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019.

What people refer to as “the cloud” is commonly divided into three categories: Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and software as a Service (SaaS). With IaaS, you bring your own software—i.e. loading your owned or appropriately licensed tools onto cloud hardware that you rent by the minute. This service is available from providers like Google Cloud Platform, Amazon Web Service, and Microsoft Azure. In PaaS (also available from the major cloud providers), you create your own offering using capabilities and a software design environment provided by the cloud vendor that makes subsequent scaling and distribution really easy because the service was “born in the cloud”.  Lastly, there’s SaaS, where the cloud is used to access and manage functionality and data without requiring users to set up or manage any of the underlying infrastructure used to provide it.  SaaS companies like Workday and Salesforce deliver their value in this manner.  The Cadence Cloud portfolio makes use of both IaaS and SaaS, depending on the customers’ interest.  Cadence doesn’t have PaaS offerings because our customers don’t create their own EDA software from building blocks that Cadence provides.

All of these designations are great, but you’re a semiconductor designer. Presumably you use Workday or some similar software, or have in the past when you were an intern, but what about all of your tools? Those aren’t on the cloud.

Wait—actually, they are.

Using EDA tools in the cloud allows you to address complexity and data explosion issues you would have to simply struggle through before. Since you don’t have to worry about having the compute-power on-site, you can use way more power than you could before. You may be wary about this new generation of cloud-based tools, but don’t worry: the old rules of cloud computing no longer apply. Cloud capacity is far larger than it used to be, and it’s more secure. Updates to scheduling software means that resource competition isn’t as big of a deal anymore. Clouds today have nearly unlimited capacity—they’re so large that you don’t ever need to worry about running out of space.

The vast increase in raw compute available to designers through the cloud makes something like automotive functional safety verification, previously an extremely long verification task, doable in a reasonable time frame. With the cloud, it’s easy to scale the amount of compute you’re using to fit your task—whether it’s an automotive functional safety-related design or a small one.

Nowadays, the Cadence Cloud Portfolio brings you the best and brightest in cloud technology. No matter what your use case is, the Cadence Cloud Portfolio has a solution that works for you. You can even access the Palladium Cloud, allowing you to try out the benefits of an accelerator without having to buy one.

Cloud computing is the future of EDA. See the future here.

Emulators are great. They vastly speed up verification to the point where it’s hard to imagine life without them; as designs grow in complexity, simple simulation can’t keep up for the biggest designs. The extra oomph from emulation is almost a necessity for the top percentages of design sizes. However, many users of Palladium aren’t efficiently using their unit’s processing power, and as a result they’re missing out on the full speed-up potential that Palladium can provide.

Altair’s HERO is here for you. With its help, your Palladium unit can be even more amazing for your productivity than before.

HERO (that’s Hardware Emulator Resource Optimizer) adds emulator support to Altair’s Accelerator. You already know and love Altair’s scheduling tools; so why not make them do more for you, so you can be one of those people who are making the most out of their Palladium system?

Emulators are kind of like big computers, but it’s a lot harder to manage leftover resources on an emulator than it is on, say, a CPU. A scheduler like HERO neatly sidesteps this problem by more intelligently using the resources available to ensure that there’s a minimal patchwork of leftover resources to begin with.

HERO supports past generations of Palladium as well, so if you’re still using an older version, you can still take advantage of the upgrades HERO provides. There’s a wide variety of features HERO has that make your emulator easier to use. HERO separates a job into a “select” section and a “run” section: the “select” part makes a last-minute decision on which domains or boards to use, while the “run” part is the actual job. This makes it easier to ensure that your Palladium emulator is being used as efficiently as possible. Jobs are placed using “shapes”, which are a set of job types; these can be selected from a list of pre-defined ones by the user. Shapes can have special constraints if those are needed.

A new reservation system also helps HERO organize Palladium’s processing power better. HERO offers both “hard” reservations and “soft” reservations. A hard reservation locks other users out of reserving any part of the emulator at all, while a soft reservation allows a user to reserve a part of the emulator for a later use. Think of it like this: a soft reservation is like grabbing a ticket from the deli counter, while a hard reservation stops you from ever entering the market.

When using HERO, you can manage your entire verification workload. You’ll find that your utilization of your emulator vastly increases—it’s been reported that some users using only 30% of the capabilities of their Palladium unit(s) saw a massive increase to over 90% once they made the switch to HERO.

If you’re ready to take your Palladium productivity to the next level, Altair has a HERO for you.

To see the full presentation given by Andrea Casotto in the Cadence Theater at DAC 2019, check here.

If you weren't able to attend the 2013 DVCon, you missed out on a great IEEE 1801/UPF tutorial delivered by members of the IEEE committee. Accellera had the event recorded and that recording is now posted on the Accellera.org website. Regardless of your work so far with low power design and verification, you need to watch this video.

Power management is becoming ubiquitous in our world. The popular aspect is that reduced power is good for the evironment and that is true. But for those teams that have been building chips around the 40nm node and below, there is another truth. Power management is required simply to get working silicon in many cases. As the industry expands the number of designs with power management and forges deeper into advanced nodes, we steadily identify improvements to the power format descriptions. The most recent set of imporvements to the IEEE 1801 standard are now available in the 2013 version of that standard.

To help bring the standard to life, five representatives from the IEEE joined to deliver a tutorial at DVCon in 2013. Qi Wang (Cadence), Erich Marschner (Mentor), Jeffrey Lee (Synopsys), John Biggs (ARM), and Sushma Honnavarra-Prasad (Broadcom) each contributed to the tutorial. It started with a review of the UPF basics that led to the IEEE 1801 standard delivered by the EDA companies. The IEEE 1801 users then presented tutorial content on how to apply the standard. The session then concluded with a look forward to the IEEE 1801-2013 (UPF 2.1) standard. The standard was released two months after the DVCon tutorial and is available through the Accellera Get program.

So after the bowl games are over and you'vre returned through the woods and back over the river from Grandma's, grab a cup of hot cocoa and learn more about the power standards you may well be using in 2014.

Regards,

Adam "The Jouler" Sherer

Hello , i am trying to extract netlist from a circuit  in assembler

I have found the manual shown bellow , however there is no such option in tools in assembler.

how do i view the NETLIST of this circuit?

Thanks.

ASSEMBLER VIEW menu

Hi,

i am designing a broadband (100 MHz -6 GHz BW) receiver chain for  radar/rcs measurement tester. i will put Low noise amplifier after antenna input followed by mixed(10 MHz IF BW and digitizer.

I am facing problem regarding LAN. bandwidth of LAN is  approx 6 GHz(100 MHz-6GHz), gain 25-35 dB, with NF less than 2. I am uncertain about noise floor at the output of LNA.  I dont know exact SNR at the input of LNA but it shall be good.System operation will be on stepped CW waveform so receiver input signal will sweep over the BW and some step size.

so LNA output r noise floor will be? i assume, we can neglect thr role of input noise because it will be lesser than internal noise of LNA.

will it be LNA internal noise (Thermal noise due to BW) only ?

will it be LNA internal noise (Thermal noise due to BW)  + LAN Gain ? -78+25 =-53 dB? internal noise shall be lesser because NF is less than 3 . 

i have practically observed that that output noise floor is much lesser then even thermal noise( over LNA BW). i have gone through some tutorial where  formula says( internal noise+input noise)+gain. in  my case input noise shall be much less than theoretical internal noise. 

Thanks

Hello, i am a student who is studying Allegro tool with SKILL.

I have a question about SKILL axlSegDelayAndZ0. The reference says this function "returns the delay and impedance of a cline segment."

I want to know how many components does this tool consider when calculating timing delay from the length. 

How steep is input signal's rise transition? Is rise transition shape isosceles trapezoid or differential increasing shape?

Also, if it is a multi fan-out, the rise transition time will be different net by net. How can this tool can calculate in this case?

I want to hear answers about these questions.

Thank you for reading this long boring questions, and i will be waiting for answers.

Hi, I'm trying to create a circle from a pin with 10 mil air gap and at 45 degree rotation. The problem that im facing is that, I'm unable to get the bBox upper left coordinates. Because I want my circle to be placed from that coordinate with a 10 mil air gap. And the pins are "regular" and are placed on "Etch/Top" Layer. Kindly help me in solving this issue.

This is the 18th installment of The Rationalist, my column for the Times of India.

The man who gave us our national anthem, Rabindranath Tagore, once wrote that nationalism was “a great menace.” He went on to say, “It is the particular thing which for years has been at the bottom of India’s troubles.”

Not just India’s, but the world’s: In his book The Open Society and its Enemies, published in 1945 as Adolf Hitler was defeated, Karl Popper ripped into nationalism, with all its “appeals to our tribal instincts, to passion and to prejudice, and to our nostalgic desire to be relieved from the strain of individual responsibility which it attempts to replace by a collective or group responsibility.”

Nationalism is resurgent today, stomping across the globe hand-in-hand with populism. In India, too, it is tearing us apart. But must nationalism always be a bad thing? A provocative new book by the Israeli thinker Yael Tamir argues otherwise.

In her book Why Nationalism, Tamir makes the following arguments. One, nation-states are here to stay. Two, the state needs the nation to be viable. Three, people need nationalism for the sense of community and belonging it gives them. Four, therefore, we need to build a better nationalism, which brings people together instead of driving them apart.

The first point needs no elaboration. We are a globalised world, but we are also trapped by geography and circumstance. “Only 3.3 percent of the world’s population,” Tamir points out, “lives outside their country of birth.” Nutopia, the borderless state dreamed up by John Lennon and Yoko Ono, is not happening anytime soon.

If the only thing that citizens of a state have in common is geographical circumstance, it is not enough. If the state is a necessary construct, a nation is its necessary justification. “Political institutions crave to form long-term political bonding,” writes Tamir, “and for that matter they must create a community that is neither momentary nor meaningless.” Nationalism, she says, “endows the state with intimate feelings linking the past, the present, and the future.”

More pertinently, Tamir argues, people need nationalism. I am a humanist with a belief in individual rights, but Tamir says that this is not enough. “The term ‘human’ is a far too thin mode of delineation,” she writes. “Individuals need to rely on ‘thick identities’ to make their lives meaningful.” This involves a shared past, a common culture and distinctive values.

Tamir also points out that there is a “strong correlation between social class and political preferences.” The privileged elites can afford to be globalists, but those less well off are inevitably drawn to other narratives that enrich their lives. “Rather than seeing nationalism as the last refuge of the scoundrel,” writes Tamir, “we should start thinking of nationalism as the last hope of the needy.”

Tamir’s book bases its arguments on the West, but the argument holds in India as well. In a country with so much poverty, is it any wonder that nationalism is on the rise? The cosmopolitan, globe-trotting elites don’t have daily realities to escape, but how are those less fortunate to find meaning in their lives?

I have one question, though. Why is our nationalism so exclusionary when our nation is so inclusive?

In the nationalism that our ruling party promotes, there are some communities who belong here, and others who don’t. (And even among those who ‘belong’, they exploit divisions.) In their us-vs-them vision of the world, some religions are foreign, some values are foreign, even some culinary traditions are foreign – and therefore frowned upon. But the India I know and love is just the opposite of that.

We embrace influences from all over. Our language, our food, our clothes, our music, our cinema have absorbed so many diverse influences that to pretend they come from a single legit source is absurd. (Even the elegant churidar-kurtas our prime minister wears have an Islamic origin.) As an example, take the recent film Gully Boy: its style of music, the clothes its protagonists wear, even the attitudes in the film would have seemed alien to us a few decades ago. And yet, could there be a truer portrait of young India?

This inclusiveness, this joyous khichdi that we are, is what makes our nation a model for the rest of the world. No nation embraces all other nations as ours does. My India celebrates differences, and I do as well. I wear my kurta with jeans, I listen to ghazals, I eat dhansak and kababs, and I dream in the Indian language called English. This is my nationalism.

Those who try to divide us, therefore, are the true anti-nationals. We must reclaim nationalism from them.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 19th installment of The Rationalist, my column for the Times of India.

A friend of mine was very impressed by the interview Narendra Modi granted last week to Akshay Kumar. ‘Such a charming man, such great work ethic,’ he gushed. ‘He is the kind of uncle I would want my kids to have.’ And then, in the same breath, he asked, ‘How can such a good man be such a bad prime minister?”

I don’t want to be uncharitable and suggest that Modi’s image is entirely manufactured, so let’s take the interview at face value. Let’s also grant Modi his claims about the purity of his neeyat (intentions), and reframe the question this way: when it comes to public policy, why do good intentions often lead to bad outcomes? To attempt an answer, I’ll refer to a story a friend of mine, who knows Modi well, once told me about him. 

Modi was chilling with his friends at home more than a decade ago, and told them an incident from his childhood. His mother was ill once, and the young Narendra was tending to her. The heat was enervating, so the boy went to the switchboard to switch on the fan. But there was no electricity. My friend said that as he told this story, Modi’s eyes filled with tears. Even after all these years, he was moved by the memory.

My friend used this story to make the point that Modi’s vision of the world is experiential. If he experiences something, he understands it. When he became chief minister of Gujarat, he made it his stated mission to get reliable electricity to every part of Gujarat. No doubt this was shaped by the time he flicked a switch as a young boy and the fan did not budge. Similarly, he has given importance to things like roads and cleanliness, since he would have experienced the impact of those as a young man.

My term for him, inspired by Rajat Kapoor’s 2014 film, is ‘the ankhon dekhi prime minister’. At one level, this is a good thing. He sees a problem and works for the rest of his life to solve it. But what of things he cannot experience?

The economy is a complex beast, as is society itself, and beyond a certain level, you need to grasp abstract concepts to understand how the world works. You cannot experience them. For example, spontaneous order, or the idea that society and markets, like language, cannot be centrally directed or planned. Or the positive-sum nature of things, which is the engine of our prosperity: the idea that every transaction is a win-win game, and that for one person to win, another does not have to lose. Or, indeed, respect for individual rights and free speech.

One understands abstract concepts by reading about them, understanding them, applying them to the real world. Modi is not known to be a reader, and this is not his fault. Given his background, it is a near-miracle that he has made it this far. He wasn’t born into a home with a reading culture, and did not have either the resources or the time when he was young to devote to reading. The only way he could learn about the world, thus, was by experiencing it.

There are two lessons here, one for Modi himself and others in his position, and another for everyone.

The lesson in this for Modi is a lesson for anyone who rises to such an important position, even if he is the smartest person in the world. That lesson is to have humility about the bounds of your knowledge, and to surround yourself with experts who can advise you well. Be driven by values and not confidence in your own knowledge. Gather intellectual giants around you, and stand on their shoulders.

Modi did not do this in the case of demonetisation, which he carried out against the advice of every expert he consulted. We all know the damage it caused to the economy.

The other learning from this is for all of us. How do we make sense of the world? By connecting dots. An ankhon-dekhi approach will get us very few dots, and our view of the world will be blurred and incomplete. The best way to gather more dots is reading. The more we read, the better we understand the world, and the better the decisions we take. When we can experience a thousand lives through books, why restrict ourselves to one?

A good man with noble intentions can make bad decisions with horrible consequences. The only way to hedge against this is by staying humble and reading more. So when you finish reading this piece, think of an unread book that you’d like to read today – and read it!

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

I am importing sessions which are run by other people to analyse and I would like to remove them from my vManager Regressions tab as they become obsolete. As I am not the original person who run the sims, I cannot "delete" sessions. What are my options? Thanks.

Is there a setting for automatically naming nets from port names in a hierarchical design? That is, when creating a netlist for Allegro in Capture.

Is it possible to change trace ends from round to square? Allegro PCB Designer 17.2 (basic)

Thanks

Hi all,

I am using ADE assembler.

I ran transient simulation and swept the input frequency (Fin) of the circuit. And I use Spectrum Measurement to return a value of the fundamental tone magnitude (Sig_fund) for each sweep point. 

Previously, I use "plot across design points" to plot both "Fin" and "Sig_fund", and then use "Y vs Y" to get a waveform of Sig_fund vs Fin. Measure the 1dB Bandwidth with markers. 

Can I realized above measurement with an expression in "output setup" ? And how?

I know to set the "Eval type" to "sweep" to process the data across sweep points. But here, it has to return an interpolated value from "Fin" with a criteria "(value(calcVal("Sig_fund"  0) - 1)". I am not sure whether it can be done in ADE assembler.

Thanks and regards,

Yutao

Hello,

I find a strange issue when using design variable -> right-click -> copy from cellview in assembler. Cadence version is IC618-64b. 500.9

In fact, I set the value of variable (e.g., AAA = 100), then after I right-click -> copy from cellview, AAA's is updated to other value. In my opinion "copy from cellview" should only update the missing variable to the list, but not change any variable value. 

Is there any mechanism could change variable value when using "copy from cellview"?

Thanks

Hello,

I am trying to import (in spectre) an spice model of a ceramic capacitor manufactured by Samsung EM. The link that includes the model is here :-

http://weblib.samsungsem.com/mlcc/mlcc-ec.do?partNumber=CL05A156MR6NWR

They proved static spice model and interactive spice model.

I had no problem while including the static model.

However, the interactive model which models voltage and temperature coefficients seems to not be an ordinary spice model. They provide HSPICE, LTSPICE, and PSPICE model files and I failed to include any of them.

Any suggestions ?

Hello,

I am using Virtuoso 6.1.7.

I am performing the parasitic extraction of a MOM cap array of 32 caps. I use Quantus QRC and I enable field solver. I select “QRCFS” for field solver type and “High” for field solver accuracy. The unit MOM cap is horizontally and vertically symmetric. The array looks like the sketch below and there are no other structures except the unit caps:

Rationally speaking, the capacitance values of the unit caps should be symmetric with respect to a vertical symmetry axis that is between cap16 and cap17 (shown with dashed red line). For example,

the capacitance of cap1 should be equal to the capacitance of cap32

the capacitance of cap2 should be equal to the capacitance of cap31

etc. as there are no other structures around the caps that might create some asymmetry.

Nevertheless, what I observe is the following after the parasitic extraction:

As it can be seen, the result is not symmetric contrary to what is expected. I should also add that I do not observe this when I perform parasitic extraction with no filed solver.

Why do I get this result? Is it an artifact resulting from the field solver tool (my conclusion was yes but still it must be verified)? If not, how can something like this happen?

Many thanks in advance.

Best regards,

Can

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