The technology of the present application provides a networked computer system with at least one workstation and at least one shared resource such as a database. Access to the database by the workstation is managed by a database management system. An access engine reviews job requests for access to the database and allows job requests access to the resource based protocols stored by the system.

Disclosed are a reconfigurable processor and processing method, a reconfiguration control apparatus and method, and a thread modeler and modeling method. A memory area of a reconfigurable processor may be divided into a plurality of areas, and a context enabling a thread process may be stored in respective divided areas, in advance. Accordingly, when a context switching is performed from one thread to another thread, the other thread may be executed by using information stored in an area corresponding to the other thread.

Disclosed is an information processing device and a task switching method that can reduce the time required for switching of tasks in a plurality of coprocessors. The information processing device (30) includes a processor core (301); coprocessors (311 to 31n) including operation units (321 to 32n) that perform operation in response to a request from the processor core (301) and operation storage units (331 to 22n) that store the contents of operation of the operation units (321 to 32n), save storage units (351 to 35n) that store the saved contents of operation, a task switching control unit (302) that outputs a save/restore request signal when switching a task on which operation is performed by the coprocessors (311 to 31n), and save/restore units (341 to 34n) that perform at least one of saving of the contents of operation in the operation storage units (331 to 33n) to the save storage units (351 to 35n) and restoration of the contents of operation in the save storage units (351 to 35 n) to the operation storage units (331 to 33n) in response to the save/restore request signal.

A process for producing a fluoroalkyl iodide as a telomer Rf(CF2CF2)nI (wherein Rf is a C1-10 fluoroalkyl group, and n is an integer of from 1 to 6) by telomerization from a fluoroalkyl iodide represented by the formula RfI (wherein Rf is as defined above) as a telogen and tetrafluoroethylene (CF2CF2) as a taxogen, which comprises a liquid phase telomerization step of supplying a homogeneous liquid mixture of the telogen and the taxogen from the lower portion of a tubular reactor, moving the mixture from the lower portion towards the upper portion of the reactor in the presence of a radical initiator over a retention time of at least 5 minutes while the reaction system is kept in a liquid phase state under conditions where no gas-liquid separation will take place, so that the taxogen supplied to the reactor is substantially consumed by the reaction in the reactor, and drawing the reaction product from the upper portion of the reactor.

Disclosed are: a diaryliodonium salt mixture which is a precursor of a BF4 salt or the like of a diaryliodonium compound, can be produced in the form of crystals at ambient temperature, can be purified in a simple manner, can be produced with high efficiency, and can be induced into a BF4 salt or the like salt that has excellent solubility in a monomer or the like; and a process for producing the diaryliodonium salt mixture. Also disclosed is a production process which can achieve good yield and can produce reduced amounts of byproducts, and is therefore applicable to the industrial mass production of a diaryliodonium compound. The diaryliodonium salt mixture is characterized by containing at least two specific diaryliodonium salts.

The instant invention relates to a process and method for manufacturing 2,3,3,3-tetrafluoropropene by dehydrohalogenating a reactant stream of 2-chloro-1,1,1,2-tetrafluoropropane that is substantially free from impurities, particularly halogenated propanes, propenes, and propynes.

Disclosed is a process for producing 1,2-dichloro-3,3,3-trifluoropropene, which is characterized by that 1-halogeno-3,3,3-trifluoropropene represented by the general formula [1]: (In the formula, X represents a fluorine atom, chlorine atom or bromine atom.) is reacted with chlorine in a gas phase in the presence of a catalyst. It is possible by this process to produce 1,2-dichloro-3,3,3-trifluoropropene in an industrial scale with good yield by using 1-halogeno-3,3,3-trifluoropropene, which is available with a low price, as the raw material.

The invention also relates a process for the manufacture of trans 1-chloro3,3,3-trifluoropropene. The process comprises an isomerization step from cis 1233zd to trans 1233zd.

The invention also relates a process for the manufacture of trans 1-chloro3,3,3-trifluoropropene. The process comprises an isomerization step from cis 1233zd to trans 1233zd.

The present disclosure relates to processes for reducing the concentration of RfC≡CX impurities in fluoroolefins. The process involves: contacting a mixture comprising at least one fluoroolefin and at least one RfC≡CX impurity with at least one amine to reduce the concentration of the at least one RfC≡CX impurity in the mixture; wherein Rf is a perfluorinated alkyl group, and X is H, F, Cl, Br or I. The present disclosure also relates to processes for making at least one hydrotetrafluoropropene product selected from the group consisting of CF3CF═CH2, CF3CH═CHF, and mixtures thereof and reducing the concentration of CF3C═CH impurity generated during the process. The present disclosure also relates to processes for making at least one hydrochlorotrifluoropropene product selected from the group consisting of CF3CCl═CH2, CF3CH═CHCl, and mixtures thereof and reducing the concentration of CF3C≡CH impurity generated during the process.

Disclosed is a process for the synthesis of 1,1,2,3-tetrachloropropene (HCC-1230xa) using 1,1,3-trichloropropene (HCC-1240za) and/or 3,3,3-trichloropropene (HCC-1240zf) and Cl2 gas as the reactants, wherein the process takes place in a single reactor system. Before this invention, HCC-1230xa was made in a two-step process using HCC-1240za/HCC-1240zf and Cl2 gas, and the processing was conducted using two separate reactors.

The present disclosure relates to a process for separating a fluoroolefin from a mixture comprising hydrogen fluoride and fluoroolefin, comprising azeotropic distillation both with and without an entrainer. In particular are disclosed processes for separating any of HFC-1225ye, HFC-1234ze, HFC-1234yf or HFC-1243zf from HF.

The present invention is directed to processes for the production of 1233zd from 240fa and HF, with or without a catalyst, at a commercial scale. The 240fa and HF are fed to a reactor operating at high pressure. The resulting product stream comprising 1233zd, HCl, HF, and other byproducts is treated to one or more purification techniques including phase separation and one or more distillations to provide purified 1233zd, which meets commercial product specifications, i.e., having a GC purity of 99.5% or greater.

The present invention relates to a process for separating chlorinated methanes utilizing a dividing wall column. Processes and manufacturing assemblies for generating chlorinated methanes are also provided, as are processes for producing products utilizing the chlorinated methanes produced and/or separated utilizing the present process(es) and/or assemblies.

The invention relates to a process for removing one or more undesired (hydro)halocarbon compounds from a (hydro)fluoroalkene, the process comprising contacting a composition comprising the (hydro)fluoroalkene and one or more undesired (hydro)halocarbon compounds with an aluminum-containing absorbent, activated carbon, or a mixture thereof.

The invention relates to a process for the preparation of formula (I) which process comprises pyrolyzing a compound of formula (II) wherein X is chloro or bromo, and to compounds which may be used as intermediates for the manufacture of the compound of formula I and to the preparation of said intermediates.

Disclosed is a reactor and agitator useful in a high pressure process for making 1-chloro-3,3,3-trifluoropropene (1233zd) from the reaction of 1,1,1,3,3-pentachloropropane (240fa) and HF, wherein the agitator includes one or more of the following design improvements: (a) double mechanical seals with an inert barrier fluid or a single seal;(b) ceramics on the rotating faces of the seal;(c) ceramics on the static faces of seal;(d) wetted o-rings constructed of spring-energized Teflon and PTFE wedge or dynamic o-ring designs; and(e) wetted metal surfaces of the agitator constructed of a corrosion resistant alloy.

The subject of the invention is a process for the preparation of fluoroolefin compounds. It relates more particularly to a process for manufacturing a (hydro)fluoroolefin compound comprising (i) bringing at least one compound comprising from three to six carbon atoms, at least two fluorine atoms and at least one hydrogen atom, provided that at least one hydrogen atom and one fluorine atom are located on adjacent carbon atoms, into contact with potassium hydroxide in a stirred reactor, containing an aqueous reaction medium, equipped with at least one inlet for the reactants and with at least one outlet, in order to give the (hydro)fluoroolefin compound, which is separated from the reaction medium in gaseous form, and potassium fluoride, (ii) bringing the potassium fluoride formed in (i) into contact, in an aqueous medium, with calcium hydroxide in order to give potassium hydroxide and to precipitate calcium fluoride, (iii) separation of the calcium fluoride precipitated in step (ii) from the reaction medium and (iv) optionally, the reaction medium is recycled after optional adjustment of the potassium hydroxide concentration to step (i).

The present invention provides routes for making 1-chloro-3,3,3-trifluoropropene (HCFO-1233zd) from commercially available raw materials. More specifically, this invention provides routes for HCFO-1233zd from inexpensive and commercially available trifluoromethane (HFC-23).

The present invention provides routes for making 1-chloro-3,3,3-trifluoropropene (HCFO-1233zd) from commercially available raw materials. More specifically, this invention provides several routes for forming HCFO-1233zd from 3,3,3-trifluoropropene (FC-1234zf).

Disclosed is a process for producing 2-chloro-1,3,3,3-tetrafluoropropene (1224), including a first step of separating 2,3-dichloro-1,1,1,3-tetrafluoropropane (234da) into erythro form and threo form, and a second step of bringing the separated erythro form or threo form in contact with a base to obtain 2-chloro-1,3,3,3-tetrafluoropropene (1224). The first step is a step of separating 234da by distillation to achieve a separation into a fraction containing mainly erythro form and a fraction containing mainly threo form. In the second step, 1224 cis form is obtained from the erythro form, and 1224 trans form is obtained from the threo form. By this process, it is possible to selectively and efficiently produce cis form or trans form of 2-chloro-1,3,3,3-tetrafluoropropene (1224).

This invention provides a process for producing 2,3,3,3-tetrafluoropropene, the process comprising: (1) a first reaction step of reacting hydrogen fluoride with at least one chlorine-containing compound selected from the group consisting of a chloropropane represented by Formula (1): CClX2CHClCH2Cl, wherein each X is the same or different and is CI or F, a chloropropene represented by Formula (2): CClY2CCl═CH2, wherein each Y is the same or different and is CI or F, and a chloropropene represented by Formula (3): CZ2═CClCH2Cl, wherein each Z is the same or different and is CI or F in a gas phase in the absence of a catalyst while heating; and (2) a second reaction step of reacting hydrogen fluoride with a reaction product obtained in the first reaction step in a gas phase in the presence of a fluorination catalyst while heating. According to the process of this invention, 2,3,3,3-tetrafluoropropene (HFO-1234yf) can be obtained with high selectivity, and catalyst deterioration can be suppressed.

Process for producing silica-comprising dispersions comprising a polyetherol or a polyether amine, which comprises the steps of (i) admixing an aqueous silica sol (K) having an average particle diameter of from 1 to 150 nm and a silica content, calculated as SiO2, of from 1 to 60% by weight and a pH of from 1 to 6 with at least one polyetherol (b1) and/or polyether amine (b2) based on ethylene oxide and/or propylene oxide and having an average OH or amine functionality of from 2 to 6 and a number average molecular weight of from 62 to 6000 g/mol,(ii) distilling off at least part of the water,(iii) admixing the dispersion with at least one compound (S) having at least one at least monoalkoxylated silyl group and at least one alkyl, cycloalkyl or aryl substituent, where this substituent may have groups which are reactive toward an alcohol, an amine or an isocyanate in an amount of from 0.1 to 20 μmol of (S) per m2 of surface area of (K), where steps (i) and (iii) can be carried out simultaneously or in succession in any order, (iv) optionally adjusting the pH of the silica-comprising dispersions obtained to a value of from 7 to 12 by adding a basic compound, where step (iv) can also be carried out between steps (ii) and (iii).

The invention relates to process for the treatment of a hydrophobic surface by a liquid film comprising an aqueous phase comprising the coating of said surface by the liquid whose aqueous phase comprises an effective amount of an agent of modification of the properties of surface and an active agent.

A data processing apparatus includes multiple processing means that are connected in a ring shape via corresponding communication means respectively. Each communication means includes a reception means for receiving data from a previous communication means, and a transmission means for transmitting data to a next communication means. Connection information is assigned to each of the reception means and the transmission means. The communication means, when receiving a packet that has same connection information as one assigned to its reception means, causes the corresponding processing means to perform data processing on the packet, sets the connection information assigned to its transmission means to the packet, and transmits the packet to the next communication means, and when receiving a packet that has connection information that is not same as one assigned to its reception means, transmits the packet to the next communication means without changing the connection information of the packet.

A vector data access unit includes data access ordering circuitry, for issuing data access requests indicated by elements of earlier and a later vector instructions, one being a write instruction. An element indicating the next data access for each of the instructions is determined. The next data accesses for the earlier and the later instructions may be reordered. The next data access of the earlier instruction is selected if the position of the earlier instruction's next data element is less than or equal to the position of the later instruction's next data element minus a predetermined value. The next data access of the later instruction may be selected if the position of the earlier instruction's next data element is higher than the position of the later instruction's next data element minus a predetermined value. Thus data accesses from earlier and later instructions are partially interleaved.

A statue management section of a control section is provided with a corresponding real number storage section that stores a real number converted from a logical number by a configuration number converting section. When the corresponding real number storage section has stored configuration information with a real number of the next transition state, the state management section directly supplies the real number to the configuration information storage section in the next or later processing cycle.

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index, and then, the register file pointed to by said index is accessed based on said index; an execution stage where an access result of said decode stage is received, and computations are implemented according to the access result of the decode stage.

The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.

A technique for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced. The disclosure reduces the cycle delay of the slave processor in accessing the dual-port RAM and the register, thereby effectively reducing the dynamic power consumption of the chip, improving the processing capability of the slave processor and enhancing the effective performance of the slave processor.

A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.

Augmented processor hardware contains a microcode interpreter. When encrypted microcode is included in a message from a service, the microcode may be passed to the microcode interpreter. Based on decryption and execution of the microcode taking place at the processor hardware, extended functionality may be realized.

A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.

A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.

In a multiprocessor system, in general, a processor assigned with a larger amount of tasks is apt to perform a larger amount of communication with other processors assigned with tasks, than a processor assigned with a smaller amount of tasks. Thus in order for each processor to be able to perform the routing process efficiently, tasks are assigned such that, when there are a first processor and a second processor, the number of processors each assigned with one or more tasks and directly connected with the second processor being smaller than the number of processors each assigned with one or more tasks and directly connected with the first processor, the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor.

A method for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.

A multiprocessor system includes a first microprocessor and a second microprocessor. A first signaling pathway is configured to send message transmission coordination signals from the first microprocessor to the second microprocessor. The first signaling pathway may be coupled to at least two flag registers associated with the second microprocessor. A second signaling pathway is configured to send message transmission coordination signals from the second microprocessor to the first microprocessor. The second signaling pathway may be coupled to at least two flag registers associated with the first microprocessor. The first signaling pathway is independent of the second signaling pathway.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

In accordance with embodiments, there are provided mechanisms and methods for controlling a process using a process map. These mechanisms and methods for controlling a process using a process map can enable process operations to execute in order without necessarily having knowledge of one another. The ability to provide the process map can avoid a requirement that the operations themselves be programmed to follow a particular sequence, as can further improve the ease by which the sequence of operations may be changed.

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.

A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.

A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction that corresponds to the instruction bits. In turn, the processor executes the forced event.

In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state.

A method of applying formal verification methodologies to event processing applications is provided herein. The method includes the following stages: representing an event processing application as an event processing network, being a graph with event processing agents as nodes; generating a finite state machine based on the event processing network, wherein the finite state machine is an over-approximation of the event processing application; expressing stateful rules and policies that are associated with the event processing application using temporal logic, to yield a temporal representation of the event processing application; combining the temporal representation and the finite state machine into a model; generating a statement associated with a user-selected verification-related property of the event processing application, wherein the statement is generated using the temporal representation; and applying the statement to the model, to yield an indication for: (i) a correctness of the statement or (ii) a counter example, respectively.