Disclosed is a heat exchanger including: a heat exchanger body; a gas inlet for introducing exhaust gas into the heat exchanger body; a coolant inlet for introducing a coolant into the heat exchanger body; a gas outlet for discharging the exhaust gas that is cooled by heat exchange with the coolant; and a coolant outlet for discharging the coolant that completes heat exchange with the exhaust gas. In this case, the heat exchanger body includes: a laminated tube core formed by laminating a plurality of gas channels side by side; a housing formed so as to enclose the laminated tube core except for opposite ends thereof; and a wave fin plate integrally provided with a plurality of wave fins and arranged within each of the gas channels, wherein each of the wave fins includes a fixed pitch section, and a variable pitch section.

An integratable movement device for ventilating equipment includes an electric machine such as a motor and a fan wheel connected with the electric machine. The movement device further includes a housing, wherein the electric machine and the fan wheel are installed in an inner lower portion of the housing. An upper portion of the housing integrally forms one or more venting outlets. A plurality of venting outlet units is provided at the venting outlets respectively. A chamber provided between the venting outlets and the fan wheel in the housing defines a venting channel. The housing having the venting outlets and the venting channel, along with the venting outlet units, the electric machine and the fan wheel configure the integratable movement device that is able to be directly assembled into the ventilating equipment.

A heat exchange device includes a housing, a heat exchange module, and a piezoelectric module. Isolated inner and outer circulation chambers are formed in the housing. The heat exchange module in the housing includes a stack of separated plates parallel to each other. An inner channel communicated with the inner circulation chamber and an outer channel communicated with the outer circulation chamber are defined respectively by both sides of one of the plates and the other adjacent plates. The piezoelectric module in the housing includes a piezoelectric chip, and first and second heat exchange sides thermally coupled to the piezoelectric chip. The first heat exchange side is located in the inner circulation chamber and the second heat exchange side is located in the outer circulation chamber, so that heat can be transferred between the inner and outer circulation chambers via the piezoelectric chip.

An adjustable refrigerant distribution device and a heat exchanger having same. The heat exchanger comprises: first and second collecting pipes; a heat exchanger core body; and a refrigerant distribution device, the refrigerant distribution device comprises a first distribution pipe, a first inlet pipe and a first drive assembly. The pipe wall of the first distribution pipe is provided with a first distribution hole. The first distribution pipe is inserted into at least one of the first and the second collecting pipes. The first inlet pipe is located outside at least one collecting pipe and is in communication with the first distribution pipe, and the first drive assembly drives the first distribution pipe to move relative to at least one collecting pipe. The distribution pipe of the refrigerant distribution device and the heat exchanger can translate along the axial direction, thereby adjusting refrigerant distribution so as to satisfy different distribution requirements.

In order to enhance heat reception from a cooling target object by a heat sink to efficiently cool a device, the cooling target object, a cooling device including a heat sink and a fluid path is provided. Further, the heat sink includes a heat receiving face. The fluid path is formed so as to allow a predetermined fluid to pass therethrough. The heat exchange portion includes a first path arranged approximately in parallel to the heat receiving face of the heat sink.

Integrated heat spreaders having electromagnetically-formed features, and semiconductor packages incorporating such integrated heat spreaders, are described. In an example, an integrated heat spreader includes a top plate flattened using an electromagnetic forming process. Methods of manufacturing integrated heat spreaders having electromagnetically-formed features are also described.

A digital down converter with an equalizer translates an ADC output signal to a low frequency spectral region, followed by decimation. All operations of correction of the processed signal are carried out with a reduced sampling rate compared with sampling rates of the prior art. Equalization is performed only in a frequency pass band of the down converter. The achieved reduction of the required computation resources is sufficient to enable the down converter with equalization to operate in a real time mode.

Embodiments of the invention provides a decoder for decoding a signal received through a transmission channel in a communication system, said signal carrying information symbols selected from a given alphabet and being associated with a signal vector, said transmission channel being represented by a channel matrix, wherein said decoder comprises: a sub-block division unit (301) configured to divide the received signal vector into a set of sub-vectors in correspondence with a division of a matrix related to said channel matrix;a candidate set estimation unit (305) for recursively determining candidate estimates of sub-blocks of the transmitted signal corresponding to said sub-vectors, each estimate of a given sub-block being determined from at least one candidate estimate of the previously processed sub-blocks,wherein said candidate set estimation unit is configured to determine a set of candidate estimates for at least one sub-block of the transmitted signal by applying at least one iteration of a decoding algorithm using the estimates determined for the previously processed sub-blocks, the number of candidate estimates determined for said sub-block being strictly inferior to the cardinal of the alphabet and superior or equal to two, the decoder further comprising a signal estimation unit (306) for calculating an estimate of the transmitted signal from said candidate estimates determined for said sub-blocks.

A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.

Input device adhesive techniques are described. A pressure sensitive key includes a sensor substrate having one or more conductors, a spacer layer, and a flexible contact layer. The spacer layer is disposed proximal to the sensor substrate and has at least one opening. The flexible contact layer is spaced apart from the sensor substrate by the spacer layer and configured to flex through the opening in response to an applied pressure to initiate an input. The flexible contact layer is secured to the spacer layer such that at first edge, the flexible contact layer is secured to the spacer layer at an approximate midpoint of the first edge and is not secured to the spacer along another portion of the first edge and at a second edge, the flexible contact layer is not secured to the spacer layer along an approximate midpoint of the second edge.

A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.

A method for adaptively regulating a coding mode and a digital correction circuit thereof are provided. The method is for a successive-approximation-register analog-to-digital converter (SAR ADC). In the method, whether to regulate a binary weight corresponding to each of digital bits is determined according to the number of completed comparison cycles to provide a first coding sequence. The first coding sequence is directly compensated according to uncompleted comparison cycles to provide a correct digital output code.

The invention relates to an encoder and a decoder and methods therein for supporting split gain shape vector encoding and decoding. The method performed by an encoder, where the encoding of each vector segment is subjected to a constraint related to a maximum number of bits, BMAX, allowed for encoding a vector segment. The method comprises, determining an initial number, Np—init, of segments for a target vector x; and further determining an average number of bits per segment, BAVG, based on a vector bit budget and Np—init. The method further comprises determining a final number of segments to be used, for the vector x, in the gain shape vector encoding, based on energies of the Np—init segments and a difference between BMAX and BAVG. The performing of the method enables an efficient allocation of the bits of the bit budget over the target vector.

A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.

An input buffer for an ADC is provided. The input buffer includes a receiving circuit and an impedance circuit. The receiving circuit is coupled between a power supply and a sample-and-hold circuit of the ADC, and receives an analog input signal and generating an analog signal. The impedance circuit is coupled to the receiving circuit, and selectively provides a variable impedance. When the sample-and-hold circuit of the ADC is operated in a first phase, the impedance circuit provides a small impedance, and when the sample-and-hold circuit of the ADC is operated in a second phase, the impedance circuit provides a large impedance.

A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

A digital-to-analog converter (DAC) and a high-voltage tolerance circuit are provided. The DAC includes a high-voltage tolerance circuit. The high-voltage tolerance circuit is configured to generate a reference voltage, and select the reference voltage or a first power-source voltage to control the node voltage of each branch of an operational amplifier circuit of the high-voltage tolerance circuit according the logical signal level of an input signal.

An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

A semiconductor device configured to perform an A/D conversion of a wide range of signals is provided. A semiconductor device includes: an input voltage detection unit configured to detect an analog input voltage; a reference voltage setting unit configured to set a reference voltage based on the detected input voltage; an amplifier configured to amplify a difference between the input voltage and the reference voltage; an ADC configured to perform an A/D conversion of an amplified signal; and an arithmetic processing unit configured to calculate a digital voltage corresponding to the input voltage based on a result of the A/D conversion and the reference voltage.

A hybrid SAR-ADC that uses a combination of voltage-based signal processing and time-based signal processing to convert an analog input signal to a digital output signal is disclosed. In some embodiments, the hybrid SAR-ADC has a voltage-based signal processing element configured to convert an analog input signal to a first digital signal having a plurality of MSBs and to generate a residue voltage from an input voltage and the first digital signal. A voltage-to-time conversion element is configured to convert the residue voltage to a time domain representation. A time-based signal processing element is configured to convert the time domain representation to a second digital signal comprising a plurality of LSBs. By determining the plurality of MSBs using voltage-based signal processing and determining the plurality of LSBs using time-based signal processing, the hybrid SAR-ADC is able to achieve low power and compact area.

A converter includes: a terminal that receives code-modulated power that has been generated with a modulation code; and a circuit that intermittently converts the code-modulated power with a conversion code based on the modulation code. The code-modulated power is alternating-current power.

Methods and apparatus are described. A method, implemented in a decoder, includes receiving two or more signals from an encoder over two or more respective wires. At least one of the two or more signals includes at least one code that was recoded by the encoder. The decoder receives a recoding table. The recoding table provides a mapping indicating the recoding for each code that was recoded by the encoder in the received two or more signals. The decoder decodes the two or more received signals using the received recoding table.

A computer-implemented method, system, and apparatus for storing binary data is disclosed. A processor receives a digital bit stream and transforms the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises a data message encoded by an OCTS-expanded table for storage. The processor stores the encoded digital bit stream on a digital data storage device or system.

Typically, complex systems require a separate and expensive equalizer at the output of an analog-to-digital converter (ADC). Rather than providing a separate equalizer, the effective Signal Transfer Function (STF) of a Multi-stAge noise SHaping (MASH) ADC can be modified by leveraging available digital filtering hardware necessary for quantization noise cancellation. The modification can involves adding calculations in the software previously provided for computing digital quantization noise cancellation filter coefficients, where the calculations are added to take into account equalization as well. As a result, the signal transfer function can be modified to meet ADC or system-level signal-chain specifications without additional equalization hardware. The method is especially attractive for high-speed applications where magnitude and phase responses are more challenging to meet.

Modifying a digital data stream that includes immediately consecutive code words of different length by segmenting, based on a certain block grid, the digital data stream. Each block of the block grid includes a fixed number of bits. It is determined whether all bits of the last block associated with the digital data stream are occupied by data of the digital data stream. If not all bits of the last block are occupied, the unoccupied bits of the last block are padded with bits of an end-of-record (EOR) indicator. If all bits of the last block are occupied, attaching an EOR indicator to the digital data stream is skipped.

For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.

An analog-to-digital converter (ADC) is a device that can include a reference shuffler and a loop filter. An ADC can achieve better performance with incremental adjustment of a pointer of the reference shuffler, changing coefficients of the loop filter, and storing calibration codes of the ADC in a non-volatile memory. By incrementally adjusting a pointer of the reference shuffler, a calibration can be performed more efficiently than with a random adjustment of the pointer. By temporarily changing the loop filter coefficients, a greater amount of activity can be introduced into the loop filter. This activity can allow the calibration to proceed more efficiently. By storing the calibration codes in a non-volatile memory, a search space for calibration codes can be reduced. Thus, a calibration can occur more quickly, and the calibration itself can be improved.

An analog to digital converter includes an error integration circuit configured to receive an input charge from a detector and to integrate a difference between the input charge and one or more feedback charge pulses to create an error voltage. A quantizer is in operable communication with the error integration circuit and is responsive to the created error voltage. An accumulator having a mantissa component and a radix component is in operable communication with the quantizer. A charge feedback device in operable communication with the quantizer and the radix component of the accumulator. The charge feedback device is configured to generate the one or more feedback charge pulses proportional to the radix component of the accumulator and an output of the quantizer. Digital focal plane read out integrated circuits including the analog to digital converter are also disclosed.

The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

A circuit and a method for converting an analog signal to a digital value representation is disclosed. In one aspect, the circuit includes an incremental sigma-delta analog-to-digital converter (ADC). The circuit further includes a first input line for providing a primary analog signal representing a sensor measurement to the incremental sigma-delta ADC. The circuit further includes a second input line for providing a secondary analog signal to the incremental sigma-delta ADC. The incremental sigma-delta ADC receives the primary and secondary analog signals during a first period (TADC1) and a second period (TADC2), respectively. The circuit further includes a filter configured to weight the digital values in a sequence of digital values output by the incremental sigma-delta ADC, and to output a single digital value representing the sensor measurement.

The present disclosure pertains to systems and methods for monitoring a plurality of analog-to-digital converters. In one embodiment, a plurality of input channels may each be in communication with a different phase of a three-phase electric power delivery system. The input channels may be configured to receive analog signals from the different phases. A composite signal subsystem may be configured to generate a composite signal based on the plurality of input channels. An analog-to-digital converter subsystem may be configured to produce a digitized representation of each of the plurality of input channels and a digitized representation of the composite signal. An analog-to-digital converter monitor subsystem may identify an error in the analog-to-digital conversion based on the digitized representation of the composite signal and the digitized representations of the plurality of input channels.

A semiconductor device having an analog/digital conversion circuit converting an analog signal to a digital signal, includes a holding circuit outputting an analog signal having a value according to a value of an analog signal supplied in a first period; and a prediction circuit generating a first digital signal based on bit position information from a prediction table corresponding to the supplied analog signal.

System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

A process is provided for recovering sodium chloride crystals and sodium carbonate decahydrate crystals from a concentrated brine that results from a gas mining operation where gas and produced water is recovered and the produced water constitutes a brine. An initial pre-concentration process is carried out where the brine is concentrated and in the process carbon dioxide is removed from the brine and at least some sodium bicarbonate is converted to sodium carbonate. In one process, the concentrated brine is directed to a sodium chloride crystallizer where the brine is heated and further concentrated to form sodium chloride crystals which are separated from the brine to yield a product and wherein the resulting brine is termed a first mother liquor. The first mother liquor is then directed to a sodium carbonate decahydrate crystallizer where the first mother liquor is cooled and concentrated resulting in the formation of sodium carbonate decahydrate crystals and a second mother liquor. The second mother liquor is split into two streams where one stream is directed back to the sodium chloride crystallizer while the other stream is wasted or further treated.

Method for the production of a coarse-grained ammonium sulphate product by crystallization and installation for carrying out the method from an ammonium sulphate solution in a DTB type crystallizer having an internal suspension circuit and a clarifying zone, from which a clarified partial flow of solution is constantly drawn off into an external circuit, is heated in a heat exchanger to dissolve the solids contained therein and is guided back as a clear solution into the lower region of the crystallizer. A fine crystal suspension flow is drawn off from the clarifying zone as a further partial flow and guided back into the internal circuit of the crystallization stage without any previous dissolution of the solid proportion contained therein.

A method of producing a titanium dioxide pigment is provided. Also provided is a method of improving the processability of titanium dioxide particles without adversely affecting the rheological properties of the titanium dioxide particles.

Method and apparatus for limiting absorption of food products in specific parts of the digestive system is presented. A gastrointestinal implant device is anchored in the pyloric portion of the gastrointestinal system and extends beyond the ligament of Treitz. All food exiting the stomach is funneled through the device. The gastrointestinal device includes an anchor for anchoring the device in the pyloric portion and a flexible sleeve that extents into the duodenum. The anchor is collapsible for endoscopic delivery and removal.

Pelletizing device and method for pelletizing pelletizing materials having a pelletizing disk inclined to the horizontal and provided rotatable wherein the pelletizing disk is driven via a motor device. The pelletizing disk comprises a bottom and a side wall, the effective height of the side wall being variable. The side wall comprises an inner side wall device and an outer side wall device, the inner side wall device being disposed height-adjustable relative to the outer side wall device.

A production saltwater disposal facility comprising a separator configured to receive production saltwater from a pipeline or a vehicle and separate hydrocarbons from the production saltwater, wherein the production saltwater received from the pipeline or vehicle is substantially the same composition as when the production saltwater was located in a subterranean formation, a hydrocarbon storage tank configured to receive hydrocarbons from the separator, a settling pit configured to receive the production saltwater from the separator and separate metals and/or other solids from the saltwater, an evaporator in fluid communication with the settling pit and comprising a nozzle configured to emit a stream of the saltwater along a path in air such that water in the saltwater evaporates, and a collection pit positioned under the path and configured to collect the salt from the saltwater after the water has evaporated.

The present invention provides a kiln for the combustion of agricultural waste. The kiln includes a central cylindrical combustion chamber. The central cylindrical combustion chamber includes a system for the control of combustion air to the combustion chamber. The kiln includes a second concentric cylinder surrounding the central cylindrical combustion chamber. The second concentric cylinder includes a system for the flow of cooling water through the first annulus between the central cylindrical combustion chamber and the second concentric cylinder. The kiln includes a system for the feeding of the agricultural waste into the central combustion chamber. The kiln includes a temperature sensing device to measure and display the temperature within the central combustion chamber during the combustion of the agricultural waste. The kiln includes a system for the recovery of ash from the kiln. In operation, the temperature of combustion is controlled to between 550° C. and 650° C. by a combination of increasing the supply of combustion air when the temperature in the central combustion chamber falls to near 550° C. and the introduction of cooling flowing water when the temperature in the central combustion chamber approaches 600° C.

Catalyst activator, in particular, a catalyst activator for heat conditioning a catalyst. The activator includes a vessel for containing a catalyst charge having an internal diameter of at least 1.2 meters and/or an internal volume of at least 5 m3; a fluidisation grid plate disposed in the vessel, the fluidisation grid plate having an upper major surface and a lower major surface; an array of generally conical depressions in the upper major surface that overlap by less than 17%; and an array of holes perforating the fluidisation grid plate, the holes extending from at least some of the generally conical depressions through the lower surface.

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Small, little-known companies are selling CBD as a cure-all. While the Trump Administration has deregulated right and left — for instance, allowing polluters to go hog wild — the Food and Drug Administration isn't effing around when it comes to cracking down on companies selling supposed cures for the COVID-19 virus. Several of those targeted companies make CBD.…

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An electrical voltage-generating piezoelectric device comprising at least a first blade (1) with a curved portion (10) defining a first arm (11) and a second arm (12) of the blade, the first arm (11) being intended to be fastened to a fixed support, the second arm (12) being substantially flat and having a free end (120) designed to oscillate around its resting position under the effect of mechanical force, at least one piezoelectric element (31) resting upon one of the main surfaces (14) of the second arm (12) of the first blade. The device also includes a second blade (2) identical in structure to the first blade (1), the first arms (11, 21) of the first and second blades (1, 2) being fastened together on all or part of their surfaces and being fixed relative to each other.

An energy harvesting device includes: a first nanoporous electrode and a second nanoporous electrode, each of which is configured to which store electrical charge; a first current collector connected to the first nanoporous electrode and a second current collector connected to the second nanoporous electrode; and an enclosure that contains the first and second nanoporous electrodes and the first and second current collectors and transfers a force applied from the outside to the first nanoporous electrode and the second nanoporous electrode, wherein at least one of the first nanoporous electrode and the second nanoporous electrode comprises an ion conductive polymer.