Embodiments include circuits and methods to determine peak current for current regulation. A control signal circuit monitors a current on the primary side of a transformer based a turn on time of a switch coupled to the primary side. The control signal circuit determines whether the monitored current exceeds an over-current protection threshold, and determines a duration that the monitored current exceeds the over-current protection threshold. The control signal circuit determines a peak primary current in the primary side based on the over-current protection threshold, the duration that the monitored current exceeds the over-current protection threshold, and the turn on time of the switch. The control signal circuit controls the turn on time for the switch based on the determined peak primary current.

A light source for a photonic integrated circuit may comprise a reflection coupling layer formed on a substrate in which an optical waveguide is provided, at least one side of the reflection coupling layer being optically connected to the optical waveguide; an optical mode alignment layer provided on the reflection coupling layer; and/or an upper structure provided on the optical mode alignment layer and including an active layer for generating light and a reflection layer provided on the active layer. A light source for a photonic integrated circuit may comprise a lower reflection layer; an optical waveguide optically connected to the lower reflection layer; an optical mode alignment layer on the lower reflection layer; an active layer on the optical mode alignment layer; and/or an upper reflection layer on the active layer.

A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (fs) and the destination frequency (fd). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.

A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack. A feedback connection is from an output of the last stage to an input of the first stage. At least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device is coupled between the first gate stack and a ground pad, and/or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device is coupled between the second gate stack a power supply pad.

A circuit includes first and second transconductance stages that generate first and second currents, respectively, in response to an input signal. A current combiner circuit selectively couples the first current to a first output, selectively couples the second current to the first output, selectively couples the first current to a second output, and selectively couples the second current to the second output. In response to the first current being coupled to both the first and second outputs, the current combiner circuit couples the second current to both the first and second outputs. In response to the first current being decoupled from the second output, the current combiner circuit decouples the second current from both the first and second outputs. In response to the first current being decoupled from the first output, the current combiner circuit decouples the second current from both the first and second outputs.

A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.

Embodiments of resonator circuits and modulating resonators and are described generally herein. One or more acoustic wave resonators may be coupled in series or parallel to generate tunable filters. One or more acoustic wave resonances may be modulated by one or more capacitors or tunable capacitors. One or more acoustic wave modules may also be switchable in a filter. Other embodiments may be described and claimed.

A system for detecting a short-circuited ultracapacitor cell in a machine is disclosed. The system may have a memory that stores instructions and one or more processors capable of executing the instructions. The one or more processors may be configured to perform cell balancing among ultracapacitor cells arranged within two or more ultracapacitor modules, each ultracapacitor module including at least two ultracapacitor cells connected in series. The one or more processors may be further configured to measure a module voltage generated by each of the plurality of ultracapacitor modules after performing the cell balancing and before applying a load of the machine to the ultracapacitor modules, and determine whether an ultracapacitor cell among the plurality of ultracapacitor cells is short-circuited based on a comparison of the measured module voltages.

Differential amplifier circuits for LDMOS-based amplifiers are disclosed. The differential amplifier circuits comprise a high resistivity substrate and separate DC and AC ground connections. Such amplifier circuits may not require thru-substrate vias for ground connection.

A current mirror circuit, receiving an input current and outputting a plurality of mirroring currents, comprising: a first transistor, wherein a control terminal and a first terminal of the first transistor are connected to a first mirroring current of the input current; at least one second transistor, wherein a control terminal and a first terminal of the at least one second transistor are connected to the at least one second mirroring current of the input current; and a plurality of third transistors, outputting the plurality of mirroring currents from first terminals of the plurality of third transistors, wherein control terminals of the plurality of third transistors are connected to control terminals of the first transistor and the at least one second transistor. The first transistor, the at least one second transistor and the plurality of third transistors are identical.

A sequential monitoring system is for an interlocking logic system and a track circuit system including a plurality of track circuits. The sequential monitoring system includes an interface between the interlocking logic system and the track circuit system; and a processor structured to monitor a state of each of the track circuits, validate a sequence of state changes of the track circuits, and interrupt and correct invalid track circuit state indications between the track circuit system and the interlocking logic system. The interface normally passes inputs from the track circuit system to outputs to the interlocking logic system. When an out of sequence event occurs, the processor applies a quarantine to a minimum of three of the track circuits in a quarantined area, thereby inhibiting use of an unoccupied track circuit in the quarantined area.

An industrial fluid circulating system having at least one fluid circulation circuit, includes a plurality of pumps connected in parallel to circulate the fluid through each of the fluid circulation circuit, a separate motor driving each pump, a load detector to sense operating loads on the system and each circuit, and a speed control to vary the speed of each motor to thereby vary the pumping capacity of each pump in response to the detected load on the system, each pump of each respective circuit running simultaneously at a substantially similar speed or a predetermined equal reduced speed of the respective circuit or an almost equal reduced speed or a similar reduced speed.

A semiconductor device includes a plurality of circuits, a general bus configured to be connected to each of the plurality of circuits and to provide a general channel among the plurality of circuits, and a designated bus configured to be connected to a subgroup of circuits from among the plurality of circuits and to provide a designated channel among the subgroup of circuits.

The present disclosure is directed to a refractory metal core for use in forming varying thickness microcircuits in turbine engine components, a process for forming the refractory metal core, and a process for forming the turbine engine components. The refractory metal core is used in the casting of a turbine engine component. The core is formed by a sheet of refractory metal material having a curved trailing edge portion integrally formed with a leading edge portion.

An example circuit includes: a slew rate driver configured to provide an output voltage; a first voltage provider configured to provide a first input voltage to the slew rate driver in response to the output voltage being within a first range; and a second voltage provider configured to provide a second input voltage to the slew rate driver in response to the output voltage being within a second range. The slew rate driver is further configured to change the output voltage based at least in part on the first input voltage or the second input voltage.

Provided are superconducting circuits and, more specifically, methods of forming such circuits. A method may involve forming a silicon-containing low loss dielectric (LLD) layer over a metal electrode such that metal carbides at the interface of the LLD layer and electrode. The LLD layer may be formed using chemical vapor deposition (CVD) at a temperature of less than about 500° C. At such a low temperature, metal silicides may not form even though silicon containing precursors may come in contact with metal of the electrode. Silicon containing precursors having silane molecules in which two silicon atoms bonded to each other (e.g., di-silane and tri-silane) may be used at these low temperatures. The LLD layer may include amorphous silicon, silicon oxide, or silicon nitride, and this layer may directly interface one or more metal electrodes. The thickness of LLD layer may be between about 1,000 Angstroms and 10,000 Angstroms.

A testing device for FMCW radar includes an input for receiving a chirp signal generated by the radar. An IQ down-converter coupled to the input down-converts the chirp signal. A digitizer extracts digitized IQ signals from the down-converted chirp signal. A processor coupled to the digitizer determines at least one of frequency linearity and phase noise of the chirp signal.

In a piezoelectric ejector assembly, a piezoelectric actuator is attached to an ejector mechanism, while a drive signal generator and a controller are coupled to the actuator. The drive signal generator is configured to generate a drive signal for driving the actuator to oscillate the ejector assembly. The controller is configured to control the drive signal generator to drive the actuator at a resonant frequency of the ejector assembly, and an auto-tuning circuit is provided to define the optimum drive signal frequency.

Continuous-time analog-to-digital converters (ADCs) such as continuous-time delta-sigma ADCs and continuous-time pipeline ADCs, has input resistor structure at the input. The input resistor structure is typically tunable, and the tunability is usually provided by metal-oxide semiconductor field effect transistor (MOSFET) switches. Core MOSFETs, which has a terminal-to-terminal voltage

Technologies for controlling degradation of a sensor mote including detecting a trigger event and initiating degradation of at least a portion of the sensor mote in response to the trigger event. The trigger event may be embodied as any type of event detectable by the sensor mote such as a trigger signal, particular sensed data, expiration of a reference time period, completion of a task, and so forth. The sensor mote may imitate the degradation by, for example, controlling a valve to release a chemical stored in the sensor mote or allow a substance into the sensor mote.

The MIT Press, ISBN-13: 978-0262039802, English, 464 pages, 2019, USA

Nam June Paik is back in the limelight, thanks to an important historical exhibition at Tate Modern (see the report in this issue). There has →

Incoming OSU Welding Engineering freshman Sam is getting excited for classes to start in a few weeks.  This summer, he’s been working two jobs, including an internship at OSU’s ElectroScience Lab. As part of the project I’m working on there, I obtained a radio assembly kit online and put it together in order to experience […]

MECP2 gain-of-function and loss-of-function in genetically engineered monkeys recapitulates typical phenotypes in patients with autism, yet where MECP2 mutation affects the monkey brain and whether/how it relates to autism pathology remain unknown. Here we report a combination of gene–circuit–behavior analyses including MECP2 coexpression network, locomotive and cognitive behaviors, and EEG and fMRI findings in 5 MECP2 overexpressed monkeys (Macaca fascicularis; 3 females) and 20 wild-type monkeys (Macaca fascicularis; 11 females). Whole-genome expression analysis revealed MECP2 coexpressed genes significantly enriched in GABA-related signaling pathways, whereby reduced β-synchronization within fronto-parieto-occipital networks was associated with abnormal locomotive behaviors. Meanwhile, MECP2-induced hyperconnectivity in prefrontal and cingulate networks accounted for regressive deficits in reversal learning tasks. Furthermore, we stratified a cohort of 49 patients with autism and 72 healthy controls of 1112 subjects using functional connectivity patterns, and identified dysconnectivity profiles similar to those in monkeys. By establishing a circuit-based construct link between genetically defined models and stratified patients, these results pave new avenues to deconstruct clinical heterogeneity and advance accurate diagnosis in psychiatric disorders.

SIGNIFICANCE STATEMENT Autism spectrum disorder (ASD) is a complex disorder with co-occurring symptoms caused by multiple genetic variations and brain circuit abnormalities. To dissect the gene–circuit–behavior causal chain underlying ASD, animal models are established by manipulating causative genes such as MECP2. However, it is unknown whether such models have captured any circuit-level pathology in ASD patients, as demonstrated by human brain imaging studies. Here, we use transgenic macaques to examine the causal effect of MECP2 overexpression on gene coexpression, brain circuits, and behaviors. For the first time, we demonstrate that the circuit abnormalities linked to MECP2 and autism-like traits in the monkeys can be mapped to a homogeneous ASD subgroup, thereby offering a new strategy to deconstruct clinical heterogeneity in ASD.

Although pain is a prevalent nonmotor symptom in Parkinson’s disease (PD), it is undertreated, in part because of our limited understanding of the underlying mechanisms. Considering that the basal ganglia are implicated in pain sensation, and that their synaptic outputs are controlled by the subthalamic nucleus (STN), we hypothesized that...

Thanks to its unique three-dimensional manufacturing capacity, ultrafast laser writing is a prime candidate to meet the growing demand for the miniaturization of photonic circuitry, e.g., for scaling up optical quantum computers capacity. Towards this goal, scientists from Canada discovered a phenomenon related to the material electronic resonance that allows a much greater miniaturization of the laser written devices. Surprisingly, the new phenomenon allows other intriguing applications such as a new concept of invisibility.

On May 15, 2009, the Fifth Circuit, in Klamath Strategic Investment Fund v. United States (No. 07-40861), affirmed the district court’s decision denying over $50 million in claimed tax losses arising from the taxpayers’ investment in a “Son of Boss (BLIPS)” tax shelter.

Peter Picone, 41, of Methuen, Massachusetts, pleaded guilty today in U.S. District Court in Hartford, Connecticut to importing thousands of counterfeit integrated circuits (ICs) from China and Hong Kong and then reselling them to U.S. customers.

Imports - Making & Breaking Elec. Circuits Apparatus in Japan increased to 49101.70 JPY Million in March from 33979.76 JPY Million in February of 2020. Imports - Making & Breaking Elec. Circuits Apparat in Japan averaged 25033.77 JPY Million from 1988 until 2020, reaching an all time high of 56325.62 JPY Million in November of 2017 and a record low of 2340.21 JPY Million in April of 1988. This page includes a chart with historical data for Japan Imports of Making & Breaking Elec. Circuits Appar.

In the wake coronavirus pandemic, the first 10 races of the 2020 calender have either been called off or postponed.

Hayden Library - PN1995.9.H6 R57 2018

Alexander, Charles K., author

Rizzi, Peter A

IEEE / Institute of Electrical and Electronics Engineers Incorporated

IEEE / Institute of Electrical and Electronics Engineers Incorporated

IEEE / Institute of Electrical and Electronics Engineers Incorporated

IEEE / Institute of Electrical and Electronics Engineers Incorporated

Online Resource

Online Resource

Online Resource

Rodriguez, Esther

Online Resource