A trailer for transporting an agricultural harvesting head includes a pair of saddles for supporting the head. The saddles are adjustably mounted on the trailer frame and are simultaneously moved together by an actuator operated by a remote control. The saddles are connected by telescoping rod sections so that the spacing between the saddles is adjustable.

A vehicle restraint system for an auto-rack railroad car which includes an active chock and an anchor chock configured to co-act to secure a vehicle in the auto-rack railroad car. In various embodiments, each chock has a chock body including a substantially diamond shaped elongated tube which includes four integrally connected elongated walls. In various embodiments, for each chock, various components of that chock extend substantially along longitudinal axis that lie in the same or substantially the same vertical plane as the apex and trough of the substantially diamond shaped elongated tube of the chock body. The active and anchor chocks: (a) have a lower height than known commercially available vehicle restraints; (b) have a smaller width than known commercially available vehicle restraints; (c) position the strap and the torque tube closer to the tire of the wheel than any known commercially available vehicle restraints; (d) take up a smaller area of each safe zone adjacent to the wheel than known commercially available vehicle restraints; (e) provide a greater strength to size ratio than known commercially available vehicle restraints; and (f) are easy to operate, install, and remove.

A transportation and storage system for a wind turbine rotor blade comprises a tip end frame assembly comprising a tip end receptacle and a tip end frame. The tip end receptacle comprises an upwardly open tip end-receiving space for receiving a portion of the tip end of the blade and having a supporting surface for supporting the blade, a lower surface allowing the tip end receptacle to rest upright on a substantially horizontal surface, such as the ground, and releasable retaining means for releasably retaining the tip end of the blade in the receiving space of the tip end receptacle. The tip end frame comprises an upwardly open receptacle-receiving space for receiving the receptacle and provided with positioning means for positioning the receptacle in the tip end frame. A base part defines a bottom surface allowing the tip end frame to rest upright on the ground.

An apparatus for securing a cargo item within a cargo area that is defined by a pickup truck bed and a bed liner that is disposed within the pickup truck bed, the bed liner defining a plurality of elongate grooves. The apparatus includes a rod that extends along an axis in an axial direction of the rod. An engaging structure is receivable within at least one groove from the plurality of elongate grooves of the bed liner for engagement with the bed liner. An adjustable connecting structure connects the engaging structure to the rod and allows adjustment of an axial position of the engaging structure along the rod in the axial direction of the rod. A body is connected to the rod for engaging the cargo item.

A vehicle load securing apparatus comprising a frame including opposite side walls and an end wall extending between the side walls, with the frame having open sides positioned in opposition to each other. A spool is rotatably mounted on the frame and includes a rotating shaft, and a length of an elongate member at least partially wrapped about the spool with a hook mounted thereon. A ratcheting structure may control rotation of the spool with engaged position in which the ratcheting structure resists rotation of the spool in an unwind direction and a disengaged position in which the ratcheting structure permits rotation of the spool in the unwind direction. The shaft may have a first end portion extending through one of the side walls of the frame, and a section of the first end portion having a substantially hexagonal cross-sectional shape for engagement by a tool.

A bull ring for a vehicle comprises a top plate coupled to a rotating plate having a tie-down. Two opposing rail flanges extend from the rotating plate and a fastener selectively couples the rotating plate in a securing position relative to the top plate. The rail flanges extend beyond an outer edge of the top plate to define a clamping region with the top plate.

A blade holding apparatus for holding one end of a wind turbine blade during handling, which blade holding apparatus includes a support structure including an opening for accommodating one end of the wind turbine blade, a clamping arrangement arranged in the opening, which clamping arrangement is realized to exert a clamping force on the wind turbine blade, and a locking arrangement for locking the clamping arrangement relative to the support structure. A method of operating such a blade holding apparatus during a handling procedure of a wind turbine blade is also provided.

A side rail of a floor assembly of a trailer, such as a flatbed trailer, including a channel formed in a top wall of the side rail and an aperture formed in the top wall of the side rail at a location spaced-apart from the channel. The channel extends along a length of the side rail and is configured to receive a first cargo restraint device therein. The aperture is configured to receive a second cargo restraint device therein.

A cargo holding apparatus configured to secure cargo in a pickup truck cargo bed and facilitate unloading of the cargo therefrom is provided with a holding frame having cross members forming a top and a bottom of the holding frame; and side support members forming a left side and a right side of the holding frame, where the cross members being joined to the side support members at each end; a strap secured to each side support member, the strap being dimensioned to extend at least a length of the cargo bed; and a clamping member disposed and a left and a right side vertical walls of the cargo bed at a position nearest a lift gate of the cargo bed, each of the straps being fed through respective clamping members, the respective clamping members securely holding each strap when in an engaged aspect and allowing each strap to slide unrestricted when in a disengaged aspect.

Method and apparatus for handling aerogenerator blades that provide a versatile means for handling aerogenerator blades without an unbalanced distribution of the loads in the blade. The method comprises positioning an upper mounting part (103) over the blade after the upper mold has been retracted; lifting the blade with the upper mounting part from the under mold using a lifting means; positioning the blade over an under mounting part (104) which is fixedly attached to an inferior movable support (102); attaching the upper mounting part to the under mounting part, wherein the upper and under mounting parts together have the inner surface substantially corresponding to the shape of the blade outer profile section. The invention further comprises an apparatus for handling aerogenerator blades.

An automatic lock affixed to a cargo container for interconnecting two stacked containers, and for automatically locking and unlocking without reliance upon the overcoming of a friction force to release the device.

A cargo rack for transferring loads between a marine vessel and an offshore marine platform provides a frame having a front, a rear, and upper and lower end portions. The lower end of the frame has a perimeter beam base, a raised floor and a pair of open-ended parallel fork tine tubes that communicate with the perimeter beam at the front and rear of the frame. The frame includes a plurality of fixed side walls extending upwardly from the perimeter beam. A plurality of gates are movably mounted on the frame, each gate being movable between open and closed positions, the gates enabling a forklift to place loads on the floor. The frame has vertically extending positioning beams that segment the floor into a plurality of load-holding positions. Each load holding position has positioning beams that laterally hold a load module in position on the floor.

A seat fixing device for fixing an air passenger seat to a floor of an aircraft includes at least one fastening rail (10) in the form or a hollow profile, which is provided with a longitudinal channel (14) delimiting the free flanks (16) of the profile on the top part thereof (12) oriented to the seat. The channel includes through openings (18) located in a predetermined modular dimension, which enlarge the free input section and are used for inserting at least one snap-locking part (24) of a locking body (26). The looking body (26) is movable to a clamping position with the profile (16) of the hollow profile (14) by the relative displacement of each snap-locking part (24) in a perpendicular direction with respect to the longitudinal axis (28) of the fastening rail (10). The fixing device provides an eccentric drive (30) of the locking body (26) for carrying out relative displacement, which reduces assembly costs.

An apparatus for selectively securing a boat to a trailer may include a hull contact structure for abutting against the boat hull, and a releasable gripping structure positioned adjacent the hull contact structure to engage the boat's securing loop and selectively lock onto the loop to hold the boat to the trailer.

An apparatus and method for applying an underlayment layer to trucking cargo are provided. The underlayment layer may be formed into a roll with a rod disposed therethrough. The roll may be supported by a frame. The roll can be configured to move vertically with respect to the ground. A trailer carrying trucking cargo can be stationed beneath the frame. The underlayment layer may unwound and dispensed from the roll. In order to drape the trucking cargo with the underlayment layer, the roll may be moved horizontally over the frame in addition to or alternatively to having the trucking cargo driven horizontally with respect to the roll.

A novel configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations is provided. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. The configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. The configuration network is a pipelined network.

An apparatus relates generally to a clock generator is disclosed. The clock generator is coupled to receive an input clock signal and further coupled to provide an output clock signal. An address and control register is coupled to receive an address signal and the output clock signal. An access generator is coupled to receive the output clock signal. The clock generator includes: an input node coupled to receive the input clock signal; at least one pulse generator coupled to the input node to receive the input clock signal and further coupled to provide a clock control signal; and a control gate coupled to the input node to receive the input signal and further coupled to the at least one pulse generator to receive the clock control signal. The clock control signal is provided in a non-toggling state for a high-frequency mode and in a toggling state for a low-frequency mode.

A latch circuit includes a latch unit and a clock propagation suppressing unit. The latch circuit holds and outputs input data of 0 or 1. The clock propagation suppressing unit compares the input data input to the latch unit with output data output from the latch unit. When it is detected that the input data matches the output data at 0, or that the input data matches the output data at 1, an externally input clock signal is prevented from propagating to the latch unit.

A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

A bridge output circuit includes an output terminal, a high side transistor, a low side transistor, a high side driver for controlling a gate voltage of the high side transistor, a low side driver for controlling a gate voltage of the low side transistor, and a controller for controlling the high side and low side drivers. The low side driver includes a first current source, a second current source, and a first assist circuit. The controller is configured to control the turning-on and turning-off states of the first current source, the second current source and the first assist circuit.

An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.

Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc.

Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.

A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.

A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.

An impedance tuning circuit includes a calibration unit and a post-processing unit. The calibration unit generates an initial pull-up code and an initial pull-down code by performing a calibration operation using an external resistor during an initial impedance tuning operation. The post-processing unit outputs the initial pull-up code and the initial pull-down code as a final pull-up code and a final pull-down code during the initial impedance tuning operation, and generates the final pull-up code and the final pull-down code by using the initial pull-up code and the initial pull-down code during a subsequent impedance tuning operation.

A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

An isolator circuit capable of two-way electrical disconnection and a semiconductor device including the isolator circuit are provided. A data holding portion is provided in an isolator circuit without the need for additional provision of a data holding portion outside the isolator circuit, and data which is to be input to a logic circuit that is in an off state at this moment is stored in the data holding portion. The data holding portion may be formed using a transistor with small off-state current and a buffer. The buffer can include an inverter circuit and a clocked inverter circuit.

Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.

There is disclosed a gate driver, a driving circuit, and a liquid crystal display (LCD), wherein the gate driver comprises input terminals for inputting a CPV signal, an OE signal, and an STV signal, and output terminals for outputting a CKV signal and a CKVB signal, and a processing circuit is connected between the input terminals and the output terminals for processing the CPV signal, the OE signal, and the STV signal such that a preset time interval is present between the falling edge of the CKV signal and the rising edge of the CKVB signal during one period of the CKV signal, or a preset time interval is present between the rising edge of the CKV signal and the falling edge of the CKVB signal during one period of the CKVB signal.

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

The present invention relates to a method for downloading a binary configuration file in a programmable circuit implemented in a device. The device comprises at least one central processing unit, a plurality of connectors, and a programmable circuit enabling all or a part of the signals received by said connectors to be processed and transmitted to at least one other circuit of the device. The device analyzes the signals present on the connectors in order to define what other devices are connected and whether the connections are operational. Then, a configuration file is selected from among a set of configuration files according to the operational connections and is downloaded from a memory of the device into the programmable circuit. The invention also relates to a device having a component programmed according to the method previously described.

The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

An integrated circuit (IC) with a novel configurable routing fabric is provided. The configurable routing fabric has signal paths that propagate signals between user registers on user clock cycles. Each signal path includes a set of configurable storage elements and a set of configurable logic elements. Each configurable storage element in the path is reconfigurable on every sub-cycle of the user clock cycle to either store an incoming signal or to pass the incoming signal transparently.

Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.

A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

According to one embodiment, a first oscillator has an oscillation frequency that is changed depending on a temperature. A second oscillator has different temperature characteristics from the first oscillator. An on-chip heater heats the first oscillator and the second oscillator. A counter counts a first oscillation signal of the first oscillator. An ADPLL generates a third oscillation signal on the basis of a second oscillation signal of the second oscillator and corrects the frequency of the third oscillation signal on the basis of a count value of the counter.

The present disclosure relates to nanoresonator oscillators or NEMS (nanoelectromechanical system) oscillators. A circuit for measuring the oscillation frequency of a resonator is provided, comprising a first phase-locked feedback loop locking the frequency of a controlled oscillator at the resonant frequency of the resonator, this first loop comprising a first phase comparator. Furthermore, a second feedback loop is provided which searches for and stores the loop phase shift introduced by the resonator and its amplification circuit when they are locked at resonance by the first loop. The first and the second loops operate during a calibration phase. A third self-oscillation loop is set up during an operation phase. It directly links the output of the controllable phase shifter to the input of the resonator. The phase shifter receives the phase-shift control stored by the second loop.

A resonator element includes a substrate including a first principal surface and a second principal surface respectively forming an obverse surface and a reverse surface of the substrate, and vibrating in a thickness-shear vibration mode, a first excitation electrode disposed on the first principal surface, and a second excitation electrode disposed on the second principal surface, and being larger than the first excitation electrode in a plan view, the first excitation electrode is disposed so as to fit into an outer edge of the second excitation electrode in the plan view, and the energy trap confficient M fulfills 15.5≦M≦36.7.

A resonator element includes a substrate vibrating in a thickness-shear vibration mode, a first excitation electrode disposed on one principal surface of the substrate, and has a shape obtained by cutting out four corners of a quadrangle, and a second excitation electrode disposed on the other principal surface of the substrate, and a ratio (S2/S1) between the area S1 of the quadrangle and the area S2 of the first excitation electrode fulfills 87.7%≦(S2/S1)

An oscillating device includes a temperature compensated oscillator that compensates a frequency temperature characteristic in a temperature compensation range including apart of a first temperature range, and a temperature control circuit that includes a heater and controls a temperature of a quartz crystal resonator of the temperature compensated oscillator into a second temperature range included in the temperature compensation range. Further, the temperature compensation range of the temperature compensated oscillator may include a part of the first temperature range in which compensation can be performed by first-order approximation.

A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

A self-feedback random generator comprises a digital-to-analog converter, a digital oscillator, a frequency-modulating unit and a first D-type flip-flop. The digital-to-analog converter receives a digital random-code signal and the digital random-code signal is converted to corresponding analog random signal. The frequency-modulating unit modulates frequency of first digital oscillating signal so as to increase random of frequency of first digital oscillating signal according to voltage value of the analog random signal, and accordingly outputs a second digital oscillating signal. The first D-type flip-flop receives the second digital oscillating signal and a clock signal, and reads the second digital oscillating signal through utilizing the clock signal so as to outputs the digital random-code signal, wherein frequency of the clock signal is smaller than frequency of the first digital oscillating signal, and random of frequency of the second digital oscillating signal corresponds to random of the digital random-code signal.

There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (100), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider (112) for feeding back an output of a VCO (115) of an output stage to a preceding stage is generated using an error signal from an accumulator (120). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector (140) are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider (112) is suppressed.

A digitally controlled oscillator has a high-order ΔΣ modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ΔΣ modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.

An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.