1 Peruvian Nuevo Sol = 0.8687 Lithuanian Lita

Lawrence, Kansas – The Haskell men's golf team finished eighth at the Ottawa Invitational held at Eagle Bend Golf Course on Tuesday evening. The Indians finished with a two round score of 678. 

Lawrence, Kansas – The Haskell men's golf team finished 8th out of 9 teams at the Ottawa Spring Invitational held at Eagle Bend Golf Course on Monday. The Indians finished with a round score of 344 and the second round was cancelled due to snow on the course. 

Maryville, MO – The Haskell Men's golf team competed in the Graceland Invitational which was cut short due to inclement weather conditions on the second day. 

Lawrence, Kansas – The Haskell men's golf team finished 8th out of 11 teams in the Ottawa Invitational held at Eagle Bend Golf Course in Lawrence, Kansas on Monday and Tuesday. The Indians finished with a round score of 321, 331, with a total team score 652.

The collegiate races for the Haskell Invitational have been rescheduled for October 11 at 4pm.

This week Cross Country is training for their first home meet on Saturday October 12, 2019 at 9:15 & 10:00 am during Homcoming Weekend!

Haskell Men's Cross CountryTop 20 finishers from Haskell's Invitational. From left to right Dorian Daw, Ronson Begay, Uriah Little Owl & Joshua Garcia (not pictured Tristan Antonio).

Women's Cross Country Pictured, Chantel Yazzie crossing the finish line as Haskell's first Women's Cross Country runner to cross at the Haskell Invitational. 

1 Dominican Peso = 0.0536 Lithuanian Lita

Ottawa, Kansas - The Haskell Indian Nations University Men's track and field teams competed at the Ottawa Braves Invitational on Saturday.

1 Papua New Guinean Kina = 0.8608 Lithuanian Lita

1 Brunei Dollar = 2.0893 Lithuanian Lita

Let’s face it – the EDA industry needs new people and new ideas. One of the best places to find both is academia, and a presentation at the Cadence Theater at the recent Design Automation Conference (DAC 2015) described collaboration models that are working today.

The presentation was titled “Industry/Academia Engagement Models – From PhD Contests to R&D Collaborations.” It included these speakers, shown from left to right in the photo below:

• Prof. Xin Li, Electrical and Computer Engineering, Carnegie-Mellon University (CMU)
• Chuck Alpert, Senior Software Architect, Cadence
• Prof. Laleh Behjat, Department of Electrical and Computer Engineering, University of Calgary

Alpert, who was filling in for Zhuo Li, Software Architect at Cadence, was the vice chair of DAC 2015 and will be the general chair of DAC 2016 in Austin, Texas. “My team at Cadence really likes to collaborate with universities,” he said. “We’re a big proponent of education because we really need the best and brightest students in our industry.”

Contests Boost EDA Research

One way that Cadence collaborates with academia is participation in contests. “It’s a great way to formulate problems to academia,” Alpert said. “We can have the universities work on these problems and get some strategic direction.”

For example, Cadence has been involved with the annual CAD contest at the International Conference on Computer-Aided Design (ICCAD) since the contest was launched in 2012. This is the largest worldwide EDA R&D contest, and it is sponsored by the IEEE Council on EDA (CEDA) and the Taiwan Ministry of Education. Its goals are to boost EDA research in advanced real-world problems and to foster industry-academia collaboration.

Contestants can participate in one of more problems in the three areas of system design, logic synthesis and verification, and physical design. The 2015 contest has attracted 112 teams from 12 regions. Cadence contributes one problem per year in the logic synthesis area. Zhuo Li was the 2012 co-chair and the 2013 chair. The awards will be given at ICCAD in November 2015.

Another step that Cadence has taken, Alpert said, is to “hire lots of interns.” His own team has four interns at the moment. One advantage to interning at Cadence, he said, is that students get to see real-world designs and understand how the tools work. “It helps you drive your research in a more practical and useful direction,” he said.

The Cadence Academic Network co-sponsors the ACM SIGDA PhD Forum at DAC, and Xin Li and Zhuo Li are on the organizing committee. This event is a poster session for PhD students to present and discuss their dissertation research with people in the EDA community. This year’s forum was “packed,” Alpert said, and it’s clear that the event needs a bigger room.

Finally, Alpert noted, Cadence researchers write and publish technical papers at DAC and other conferences, and Cadence people serve on the DAC technical program committee. “We try to be involved with the academic community on a regular basis,” Alpert said. “We want the best and the brightest people to go into EDA because there is still so much innovation that’s needed. It’s a really cool place to be.”

Research Collaboration Exposes Failure Rates

Xin Li presented an example of a successful research collaboration between CMU and Cadence. The challenge was to find a better way to estimate potential failure rates in memory. As noted in a previous blog post, PhD student Shupeng Sun met this challenge with a new statistical methodology that won a Best Poster award at the ACM SIGDA PhD Forum at DAC 2014.

The new methodology is called Scaled-Sigma Sampling (SSS). It calculates the failure rate and accounts for variability in the manufacturing process while only requiring a few hundred, or a few thousand, sample circuit blocks. Previously, millions of samples were required for an accurate validation of a new design, and each sample could take minutes or hours to simulate. It could take a few weeks or months to run one validation.

The SSS methodology requires greatly reduced simulation times. It makes it possible, Li noted, to run simulations overnight and see the results in the morning.

Li shared his secret for success in collaborations. “I want to emphasize that before the collaboration, you have to understand the goal. If you don’t have a clear goal, don’t collaborate. Once you define the goal, stick to it and make it happen.”

Contest Provides Learning Experience

Last year Laleh Behjat handed two of her new PhD students a challenge. “I told them there is an ISPD [International Symposium for Physical Design] contest on placement, and I expect you to participate and I expect you to win. Not knowing anything about placement, I don’t think they realized what I was asking them.”

The 2015 contest was called the Blockage-Aware Detailed Routing-Driven Placement Contest. Results were announced at the end of March at ISPD. And the University of Calgary team, despite its lack of placement experience, took second place.

Such contests provide a good learning tool, according to Behjat. Graduate students in EDA, she said, “have to be good programmers. They have to work in teams and be collaborative, be able to innovate, and solve the hardest problems I have seen in engineering and science. And they have to think outside the box.” A contest can bring out all these attributes, she said.

Further, Behjat noted, contest participants had access to benchmarks and to a placement tool. They didn’t have to write tools to find out if their results were good. Industry sponsors, meanwhile, got access to good students and new approaches for solving problems.

“You can see Cadence putting a big amount of time, effort and money to get students here and get them excited about doing contests,” she said. She advised students in the theater audience to “talk to people in the Cadence booth and see if you can have more ideas for collaboration.”

Richard Goering

Related Blog Posts

EDA Plus Academia: A Perfect Game, Set and Match

Cadence Aims to Strengthen Academic Partnerships

BSIM-CMG FinFET Model – How Academia and Industry Empowered the Next Transistor

Is there a better approach to varying the coefficients of a digital IIR over time to adjust the values of its poles and zeros than just recalculating the whole thing every time it changes? For example, lots of synth programs can apply an LFO to the cutoff frequency of a low/high pass filter. I can do some polynomial multiplication to get the coefficients for an IIR filter given its poles and zeros, but am wondering if there is a better way to adjust them over time than simply doing all the calculations over again for new poles/zeros. Particularly, I'm curious if there is a method that will more or less work for an arbitrary number of poles and zeros. You could use a filter implementation (state space) that directly uses the pole/zero values instead of a polynomial walmartone. That might be computationally more expensive, though (as you are taking a trip through the domain of complex numbers even though your inputs and output are real), and possibly numerically iffy.As far as I am aware, modifying filter behavior while introducing as few artefacts as possible is still an area of research. You might get away with just adjusting the filter coefficients if you do it slowly, but this does not mean this is the best method.In an audio application, I assume they do not switch filter coefficients abruptly, but instead do a cross-fade between the (settled) first filter and the (mostly or completely settled) target filter to avoid audible artefacts.

Respected sir,

How can i design and simulate cmos inverter using digital flow and also ineed to do prelayout ans post layout for the same cmos inverter..can i use cadence encounter for this experiments

In last week's post, 1G Mobile: AMPS, TOPS, C-450, Radiocom 2000, and All Those Japanese Ones . I covered 1G mobile, the first analog standards. Then we went digital. 2G The Nordic countries...

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Hello,

I am using Virtuoso 6.1.7.

I am performing the parasitic extraction of a MOM cap array of 32 caps. I use Quantus QRC and I enable field solver. I select “QRCFS” for field solver type and “High” for field solver accuracy. The unit MOM cap is horizontally and vertically symmetric. The array looks like the sketch below and there are no other structures except the unit caps:

Rationally speaking, the capacitance values of the unit caps should be symmetric with respect to a vertical symmetry axis that is between cap16 and cap17 (shown with dashed red line). For example,

the capacitance of cap1 should be equal to the capacitance of cap32

the capacitance of cap2 should be equal to the capacitance of cap31

etc. as there are no other structures around the caps that might create some asymmetry.

Nevertheless, what I observe is the following after the parasitic extraction:

As it can be seen, the result is not symmetric contrary to what is expected. I should also add that I do not observe this when I perform parasitic extraction with no filed solver.

Why do I get this result? Is it an artifact resulting from the field solver tool (my conclusion was yes but still it must be verified)? If not, how can something like this happen?

Many thanks in advance.

Best regards,

Can

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A deficiency in handling authentication and authorization has been found with Kguard 104/108/v2 models. While password-based authentication is used by the ActiveX component to protect the login page, all the communication to the application server at port 9000 allows data to be communicated directly with insufficient or improper authorization. Proof of concept exploit included.

•Dassault Systèmes becomes the first and only software provider today to be recognized as Groupe PSA’s preferred digital partner •Dassault Systèmes and Groupe PSA engage in long-term strategy with the intent to further deploy the 3DEXPERIENCE platform •New level of partnership will enable Groupe PSA to improve efficiency and innovation in challenging marketplace

•Lockheed Martin deploys the 3DEXPERIENCE platform as an engineering and manufacturing planning toolset •Multi-year collaboration aims to speed timelines and improve efficiencies of next generation products •Digital experience platform approach drives advances in complex, sophisticated aircraft innovation

IBM Bigfix Platform version 9.5.9.62 suffers from an arbitrary file upload vulnerability as root that can achieve remote code execution.

Digital Whisper Electronic Magazine issue 87. Written in Hebrew.

Digital Whisper Electronic Magazine issue 88. Written in Hebrew.