A GOA (Gate driver On Array) for an LCD (Liquid Crystal Display) device is disclosed herein. The LCD device comprises a plurality of scanning lines. The GOA circuit comprises a plurality of GOA units, which are cascaded with each other as a plurality of level GOA units. The (n)th level GOA unit comprises a clock circuit, a pull-down circuit, a bootstrap capacitor circuit, a pull-up circuit, and a pull-down sustain circuit, to improve the color shift issue of a Tri-gate.

A driver IC for driving a display panel, a display device and a method for driving the driver IC are provided. The driver IC is provided with N pins corresponding to N signal transmission lines of the display panel respectively. Each pin is connected to one corresponding signal transmission line through one transmission wire. The N pins include a first pin and a second pin. The transmission wires include a first transmission wire connected to the first pin and a second transmission wire connected to the second pin and having a length less than the first transmission wire. The driver IC includes a signal generation module configured to generate N driving signals. The N driving signals include a first driving signal corresponding to the first pin and a second driving signal corresponding to the second pin and having a current intensity less than the first driving signal.

A gate driving circuit in a display device includes a plurality of stages connected in cascade. An ith stage from among the plurality of stages includes a first output unit, a control unit, a pull-down unit, and an inverter unit. The first output unit includes a first output transistor including a first control electrode, a second control electrode overlapping with the first control electrode, an input electrode, and an output electrode. A signal outputted from an inverter unit of an i−1th stage is applied to the second control electrode.

A voltage regulation circuit is provided, including a reverse processing module for processing a first initial voltage of a common voltage generating module so as to obtain a reverse voltage of AC voltage; and an integration module for regulating the first initial voltage according to the reverse voltage of the AC voltage so as to make a liquid crystal drive voltage equal to a preset value. The liquid crystal drive voltage is a difference value of between a second initial voltage and the first initial voltage which is regulated.

A GOA circuit located in a display panel is disclosed. The GOA circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a first boost thin film transistor, a second boost thin film transistor, a boost capacitor, a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, and a fifteenth thin film transistor. Through the first boost thin film transistor, the second boost thin film transistor, and the boost capacitor, a voltage level of a gate output signal outputted by a gate of the second thin film transistor is lifted.

A touch drive circuit and a driving method therefor, an array substrate and a touch display apparatus relate to a field of display. The driving method includes: during touch scanning time period in one frame, by each of output control unit (2), receiving a touch enable signal, a common voltage signal and a touch scanning signal, and receiving an output signal of an shift register unit connected with the output control unit; and outputting, by each of the output control units, the touch scanning signal to a touch drive electrode connected with the touch control unit in a first time period according to the touch enable signal and the output signal of the shift register unit connected with the output control unit, wherein the first time period is scanning time allocated to the touch drive electrode in one frame of time.

A level-shift circuit that operates stably is provided. The level-shift circuit has a function of boosting a first signal having an amplitude voltage between a first voltage and a second voltage to a second signal having an amplitude voltage between a third voltage and the second voltage. The level-shift circuit includes first to eighth transistors. Gates of the third and seventh transistors are electrically connected to a wiring for transmitting a third signal for controlling the amounts of current flowing into one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the fifth transistor, and one of a source and a drain of the sixth transistor.

An exhaust gas recirculation device is provided. The device recirculates, from an exhaust system to an intake system, a part of exhaust gas from a plurality of cylinders of a multi-cylinder engine as EGR gas. The device includes a single EGR pipe extending from the exhaust system toward the intake system, an EGR manifold branching from a downstream end portion of the EGR pipe toward each cylinder, and an EGR valve for adjusting an EGR gas amount. The EGR manifold has one or more common EGR passages having a single pipe portion and branched pipe portions, and one or more independent EGR passages. Each shape of the common and independent EGR passages is set so that a communicating path in the EGR manifold communicating an arbitrary cylinder with a cylinder where combustion is performed subsequently thereto has the same volume for any cylinder combination having the adjacent combustion order.

According to the present disclosure, a fuel supply system having a recirculation loop is provided. The fuel supply system comprises a fuel tank; a return line coupled fluidly to the fuel tank; a fuel manifold; and a recirculation loop, wherein the return line is coupled fluidly to the recirculation loop at a first node to return fuel from the recirculation loop to the fuel tank, and the recirculation loop comprises a heat exchanger positioned downstream of the fuel manifold and upstream of the first node. The recirculation loop may comprise an orifice positioned upstream of the heat exchanger and downstream of the fuel manifold. Additionally, the fuel supply system may further comprise a supply line coupled fluidly to the fuel tank and further coupled fluidly to the recirculation loop at a second node positioned upstream of the fuel manifold and downstream of the first node.

A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.

The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising:first and second conduction electrodes (201, 202);a channel zone (203) arranged between the first and second conduction electrodes;a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222);an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.

A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.

A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.

An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.

A machine for producing circular products such as bottoms and lids of casks comprising a machine base, a blank feeding station, a blank sawing station, a blank chamfering station and a blank positioning station provided on said base in a circumferentially spaced relationship, a vertical main drive shaft rotatably mounted in said base, blank support means fixedly mounted on said drive shaft and having a plurality of spaced blank support discs, blank holding-down means fixedly mounted on said drive shaft and having a plurality of arms each having a downwardly extending shaft on which a blank holding-down member is journalled in opposition to the associated one of said support discs to hold a blank therebetween.

A phase-locked loop circuit and method for providing for compensation for an offset. A phase-locked loop circuit comprises a phase detector, a compensation circuit, a loop filter, and a VCO. The phase detector is coupled to receive a first input signal and a second input signal. The phase detector is configured to output one or more of a plurality of output signals indicative of a difference between the first input signal and the second input signal. The compensation circuit is coupled to receive the output signals and to reduce a voltage offset between the output signals. The compensation circuit is further configured to provide a plurality of compensated output signals. The loop filter is coupled to receive the compensated control signals. The loop filter is configured to output a first control signal. The VCO is coupled to receive the first control signal and to output the second input signal based on the first control signal. A method of operating a phase-locked loop circuit comprises receiving and comparing a first input signal and a second input signal and providing output signals indicative of the comparison. The method compensates for a voltage offset between the output signals and provides compensated output signals indicative of the compensation. The method filters the compensated control signals and provides a control signal indicative of the filtration. The method provides the second input signal based on the first control signal. Lower skew between the input and output may be achieved.

A tractor includes a prime mover, a driven implement selectively engaged with the prime mover, and a switch for selectively engaging and disengaging the driven implement with the prime mover. The switch has three positions including a disengaged position, a momentary position, and an engaged position located between the disengaged position and the momentary position. The prime mover can be started with the switch in the disengaged position. The prime mover can be started with the switch in the engaged position when the switch was previously moved to the momentary position before being moved to the engaged position, such that after operation of the prime mover is stopped, the prime mover can be restarted without changing the position of the switch.

A hydraulic circuit includes a clutch actuator operatively associated with a clutch that may be disposed in a transmission. A hydraulic fluid source supplies pressurized hydraulic fluid for the clutch actuator. To measure the filling rate of the hydraulic actuator, a reference actuator having a predetermined filling rate is disposed in parallel with the hydraulic actuator and in fluid communication with the hydraulic fluid source. If hydraulic pressure associated with the reference actuator does not correspond to the hydraulic pressure associated with the clutch actuator, a compensation valve can appropriately respond by selectively directing hydraulic fluid to or from the clutch actuator. In a further embodiment, the reference actuator and compensation valve may be replaced with an electrohydraulic valve utilizing feedback from the hydraulic pressure present at the inlet of the clutch actuator.

A hydraulic circuit includes a clutch actuator operatively with a clutch that may be disposed in a transmission. A hydraulic fluid source supplies pressurized hydraulic fluid for the clutch actuator. An on-off valve is disposed in fluid communication between the clutch actuator and the hydraulic fluid source; the on-off valve configured to fill the clutch actuator with hydraulic fluid. An accumulator is disposed in parallel with the on-off valve and in fluid communication with the clutch actuator. The accumulator is adapted to receive hydraulic fluid redirected from the clutch actuator and to provide a counter-pressure for modulating the clutch actuator.

A charge pump circuit includes a capacitor, a first switch between the capacitor and a power supply terminal, a second switch between the capacitor and an output terminal, a third switch between the output terminal and the capacitor, a fourth switch between the capacitor and a ground terminal, and a control unit configured to generate control signals for the switches. The control signals include first signals generated during a first period that cause first and third switches to be in an ON state and second and fourth switches to be in an OFF state, second signals generated during a second period that cause first and third switches to be in an OFF state and second and fourth switches to be in an ON state, and third signals generated between the first and second periods, that cause the ON/OFF state of each of the switches to be switched at different times.

A control switch is connected to a power supply voltage and turns on based on a control signal to output a current. A clamp circuit is connected to a load and performs clamp control of the output voltage of the control switch. A current control element conducts or shuts off a current based on the output voltage to be clamp-controlled. A selector switch group includes switches, and performs switching based on a voltage varying with the current control by the current control element, thereby switching between paths for generating an internal power supply. The switch circuit connects or disconnects the coupling between the clamp circuit and the selector switch group.

An active filter device and a circuit arrangement comprising an active filter device are disclosed. In an embodiment the active filter device includes sensor terminals for applying a sensor signal depending on a sensed noise signal, an output terminal for providing a correction signal that is suitable for reducing the noise signal, a signal source adapted for generating a correction signal and a high-pass filter coupled between the sensor terminals and the signal source, wherein the correction signal is generated with a dependence on a high-pass filtered sensor signal.

An SR latch circuit with single gate delay is provided. The circuit has an an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage.

A semiconductor device includes a first transistor and a clamping circuit. The first transistor is arranged to generate an output signal according to a control signal. The clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level.

The present disclosure relates to a delay control circuit arranged for adding delay to a signal. The delay control circuit includes a driver circuit arranged to receive a first signal and to output a second signal. The driver circuit includes a variable load arranged for outputting the second signal by adding delay to the first signal. The delay control circuit also includes a control circuit arranged to receive the first signal and to control the variable load of the driver circuit based on a current state of the first signal and on a control signal indicative of an amount of delay to be added to the first signal in the current state.

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

A load-driving circuit for receiving a supply of power from a power source and driving a load, wherein the load-driving circuit is provided with: a high-side switching element; a low-side switching element; a high-side current detection circuit connected in parallel to the high-side switching element, the high-side current detection circuit detecting a high-side driving current; and a fault detection circuit for detecting the fault state of the load-driving circuit from the output result of the high-side current detection circuit. The high-side current detection circuit is provided with a high-side sense switching circuit operating in response to a gate signal that is different from the high-side switching element, the high-side sense switching circuit comprising a device of the same type as the high-side switching element. The output result of the high-side current detection circuit, the gate signal of the high-side switching element, and the gate signal of the high-side sense switching element are input and the fault states are detected apart from each other when the connection terminal between the load-driving circuit and the load is in a state of short circuit with the positive electrode side of the power source or in a state of short circuit with the negative electrode side of the power source.

A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.

A transmission circuit includes: a first transistor, a first current source, a third transistor. The first transistor has a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit. The first current source is coupled between a gate terminal of the first transistor and a second reference voltage terminal of the transmission circuit. The third transistor has a drain terminal coupled to the first output terminal of the transmission circuit, a source terminal coupled to the second reference voltage terminal of the transmission circuit, and a gate terminal for receiving a first input signal. The first transistor is of a first conducting type, and the second transistor is of a second conducting type different from the first conducting type.

An integrated circuit includes a drive circuit with a first inverter circuit with a first transistor of a first conductivity type and a second transistor of a second conductivity type. The drains of the first and second transistors are connected. An output circuit is provided having a third transistor of the second conductivity with a gate connected to the drains of the first and second transistors. A capacitor is connected between the gate and a drain of the third transistor and has a capacitance greater than 0.5 pF and less than or equal to 3.0 pF. A gate width of the first transistor when divided by a gate width of the third transistor has a value of less than 1/100. The output circuit is configured to output a transmission signal from the drain of the third transistor.

A signal transfer circuit may include a pass gate coupled between first and second nodes; and a control unit suitable for controlling the pass gate to prevent a current flowing from the second node to the first node during turn-on of the pass gate.

A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.

A duty cycle correction circuit may include: a phase mixing section capable of mixing a first integrated signal generated by integrating a positive clock signal, with a first compensation signal generated by differentiating and integrating the positive clock signal and a negative clock signal, respectively, to generate a first phase-mixed signal, and mixing a second integrated signal generated by integrating the negative clock signal, with a second compensation signal generated by integrating and differentiating the positive clock signal and the negative clock signal, respectively, to generate a second phase-mixed signal; and a noise removal section capable of receiving and removing a common mode noise between the first phase-mixed signal and the second phase-mixed signal by adjusting a cross-point therebetween, and outputting first and second duty-corrected clock signals.

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

An apparatus includes an integrated circuit (IC). The IC includes a power controller, which includes a regulator and a controller. The regulator receives a plurality of input voltages and provides a regulated output voltage. The controller controls the regulator to generate the regulated output voltage from the plurality of input voltages. The power controller provides power to a load integrated in the IC from a set of arbitrary input voltages. The set of arbitrary input voltages includes the plurality of input voltages.

An example circuit includes: a slew rate driver configured to provide an output voltage; a first voltage provider configured to provide a first input voltage to the slew rate driver in response to the output voltage being within a first range; and a second voltage provider configured to provide a second input voltage to the slew rate driver in response to the output voltage being within a second range. The slew rate driver is further configured to change the output voltage based at least in part on the first input voltage or the second input voltage.

A circuit suitable for data backup of a logic circuit is provided. The circuit includes first to fourth nodes, a capacitor, first to third transistors, and first and second circuits. Data can be loaded and stored between the circuit and the logic circuit. The first node is electrically connected to a data output terminal of the logic circuit. The second node is electrically connected to a data input terminal of the logic circuit. The capacitor is electrically connected to the third node. The first transistor controls electrical continuity between the first node and the third node. The second transistor controls electrical continuity between the second node and the third node. The third transistor controls electrical continuity between the second node and the fourth node. The first and second circuits have functions of raising gate voltage of the first transistor and raising gate voltage of the second transistor, respectively.

To provide a clock selection circuit capable of reducing clock omission generated when switching from a state of being synchronized with a first clock to a second clock. The clock selection circuit is equipped with a clock detection circuit which detects a first clock to output a detected signal, a switch which outputs the first clock when the detected signal is at a first level and outputs a second clock when the detected signal is at a second level different from the first level, and a one-shot circuit which outputs a one-shot pulse in response to switching of the detected signal from the first level to the second level. The output of the switch and the output of the one-shot circuit are added to be outputted as an output clock.

A clock-signal generator circuit, for generating an output clock signal starting from an input clock signal, includes: a monostable stage having a clock input configured to receive the input clock signal, a control input configured to receive a control signal, and an output configured to supply the output clock signal having a duty cycle variable as a function of the control signal; and a feedback loop, operatively coupled to the monostable stage for generating the control signal as a function of a detected value, and of a desired value, of the duty cycle of the output clock signal.

A device (442) for producing a dynamic reference signal (UREF) for a control circuit for a power semiconductor switch comprises a reference signal generator (442) for providing a dynamic reference signal (UREF), which has a stationary signal level after elapse of a predefined time following a switching process of the power semiconductor switch, a passive charging circuit (450) which is configured to increase a signal level of the dynamic reference signal in reaction to a switching of a control signal of the power semiconductor switch from an OFF state to ON state for at least one part of the predefined time above the stationary signal level, in order to produce the dynamic reference signal and an output (A) for tapping the dynamic reference signal (UREF).

A half-bridge circuit comprises a high supply contact and a low supply contact. A half-bridge output contact is connectable to drive a load and has a high-side between the high supply contact and the half-bridge output contact and a low-side between the half-bridge output contact and the low supply contact. A high-side bidirectional vertical power transistor at the high-side has a source connected to the high supply contact, and a low-side bidirectional vertical power transistor at the low-side, transistor has a source connected to the low supply contact. The high-side bidirectional vertical power transistor and low-side bidirectional vertical power transistor are connected in cascode and share a common drain connected to the half-bridge output contact, and are controllable to alternatingly allow a current flow from the high supply contact to the half-bridge output contact or from the half-bridge output contact to the low supply contact.

A device for controlling a first control gate transistor, including: a second transistor and a third transistor series-connected between a first and a second terminals of application of a power supply voltage, the junction point of these transistors being connected to the gate of the first transistor; a terminal of application of a digital control signal; a circuit for generating an analog signal according to variations of the power supply voltage; and for each of the second and third transistors, a circuit of selection of a control signal of the first transistor representative of said digital signal or of said analog signal.

A driving circuit includes a first switching element operating in a turned-on state or a turned-off state depending on a control voltage; a second switching element operating complementarily to the first switching element depending on the control voltage; a constant voltage circuit unit turning on depending on a source-gate voltage of the first switching element to maintain a constant voltage; a current adjusting circuit operating in a turned-on state or a turned-off state depending on the control voltage, and adjusting an operating current flowing to a ground depending on a current control signal in the turned-on state of the current adjusting circuit; a current control circuit controlling the operating current by providing the current control signal to the current adjusting circuit in a turned-on state of the constant voltage circuit unit; and a signal transfer circuit providing the control voltage to a gate of the second switching element.

A radio-frequency (RF) switch includes a field-effect transistor (FET) disposed between a first node and a second node, the FET having a source, a drain, a gate, and a body. The RF switch further includes a coupling circuit including a first path and a second path, the first path being connected between the gate and one of the source or the drain via a first resistor in series with a first capacitor, the second path being connected between the body and the one of the source or the drain via a second resistor in series with a second capacitor, the coupling circuit configured to allow discharge of interface charge from either or both of the gate and body.

Circular comb for a combing machine for combing textile fibers, comprising a base body with a center longitudinal axis, a peripheral surface and two end faces, a plurality of bar tacks, which are arranged on the peripheral surface of the base body and define a combing region of the circular comb, a plurality of fastening devices attached to the base body for the non-positive connection of one of the bar tacks in each case to the base body and unlocking units to release the non-positive connections, each unlocking unit having an unlocking device and an unlocking means to actuate the unlocking device, wherein the unlocking units are accessible from outside the combing region, in particular from at least one of the end faces, and an additional positive securing connection to secure the bar tacks is provided on the base body.

A printhead cartridge cradle is provided having a frame, a printed circuit board pivotally supported by the frame, a cover pivotally supported by the frame to pivot between a closed position at which a printhead cartridge is secured within the frame and the printed circuit board is pivoted to connect control circuitry on the printed circuit board with a controller of the secured cartridge and an open position at which access for the cartridge with the frame is provided and the printed circuit board is pivoted to disconnect the control circuitry and controller, and a motor operatively connected to a maintenance gear and actuator arrangement and a wiper gear and actuator arrangement for maintaining and wiping a printhead of the secured cartridge under control of the connected control circuitry.

A recording head is configured to write and read data sectors to and from a recording medium, such as a heat-assisted recording medium. A read channel is coupled to the recording head. Phase-locked loop (PLL) circuitry of the read channel is configured to detect a change in a phase error at a location of the data sector. The phase error change may be indicative of a mode-hop that occurred while writing the data sector to the medium. The PLL circuitry is configured to determine a phase offset using the phase error. A controller is configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.