An analog type electronic watch having a step motor to drive hands has a movement indicator other than hands. The movement indicator has a magnet member and is driven with the magnetic influence of a rotor magnet of the step motor. The magnet member is arranged within a window provided in a dial plate of the watch within the range of the magnetic force of the rotor. The movement indicator is supported so as to be synchronously moved with the rotation of the rotor under the magnetic influence.

In an apparatus for recording and quickly retrieving video signal parts on a magnetic tape, during recording information about the local position of each video signal part is automatically stored in a memory associated with the apparatus, which is designed for storing identifying information for a large number of magnetic tape cassettes. The retrieval of each video signal part on each of the cassettes can be effected substantially without delay in the quick rewind mode of operation.

The disclosed device enables the recording of television broadcasts which are preprogrammed in a memory. The presence of data lines of the television signal in combination with the presence of a color television signal is checked. When the data lines stop, the video recorder is switched on in real time by a clock time signal.

A device and method provide for an accurate output from a unit, such as an oscillator and/or clock providing an output indicative of frequency and/or time. The device includes a processing section having a microprocessor that develops a model characterizing the performance of the device, including establishing predicted accuracy variations, and the model is then used to correct the unit output. An external reference is used to provide a reference input for updating the model, including updating of predicted variations of the unit, by comparison of the reference input with the unit output. The ability of the model to accurately predict the performance of the unit improves as additional updates are carried out, and this allows the interval between the updates to be lengthened and/or the overall accuracy of the device to be improved. The accuracy of the output is thus adaptively optimized in the presence of systematic and random variations.

A method is described for detecting the time messages in the faulty signal of a time-signal transmitter comprising the steps below. Probabilities are assigned to the received information/bits as they are received and whose sign specifies the value of the bit and whose numerical value indicates the certainty of reception. Except for the bits designating the minute information, the probabilities of successive time messages are totaled with time correctness in a one-dimensional memory field. From the totaled probabilities, a reduced time message is reconstructed that initially contains no information on the minutes. If the reconstructed time message does not change over two successive time intervals, and if preset minimum values for the number of probabilities are exceeded for all bits, then the reduced time message is recognized as being correct. The minutes are determined separately and added to the time message recognized as being correct.

Accessory for a laptop computer with LCD display which is connected to the laptop serial communications port and optically transmits data to a portable information device, such as a wristwatch designed to receive data as sequential pulses of light. The accessory includes a microcomputer with an RC timebase which is calibrated each time it is used by a special internal program, so that the input baud rate to the accessory matches the communications baud rate of the data received from the laptop. The internal program also permits selection of an output baud rate for the optically transmitted data.

A radio paging selective receiver determines that a received message is unread based on the time difference between the message reception time and the current time being larger that some predetermined value of time, and the paging selective receiver provides an indication of the unread message by displaying the reception time of the unread message in a second fashion which is visibly different from a first fashion normally used to display the current time.

An LCD is integrated with the cover glass of a wrist watch radio paging receiver which indicates the time data with a dial plate and hands, and a message is displayed on the cover glass by controlling this LCD. In this message display, the parts of the characters indicating the message are made transparent and the remaining parts intercept light. In this manner, message display is made possible by the difference in light transmissivity.

A system includes a system time counter associated with a micro controller and a secure clock module having a real time clock and an elapsed time counter. The system synchronizes operation between the secure clock module and the system time counter. The synchronized time entered into the system time counter is utilized in the operation of the system. The real time clock time can be caused to be entered into the elapsed time counter at certain point in the operation of the system. The relationship of the time provide enhanced systems security.

PCT No. PCT/CH96/00292 Sec. 371 Date May 22, 1998 Sec. 102(e) Date May 22, 1998 PCT Filed Aug. 23, 1996 PCT Pub. No. WO97/08592 PCT Pub. Date Mar. 6, 1997A method by which an elastomer is applied to a model (1) with relief marks to be reproduced. The purpose of the elastomer once set is to form a mold membrane (14) and incorporate within its own material the shape of the marks on the model. The mold membrane is then separated from the model and filled with a setting material, and the mold membrane is applied to a support in order to transfer the marks after preliminary pasting.

An apparatus for measuring a time interval between a start signal edge and a stop signal edge provides a stable clock signal as input to a delay line formed by a series of similar logic gates. The output signal of the last gate of the series is phase locked to the clock signal by adjusting a bias signal controlling the switching speed of all gates. The clock signal and the output signal of each gate form a set of phase distributed periodic timing signals applied to a start time measurement unit (TMU) and a similar stop TMU. The start TMU counts edges of one of the timing signals occurring between an edge of an arming signal and the start signal edge and generates output data representing a time delay between the arming signal and the start signal edge. The data represents the start delay as a whole and fractional number of clock signal periods by conveying the counter output and by indicating which of the timing signals had an edge most closely following the start signal edge. The stop TMU similarly produces output data indicating a whole an fractional number of clock cycles occurring between the arming signal and the stop signal edge. The delay represented by the start TMU output data is subtracted from the delay represented by the stop TMU output data to determine the interval between the start and stop signal edges.

An equatorial sundial apparatus with an adjustable base assembly utilizing one or more concave cylindrical focusing mirrors. One of the benefits that is derived from this apparatus is the use of one or more concave cylindrical mirrors to project a focused beam of light onto a calibrated surface from which the time can be read. This sundial has the additional benefit of not suffering from blurring of the time indicator in a shadow or non-focused beam of light typical of other sundials. This sundial's focused light forms a sharply demarcated indicator from which time can be read to the minute. A further benefit of this apparatus is the ability to incorporate multiple concave cylindrical focusing mirrors to reduce the size of the visual field or screen where the time is read and to incorporate various shapes and designs for ornamental purposes without significant compromise of the sundials accuracy for telling time. An additional benefit of this apparatus is the ability to quickly, accurately and easily adjust the apparatus to the proper tilt upon setup according to the latitude where it will be located by means of an adjustable base assembly.

A first circuit having a first coil electrically charges a second circuit having a second coil through electromagnetic coupling of the two coils. When data signals are to be transferred between the first and second circuits, signal transfer is started only after the second circuit has been charged for a predetermined period of time. The position relationship between the coils is also detected, and a charging/transfer selector changes a duty ratio between charge transfer and data transfer in accordance with the detected result. The charge is transferred in an intermittent manner, and the charging rate is adjusted according to the difference between the voltage of a secondary battery observed during a charging phase and the voltage of the secondary battery observed a certain time after interruption of the charging phase, or vice versa.

An object of the present invention is to provide a method for producing a display device by which a substrate is thinned efficiently. Onto one original substrate having an area for a plurality of display devices, the other original substrate is bonded via a sealing resin layer, the pair of bonded original substrates is divided and separated into a plurality of pairs of substrates of a size of each individual display device, and thereafter a substrate thinning process of thinning the substrates is performed in a state where the substrates are held by substrate holding means.

A mechanism for determining whether the sun is visible at a diurnal solar event and for mechanically triggering actions based upon the sun being visible during the diurnal solar event is disclosed. The mechanisms of the invention can perform these operations without intervention or supervision for long periods of time. Certain embodiments have been applied to provide a diurnal solar event trigger based upon sidereal noon for a clock providing accurate timing for 10,000 years without intervention or supervision.

An electronic data system for use with sporting impliments for providing a user with an electronic device integrated into sport gloves to perform various functions unique to that particular sport. The electronic data system for use with sporting impliments includes a glove member designed for substantially enveloping a hand of a user. The glove member has a notch portion in a back side of the glove member. The notch portion is for facilitating insertion and removal of the user's hand from the glove member. The glove member has a tab portion positioned adjacent to a first side of the notch portion. A data assembly has a housing. The housing is operationally coupled to the glove member. The data assembly has a display for presenting a visual representation of information to the user.

A network is described for providing estimates of the current time. The network includes multiple computer systems each configured to provide an estimate of the current time in response to a received request. The computer systems are logically arranged to form a hierarchical structure, wherein the hierarchical structure includes multiple levels ranked with respect to one another. Each of the computer systems is assigned one of multiple levels of trust, and occupies one of the levels of the hierarchical structure dependent upon the assigned level of trust. The level of trust assigned to a given computer system is dependent upon a timekeeping dependability of the given computer system. The assigned level of trust may also be dependent upon a timekeeping security of the given computer system, where the timekeeping security is dependent upon a tamper resistance of the time clock of the given computer system. Methods for delegating a level of trust to a new computer system (i.e., a computer system not part of the network) and for adding a new computer system to the network are also described.

A method and device for synchronizing the time between at least two integrated circuits (201, 202), which receive the same pulse signal. In the integrated circuits (201, 202) a counter (204, 206) is used to count the number of pulses in the received pulse signal to synchronize the common time between said integrated circuits.

A portable self contained light generating device which is powered by a flow of granular material falling under the influence of gravity to impinge upon and cause a paddle wheel to rotate thereby turning a small generator producing electricity to power one or more light emitting diodes for illumination. The device equipped with a multi-position power/illumination control switch and in some embodiments also provided with a battery providing supplemental power.

A system and method for tracking and informing about a physical, emotional, or physiological cycle, such as a menstrual cycle, includes at least one definition entry and at least one date indicator. Each definition entry defines indicia such as color to represent a stage of a physical, emotional, or physiological cycle. Each date indicator includes a date section and a tracking section corresponding to each date section. The date section of the date indicator indicates at least one date, wherein the tracking section is capable of being marked so as to indicate indicia corresponding to a definition entry to signify the stage of the physical, emotional, or physiological cycle for each date. According to one embodiment, the date indicators are arranged according to phases of the moon to allow correlation of a user's cycle to the lunar cycle.

A musical rhythm is expressed by the number of the timing marks (for example, three timing marks when in simple triple time); and a musical tempo is expressed by the distance among the timing marks and a timing ball that moves at a fixed speed among those timing marks. Accordingly, a player may easily grasp the tempo of the music and easily determine the rhythm of the music in a sound game.

A method for detecting and conveying an alarm signal, when an absorbent article is unfastened or, completely removed from the body of the wearer. The method is intended to be used in parallel with a method for detecting wetness in the absorbent article and further relates to an integrated detection-and-alarm method for detecting unfastening and/or wetness in an absorbent article. A system for detecting and conveying an alarm signal when an absorbent article is unfastened or removed from the body of the wearer and/or when the article is wet. The system includes (a) and absorbent article having at least one absorbent layer, the object to be displaced, such as a fastening system, one or more sensoring devices, one or more transmitting devices, and (b) a remote receiver. Furthermore, the system relates to the use of the system in the care of children and adults suffering from incontinence and/or psychological illnesses.

The coupled resonator comprises a first low frequency resonator, such as a balance spring (1) and a second higher frequency resonator, such as a tuning fork (2), the two resonators (1 and 2) including permanent mechanical coupling means. Application to the regulating system of a timepiece.

Smoking cessation lighter is configured for lighting cigarettes for a smoker, and learning software is provided for monitoring smoking behavior of a smoker during a first data collection period and guiding a smoker's smoking cessation by directing the smoker when the smoker is to smoke a cigarette based on data collected during the first data collection period. The learning software monitors user behavior and collects data during use of the lighter by the smoker after the initial data collection period in order to analyze and further guide the smoker based on the smoker's cheating behavior, the smoker's behavior of lighting a cigarette for a friend, and the smoker's behavior of skipping use of the lighter at a time when the smoker has been directed to light a cigarette by the lighter.

A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.

A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.

Various systems and methods are described for configuring a data storage system. In one embodiment, a plurality of actual capacities of a plurality of storage devices of the data storage system are identified and divided into a plurality of capacity slices. The plurality of capacity slices are combined into a plurality of chunks of capacity slices, each having a combination of characteristics of the underlying physical storage devices. The chunks of capacity slices are then mapped to a plurality of logical storage devices. A group of the plurality of logical storage devices is then organized into a redundant array of logical storage devices.

A sequence of storage devices of a data store may include one or more stripesets for storing data stripes of different lengths and of different types. Each data stripe may be stored in a prefix or other portion of a stripeset. Each data stripe may be identified by an array of addresses that identify each page of the data stripe on each included storage device. When a first storage device of a stripeset becomes full, the stripeset may be shifted by removing the full storage device from the stripeset, and adding a next storage device of the data store to the stripeset. A class variable may be associated with storage devices of a stripeset to identify the type of data that the stripeset can store. The class variable may be increased (or otherwise modified) when a computer stores data of a different class in the stripeset.

Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage module operable within a communication network to present the plurality of physical storage devices as a virtual storage device to a plurality of network computing elements that are coupled to the communication network. The virtual storage device comprises a plurality of virtual storage volumes, wherein each virtual storage volume is communicatively coupled to the physical storage devices via the storage module. The storage module comprises maps that are used to route read/write requests from the network computing elements to the virtual storage volumes. Each map links read/write requests from at least one network computing element to a respective virtual storage volume within the virtual storage device.

A computing system includes a plurality of dispersed storage (DS) processing units operable to receive a continuous data stream, simultaneously disperse storage error encode the continuous data stream to produce a plurality of encoded data slices and store the plurality of encoded data slices in a DS memory.

A memory storage apparatus, a memory controller and method for transmitting and identifying data streams are provided. The memory controller passes at least a portion of a data stream received from a host system to a smart card chip of the memory storage apparatus. Then, the host system accurately receives a response message from the smart card chip by executing a plurality of read commands. The memory controller is capable of adding a first verification code to a response data stream sent to the host system, and is capable of adding a write token to each of data segments of the response data stream. The host system confirms the accuracy of the response data stream by verifying the first verification code or by verifying the write token of each of the data segments.

For a plurality of input/output (I/O) operations waiting to assemble complete data tracks from data segments, a process, separate from a process responsible for the data assembly into the complete data tracks, is initiated for waking a predetermined number of the waiting I/O operations.

A flash memory file system including a plurality of flash modules. Each of the plurality of flash modules includes a respective cache memory, a respective flash memory, and a respective flash controller in communication with the respective cache memory and the respective flash memory. A first flash module of the plurality of flash modules is configured to receive a file lookup message including a path name for file data stored on a second flash module of the plurality of flash modules. A third flash module of the plurality of flash modules is configured to select the second flash module based on the path name and a directory table, and generate a file metadata message responsive to the file lookup message. The file metadata message identifies the second flash module as containing the file data.

Provided is a method and system for reducing duplicate buffers in buffer cache associated with a storage device. Reducing buffer duplication in a buffer cache includes accessing a file reference pointer associated with a file in a deduplicated filesystem when attempting to load a requested data block from the file into the buffer cache. To determine if the requested data block is already in the buffer cache, aspects of the invention compare a fingerprint that identifies the requested data block against one or more fingerprints identifying a corresponding one or more sharable data blocks in the buffer cache. A match between the fingerprint of the requested data block and the fingerprint from a sharable data block in the buffer cache indicates that the requested data block is already loaded in buffer cache. The sharable data block in buffer cache is used instead thereby reducing buffer duplication in the buffer cache.

A method, a system and a computer program product for enhancing a cache back invalidation policy by utilizing least recently used (LRU) bits and presence bits in selecting cache-lines for eviction. A cache back invalidation (CBI) utility evicts cache-lines by using presence bits to avoid replacing a cache-line in a lower level cache that is also present in a higher level cache. Furthermore, the CBI utility selects the cache-line for eviction from an LRU group. The CBI utility ensures that dormant cache-lines in the higher level caches do not retain corresponding presence bits set in the lower level caches by unsetting the presence bits in the lower level cache when a line is replaced in the higher level cache. Additionally, when a processor core becomes idle, the CBI utility invalidates the corresponding higher level cache by unsetting the corresponding presence bits in the lower level cache.

Techniques for handling version information using a copy engine. In one embodiment, an apparatus comprises a copy engine configured to perform one or more operations associated with a block memory operation in response to a command. Examples of block memory operations may include copy, clear, move, and/or compress operations. In one embodiment, the copy engine is configured to handle version information associated with the block memory operation based on the command. The one or more operations may include operating on data in a cache and/or modifying entries in a memory. In one embodiment, the copy engine is configured to compare version information in the command with stored version information. The copy engine may overwrite or preserve version information based on the command. The copy engine may be a coprocessing element. The copy engine may be configured to maintain coherency with other copy engines and/or processing elements.

In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity to help determine whether a reallocation of resources between nodes may improve memory affinity for a logical partition or for the computer system. If so, the reallocation of resources is performed so memory affinity for the logical partition or computer system is improved. Memory affinity is computed relative to the physical layout of the resources according to a hardware domain hierarchy that includes a plurality of primary domains and a plurality of secondary domains.

A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range.

An optical backup apparatus is provided and includes an optical storage device, an interface module to connect with at least one type of external storage medium, and a control unit to back up data from the external storage medium to the optical storage device in response to an external remote control operation.

Machine implemented method and system for generating a disaster recovery copy of an expandable storage volume having a namespace for storing information for accessing data objects stored at a data constituent volume is provided. A transfer operation for transferring a point in time copy of the expandable storage volume from a first location to a second location is generated. Information regarding the expandable storage volume from the first location is retrieved and a destination expandable storage volume is resized to match components of the expandable storage volume at the first location. Thereafter, the point in time copy of the expandable storage volume is transferred from the first location to the second location and configuration information regarding the point in time copy is copied from the first location to the second location.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

A mechanism is provided in a storage device for performing a write operation. The mechanism configures a write buffer memory with a plurality of write buffer portions. Each write buffer portion is dedicated to a predetermined block size category within a plurality of block size categories. For each write operation from an initiator, the mechanism determines a block size category of the write operation. The mechanism performs each write operation by writing to a write buffer portion within the plurality of write buffer portions corresponding to the block size category of the write operation.

Various systems and methods are described for configuring a logical data storage container. In one embodiment, an instruction to perform an operation to modify an attribute of the logical data storage container that is an abstraction of a plurality of pertinent storage containers is received. A translated instruction to perform a sub-operation associated with the operation is transmitted to each of a number of the plurality of pertinent storage containers. A level of success of the performing of the operation on the logical data storage container is detected based on a comparison of a threshold value to a level of success of the performing of the sub-operation on each of the number of the plurality of pertinent storage containers. A report of the detected level of success is communicated.

A partition manager relocates a logical partition from a primary shared processor pool to a secondary shared processor pool in response to a predetermined condition, such as a hardware failure. The relocated logical partition is allocated a smaller quantity of processing units from the secondary pool than it was allocated from the primary pool. A quantity of processing units reserved for a second logical partition is identified in the secondary shared processor pool, and a portion of those reserved processing units are allocated to the relocated logical partition. The reserved processing units may be redistributed among multiple relocated logical partitions.

The invention pertains to a memory management unit for a microprocessor system, the memory management unit being connected or connectable to at least one processor core of the microprocessor system and being connected or connectable to a physical memory of the microprocessor system. The memory management unit is adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware The memory management unit comprises a first register table indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other; a second register table indicating an allowed address range of physical addresses accessible to a process running in or under supervisor mode; wherein the memory management unit is adapted to prevent write access to the second register table by a process not in hypervisor mode. The memory management unit is further adapted to allow write access to the first register table of a process running in or under supervisor mode to reconfigure the physical address information indicated in the first register table with memory mapping information relating to at least one physical address, if the at least one physical address is in the allowed address range, and to prevent write access to the first register table of the process running in or under supervisor mode if the at least one physical address is not in the allowed address range. The invention also pertains to a microprocessor system and a method for managing memory.

Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.

A prefetch optimizer tool for an information handling system (IHS) may improve effective memory access time by controlling both hardware prefetch operations and software prefetch operations. The prefetch optimizer tool selectively disables prefetch instructions in an instruction sequence of interest within an application. The tool measures execution times of the instruction sequence of interest when different prefetch instructions are disabled. The tool may hold hardware prefetch depth constant while cycling through disabling different prefetch instructions and taking corresponding execution time measurements. Alternatively, for each disabled prefetch instruction in the instruction sequence of interest, the tool may cycle through different hardware prefetch depths and take corresponding execution time measurements at each hardware prefetch depth. The tool selects a combination of hardware prefetch depth and prefetch instruction disablement that may improve the execution time in comparison with a baseline execution time.

Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.

In a satellite communication system comprising at least a hub and a plurality of terminals, at least one terminal may include a cache for storing data objects. The cache may be based on a detachable memory device that may be inserted to or removed from the terminal at any given time, including after the terminal is deployed. Aspects are directed to preventing a prefetching of objects already stored in a cache of a remote terminal. In some embodiments, an efficient multicasting of content to terminals over an adaptive link may occur in a manner which may benefit terminals comprising a cache while not affecting or minimally affecting the performance of terminals that may not include a cache.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.