A method for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.

An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.

Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

A multiprocessor system includes a first microprocessor and a second microprocessor. A first signaling pathway is configured to send message transmission coordination signals from the first microprocessor to the second microprocessor. The first signaling pathway may be coupled to at least two flag registers associated with the second microprocessor. A second signaling pathway is configured to send message transmission coordination signals from the second microprocessor to the first microprocessor. The second signaling pathway may be coupled to at least two flag registers associated with the first microprocessor. The first signaling pathway is independent of the second signaling pathway.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

In accordance with embodiments, there are provided mechanisms and methods for controlling a process using a process map. These mechanisms and methods for controlling a process using a process map can enable process operations to execute in order without necessarily having knowledge of one another. The ability to provide the process map can avoid a requirement that the operations themselves be programmed to follow a particular sequence, as can further improve the ease by which the sequence of operations may be changed.

A system and method is disclosed for communicating with sensors/loggers in integrated radio frequency identification (RFID) tags. An RFID reader uses a Communicate With Data Logger Command to communicate with a data logger in an RFID tag. The RFID reader performs data access processes using an Index Register and a Data Register of the RFID tag. The RFID reader selects one of (1) Index Read access (2) Index Write access (3) Data Write access (4) Data Read access with parity and (5) Data Read access with cyclic redundancy check (CRC). The RFID tag performs the requested data access and then performs an error detection process.

A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.

A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction.

A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction that corresponds to the instruction bits. In turn, the processor executes the forced event.

In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state.

A method is disclosed which may include analyzing communication requests in a business process between a client and a server offering a service application to be tested. The method may further include identifying a call to a web service in the analyzed communication. The method may also include determining a location of a Web Service Description Language (WSDL) file relating to the web service on a remote server and downloading the WSDL file from the determined location. A computer readable medium having stored thereon instructions for performing the method and a computer system are also disclosed.

A framework for implementing multitenant architecture is provided. The framework comprises a framework services module which is configured to provide framework services that facilitate abstraction of Software-as-a-Service (SaaS) services and crosscutting services for a Greenfield application and a non SaaS based web application. Further the abstraction results in a SaaS based multitenant web application. The framework further comprises a runtime module configured to automatically integrate and consume the framework services and APIs to facilitate monitoring and controlling of features associated with the SaaS based multitenant web application. The framework further comprises a metadata services module configured to provide a plurality of metadata services to facilitate abstraction of storage structure of metadata associated with the framework and act as APIs for managing the metadata. The framework further comprises a role based administration module that facilitates management of the metadata through a tenant administrator and a product administrator.

Systems and methods for static code scheduling are disclosed. A method can include receiving an intermediate representation of source code, building a directed acyclic graph (DAG) for the intermediate representation, and creating chains of dependent instructions from the DAG for cluster formation. The chains are merged into clusters and each node in the DAG is marked with an identifier of a cluster it is part of to generate a marked instruction DAG. Instruction DAG scheduling is then performed using information about the clusters to generate an ordered intermediate representation of the source code.

Systems, Apparatus, methods, and computer program products are provided for converting an existing artifact to one or more new artifacts. For example, in one embodiment, a computing device can receive input identifying an existing artifact for conversion to one or more new artifacts. One or more items from the existing artifact and their respective types can be identified for conversion. Then, the one or more items of the existing artifact can be converted to one or more new artifacts.

A computer-implemented method is provided for evaluating team performance in a product development environment. The method includes receiving a plurality of points of effort made by a team over a plurality of days in a time period, computing a slope associated with a line of best fit through the plurality of points of effort over the plurality of days, computing a deviation of the slope from an ideal slope corresponding to a desired performance rate for the team, and generating a display illustrating at least one of the slope, the ideal slope or the deviation.

A method of applying formal verification methodologies to event processing applications is provided herein. The method includes the following stages: representing an event processing application as an event processing network, being a graph with event processing agents as nodes; generating a finite state machine based on the event processing network, wherein the finite state machine is an over-approximation of the event processing application; expressing stateful rules and policies that are associated with the event processing application using temporal logic, to yield a temporal representation of the event processing application; combining the temporal representation and the finite state machine into a model; generating a statement associated with a user-selected verification-related property of the event processing application, wherein the statement is generated using the temporal representation; and applying the statement to the model, to yield an indication for: (i) a correctness of the statement or (ii) a counter example, respectively.

Graphical programming or modeling environments in which a coding standard can be applied to graphical programs or models are disclosed. The present invention provides mechanisms for applying the coding standard to graphical programs/models in the graphical programming/modeling environments. The mechanisms may detect violations of the coding standard in the graphical model and report such violations to the users. The mechanisms may automatically correct the graphical model to remove the violations from the graphical model. The mechanisms may also automatically avoid the violations in the simulation and/or code generation of the graphical model.

Methods, devices, and systems for management of a cloud computing environment for use by a software application. The cloud computing environment may be an N-tier environment. Multiple cloud providers may be used to provide the cloud computing environment.

Disclosed is a novel system and method to select software components. A set of available software components are accessed. Next, one or more dimensions are defined. Each dimension is an attribute to the set of available software components. A set of coherence distances between each pair of the available software components in the set of available software components is calculated for each of the dimensions that have been defined. Each of the coherence distances are combined between each pair of the available software components that has been calculated in the set of the coherence distances into an overall coherence degree for each of the available software components. Using the overall coherence degree, one or more software components are selected to be included in a software bundle.

A method for recommending at least one artifact to an artifact user is described. The method includes obtaining user characteristic information reflecting preferences, particular to the artifact user, as to a desired artifact. The method also includes obtaining first metadata about each of one or more candidate artifacts, and scoring, as one or more scored artifacts, each of the one or more candidate artifacts by evaluating one or more criteria, not particular to the artifact user, applied to the first metadata. The method further includes scaling, as one or more scaled artifacts, a score of each of the one or more scored artifacts, by evaluating the suitability of each of the one or more scored artifacts in view of the user characteristic information. The method lastly includes recommending to the artifact user at least one artifact from among the one or more scaled artifacts based on its scaled score.

The present invention provides a method, a system and a computer program product for defining a version identifier of a service component. The method includes determining various specification levels corresponding to the service component. Thereafter, the determined specification levels are integrated according to a predefined hierarchy to obtain the version identifier of the service component. The present invention also enables the identification of the service components. The service components are identified from one or more service components on the basis of one or more user requirements.

An aspect of the present invention identifies differences between source codes (e.g. of different versions of a software), when each source code is organized using incorporated files. In one embodiment, in response to receiving identifiers of a first and second source codes (each source code being organized as a corresponding set of code files), listings of the instructions in the first and second source codes are constructed. Each listing is constructed, for example, by replacing each incorporate statement in the source code with instructions stored in a corresponding one of code files. The differences between the first and second source codes are then found by comparing the constructed listings of instructions.

An information processing system, computer readable storage medium, and method for automatically generating human readable and meaningful documentation for one or more source code files. A processor of the information processing system receives one or more source code files containing source code artifacts (SCA) and infers semantics therefrom based on predefined rules. The processor, based on the inferred semantics, extracts documentation from another source code file. The extracted documentation and the inferred semantics are used to generate new human readable and meaningful documentation for the SCA, such new documentation being previously missing from the SCA. The generated new documentation is included with the SCA in one or more source code files.

A system and method may generate unit tests for source code concurrently with API documentation. The system may receive a source code file including several comments sections. Each comments section may include a description of a source code unit such as a class, method, member variable, etc. The description may also correspond to input and output parameters the source code unit. The system and method may parsing the source code file to determine a source code function type corresponding to the unit description and copy the unit description to a unit test stub corresponding to the function type. A developer or another module may then complete the unit test stub to transform each stub into a complete unit test corresponding to the source code unit. Additionally, the system and method may execute the unit test and generate a test result indication for each unit test.

Disclosed is a novel computer implemented system, on demand service, computer program product and a method that leverages combined concrete and symbolic execution and several fault-localization techniques to automatically detects failures and localizes faults in PHP Hypertext Preprocessor (“PHP”) Web applications.

An information editing device is provided with an object storage portion 11 in which a character string object or image object is stored, a placement information storage portion 12 that stores placement area designation information that sets two or more placement areas that do not overlap each other for respectively placing the objects, and that correspond to the objects, an object output portion 13 that outputs, into placement areas that are set based on the placement area designation information, each of the objects corresponding to the respective placement areas, an input receiving portion 14 that receives a deletion instruction or a modification instruction for at least one of the objects output by the object output portion 13, and a placement modification portion 15 that, according to the deletion instruction or modification instruction, modifies the placement area of the object such that the placement area is placed without overlapping.

A single software project in an integrated development environment (IDE) may be built for multiple target environments in a single build episode. Multiple different output artifacts may be generated by the build process for each of the target environments. The output artifacts are then deployed to the target environments, which may be homogeneous or heterogeneous environments. The same source project may be used to generate multiple output artifacts for the same target environment.

A method is provided for providing consistent logical code across specific programming languages. The method incorporates preprocessor macros in a source computer program code to generate a program control flow. The preprocessor macros can be used to describe program control flow in the source programming language for execution in the source computer program code. The preprocessor macros can also be used to generate control flow objects representing the control flow, which converts the source computer program code into a general language representation. The general language representation when executed is used to output computer programming code in specific programming languages representing the same logical code as that of the source computer program code.

In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

In one embodiment of the invention, a method is disclosed for modifying a pre-existing application program for multi-processing and/or distributed parallel processing. The method includes searching an application program for a computational loop; analyzing the computational loop to determine independence of the computational transactions of the computational loop; and replacing the computational loop with master code and slave code to provide master-slave execution of the computational loop in response to analyzing the computational loop to determine independence of the computational transactions of the computational loop. Multiple instances of the modified application program are executed to provide multi-processing and/or distributed parallel processing.

This invention relates to a method, computer readable medium, and apparatus for identifying one or more problematic loops in an application. This invention provides a Directed Acyclic Graph or DAG representation of structure of one or more loops in the application by performing a static and a dynamic analysis of the application source code and depicts the loop information as LoopID, loop weight, total loop iteration, average loop iteration, total loop iteration time, average loop iteration time and embedded vector size. This aids a programmer to concentrate on problematic loops in the application and analyze them further for potential parallelism.

Transferring files to a baseboard management controller (‘BMC’) in a computing system, including: receiving, by the BMC, a request to initiate an update of the computing system; identifying, by the BMC, an area in memory within the computing system for storing an update file; and transmitting, by the BMC, a request to register the BMC as a virtual memory device.

Transferring files to a baseboard management controller (‘BMC’) in a computing system, including: receiving, by the BMC, a request to initiate an update of the computing system; identifying, by the BMC, an area in memory within the computing system for storing an update file; and transmitting, by the BMC, a request to register the BMC as a virtual memory device.

Embodiments of the present disclosure provide a method and a system for upgrading software. The method includes: a client reports a software upgrade request to a server, wherein the upgrade request carries file information of the local software to be upgraded; the server determines the difference with the latest version software according to the file information of the software to be upgraded in the upgrade request, and generates upgrade instruction information according to the difference and sends it to the client; the client downloads and updates the relevant files and performs the relevant local upgrade operations according to the instructions in received upgrade instruction information. Technical solutions of the present disclosure can save bandwidth resources and reduce the workload for upgrading software.

A binary library overload instruction is received at an embedded computing device that executes a write-protected firmware build. The binary library overload instruction specifies a write-protected binary library of the write-protected firmware build to be overloaded by execution of an alternative binary library instead of the write-protected binary library of the write-protected firmware build. The alternative binary library is configured within a random access memory (RAM) storage area to execute instead of the write-protected binary library as specified in the received binary library overload instruction. The write-protected firmware build is executed using the alternative binary library instead of the write-protected binary library specified in the binary library overload instruction.

A software streaming platform may be implemented that predictively chooses units of a program to download based on the value of downloading the unit. In one example, a program is divided into blocks. The sequence in which blocks of the program historically have been requested is analyzed in order to determine, for a given history, what block is the next most likely to be requested. Blocks then may be combined into chunks, where each chunk represents a chain of blocks that have a high likelihood of occurring in a sequence. A table is then constructed indicating, for a given chunk, the chunks that are most likely to follow the given chunk. Based on the likelihood table and various other considerations, the value of downloading particular chunks is determined, and the chunk with the highest expected value is downloaded.

Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each domain is monitored. If a utilization of any of these domains changes, then the number of threads for each of the domains determined for execution may also be adjusted to adapt to the change.

Methods and systems to identify and reproduce concurrency bugs in multi-threaded programs are disclosed. An example method disclosed herein includes defining a data type. The data type includes a first predicate associated with a first thread of a multi-threaded program that is associated with a first condition, a second predicate that is associated with a second thread of the multi-threaded program, the second predicate being associated with a second condition, and an expression that defines a relationship between the first predicate and the second predicate. The relationship, when satisfied, causes the concurrency bug to be detected. A concurrency bug detector conforming to the data type is used to detect the concurrency bug in the multi-threaded program.

An improved method for program building uses predefined source files and predefined build scripts comprising a sequence of build commands; wherein each build command comprises an origin command line interpretable by an operating system and addressed to at least one compiling tool.

The present invention relates to the field of perfumery and more particularly to the field of malodor counteractancy. In particular, it relates to a method for application of malodor counteracting (MOC) compositions capable of neutralizing in an efficient manner, through chemical reactions, malodors of a large variety of origins and which can be encountered in the air, on textiles, bathroom or kitchen surfaces, and the like. The composition may be applied as is or in the form of a perfuming composition or in a consumer product or article containing the compound or perfume composition.

The invention relates to a method of use of certain derivatives of formula (I) in the form of any one of its stereoisomers or a mixture thereof, and wherein R1 represents a hydrogen atom, a C1-4 alkyl or alkenyl group, or a (CHR)2OH group, each R being a hydrogen atom or a methyl group; R2 represents a hydrogen atom or a methyl, ethyl or n-propyl group; and R3 represents a hydrogen atom or a methyl group, as perfuming ingredients. The present invention concerns also certain compounds and compositions or articles containing such compounds.

The present invention concerns a compound of formula wherein R represents a hydrogen atom or a C1-2 alkyl or alkoxyl group; each R1, R2 or R3 represents a hydrogen atom or a methyl or ethyl group; and X represents a CHO, COOR4 or CN group, R4 being a methyl or ethyl group; and at least one of said R, R1 or R2 represents a group containing at least one carbon atom; and it use as perfuming ingredient, for instance to impart odor notes of the floral and/or anis type.

A perfuming composition capable of prolonging the release of a perfuming component into the surrounding environment when applied on a body surface. The composition includes isocetyl alcohol as a fragrance evaporation modulator in the presence of high amounts of ethanol. Also, consumer articles containing such compositions and methods for the perfuming of a body surface and for increasing the long-lastingness of a perfuming component using these compositions.

An individual alkamide and/or a mixture having two or more different alkamides, is disclosed for changing, masking or reducing the unpleasant flavor impression of an unpleasant-tasting substance or mixture of substances. The alkamide can be trans-pellitorine; cis-pellitorine; 2Z,4Z- or 2Z,4E-decadienoic acid-N-isobutylamide; 2E,4E-decadienoic acid-N-([2S]-2-methylbutyl)amide; 2E,4E-decadienoic acid-N-([2R]-2-methylbutylamide); 2E,4Z-decadienoic acid-N-(2-methylbutyl)amide; achilleamide; sarmentine; 2E- or 3E-decenoic acid-N-isobutylamide; 3E-nonenoic acid-N-isobutylamide; spilanthol; homospilanthol; 2E,6Z,8E-decatrienoic acid-N-([2R]-2-methylbutyl)amide; 2E- or 2Z-decen-4-oic acid-N-isobutylamide; α-sanshool; α-hydroxysanshool; γ-hydroxysanshool; γ-hydroxysanshool; γ-hydroxyisosanshool; γ-dehydrosanshool; γ-sanshool; bungeanool; isobungeanool; dihydrobungeanool; or tetrahydrobungeanool, or combinations thereof.