A most recent electrostatic capacitance value for a backup capacitor is measured periodically. Each time the most recent electrostatic capacitance value is measured, a charging voltage (a required charging voltage) that is required in order to cause a return operation of a valve from the setting opening at that time to an emergency opening/closing position (for example, the fully closed position) is calculated based on the electrostatic capacitance value that has been measured, and the terminal voltage of the backup capacitor is adjusted so as to become equal to the calculated required charging voltage.

A flush adaptor for use with a valve fitment assembly for dispensing liquids from a container; wherein the flush adaptor comprises an outer ring-collar; a flange with an edge molded to the bottom of the outer ring-collar; an interior ring-collar adjacent to the outer ring-collar; a ridge molded in the interior ring-collar; a seat molded onto the interior ring-collar and a pin molded into the interior ring-collar which keeps the valve in an open position; and a hollow tube molded into the adaptor to allow the flow of liquid through the adaptor and into the fitment assembly; whereby the flush adaptor allows for cleaning of the assembly and any tubes connected thereto.

A method of isolating a section of pipe includes the steps of locating a seal unit having two seal elements in a pipe via a penetration in the pipe, such as a branch or tee. The seal unit is then positioned in the pipe downstream of the penetration. The seal elements are activated using a primary activation mechanism to engage the pipe wall and then maintained in an activated condition using a secondary activation mechanism.

Power-efficient actuator apparatus and methods. In one exemplary embodiment, the actuator assembly utilizes a shape memory alloy (SMA) filament driven by an electronic power source to induce movement in the underlying assembly to actuate a load (e.g., water valve). In addition, a circuit board is included which allows the actuator assembly to be readily incorporated or retrofit into a wide range of systems such that the signal characteristics of the supply line can, among other applications, be conditioned in order to protect the SMA filament. Furthermore, the circuit board can also readily be adapted for use with “green” power sources such as photovoltaic systems and the like. Methods for manufacturing and utilizing the aforementioned actuator assembly are also disclosed.

A direct acting solenoid actuator includes an armature and associated push pin that are suspended from certain fixed solenoid components, such as a pole piece and/or flux sleeve, by a fully floating cage of rolling elements. The fixed solenoid component may comprise a pole piece and/or a flux sleeve. The pole piece may include stops to limit movement of the cage of rolling elements in the axial direction.

A butterfly valve including a valve body having a passage, a valve shaft assembly, a valve plate, and a tube that is friction fit inside the passage is provided. The valve shaft assembly includes a first shaft portion and a second shaft portion. The first and second shaft portions are in opposing spaced relation with the valve plate disposed therebetween. The valve plate has a flange such that when the butterfly valve is in the closed position a seal is formed with the tube, which is disposed within the fluid flow passage. The valve plate has lip extending from a portion of the valve plate that is radially outward from the circumference of the tube. The lip acts to reduce flow induced torque experienced while the valve plate is actuated from the closed to the open position.

An actuator includes a first piston and a second piston. The first piston has a piston ring that separates a first chamber from a second chamber of the actuator. The first piston has an interior chamber that communicates with the first chamber. The second piston is disposed within the interior chamber of the first piston so as to be movable with respect thereto. The second piston has a surface that interfaces with the second chamber.

In a control device for a technical processing plant, a pneumatically driven actuator having an actuator stem is provided together with a valve operated by the actuator, the valve having a valve stem. A valve element is attached to the valve stem. A stem connector connects the two stems to each other for a forced transmission of axial actuating movements and for modifying an axial distance between adjacent ends of the valve stem and the actuator stem to adjust a total axial length of the two stems. The stem connector comprises two half-shells connected to each other, and two positioning devices are provided for a friction-locking coupling of the half-shells to the respective ends. At least one of the positioning devices is designed to modify an axial attachment position of the half-shells along one of the stems.

The invention relates to a valve actuator (2), comprising a magnetic core (6) with an interspace (8) and at least one bifurcating branch (7), at least one variable magnetic field generating device (16), at least one permanent magnetic field generating device (13) and at least one movable magnetic component (12), wherein the bifurcating branch (7) defines a first region (4) and a second region (5) of said magnetic core (6). Said movable magnetic component (12) is movably arranged within said interspace (8) of said magnetic core (6) in such a way that a first gap (19) is formed between a first surface (23) of said movable magnetic component (12) and a first surface (22) of said interspace (8) of said magnetic core (6), a second gap (20) is formed between a second surface (24) of said movable magnetic component (12) and a second surface (25) of said interspace (8) of said magnetic core (6), and a third gap (21) is formed between a third surface (27) of said movable magnetic component (12) and a third surface (26) of said bifurcating branch (7) of said magnetic core (6). At least one of said variable magnetic field generating devices (48, 49) is associated with said first region (4) of said magnetic core (6) and at least one of said permanent magnetic field generating devices (13) is associated with said second region (5) of said magnetic core (6). Said valve actuator (2) is designed and arranged in a way that a magnetic flux, generated by at least one at least one of said variable magnetic field generating devices (16) is able to exert a force on said at least one movable magnetic component (12) and is able to cancel the magnetic flux (48, 49), generated by at least one of said permanent magnetic field generating devices (13). At least one magnetic flux limiting means (7, 12) is provided, whose magnetic flux limit can be reached or exceeded.

A solenoid valve, the magnet armature of which is designed to be movable relative to a first valve-closing element, for which purpose the first valve-closing element is accommodated telescopically in a coupling element attached to the magnet armature, wherein the coupling element is guided along the inner wall of a guide sleeve inserted in the valve housing in order to align the magnet armature precisely with the first valve-closing element in the direction of a second valve-closing element which is likewise accommodated in the guide sleeve.

A method and device for the production of books, including: moving book blocks successively along a conveying section of a book production line; supplying a stack of book cases to the book production line; identifying a marking on each of the book blocks and the book cases; transmitting an identified marking on at least one book case to a machine control of the book production line; assigning a dataset stored in the machine control for a sequence of book cases to the supplied stack; determining a sequence in the machine control for book blocks positioned on the conveying section; comparing the dataset for the sequence of the book cases to the sequence of the book blocks; and removing and/or supplying at least one book block from or to the conveying section if the sequence of the book blocks deviates from the sequence of the book cases using the machine control.

An apparatus and method are provided, for alternatively producing either small or bulk packs of napkins from a stack of folded napkins produced by one folding machine, through use of a pack dispatching arrangement having an inlet, a small pack transfer station and a bulk pack transfer station, and configured for operation in a small pack mode for dispatching a stream of spaced apart small packs of folded sheets separated from the stack of folded sheets, and received at an inlet of the pack dispatching arrangement, to the small pack transfer station, and alternatively operable in a bulk pack mode for dispatching a stream of spaced apart bulk packs of folded sheets separated from the stack of folded sheets, and received at an inlet of the pack dispatching arrangement, to the bulk pack transfer station.

This invention provides a technique of preventing a collision between an original document and a printing material on a conveyance path when an image forming apparatus executes both additional printing on the original document and printing on the printing material. In a case where both additional printing on an original document and printing on a printing material are executed, the image forming apparatus according to one aspect of the invention conveys a read original document to a transfer unit through a conveyance path commonly used for an original document and sheet, and prints an image to be added on the original document. After the original document is conveyed to the transfer unit through the conveyance path, the image forming apparatus feeds a sheet from a sheet feeding unit to the conveyance path, and performs copying on the sheet in the transfer unit.

A printing control apparatus according to one aspect of this invention controls to print images on sheets based on image data of a plurality of pages, generate a bookbinding product by executing folding processing for the image-printed sheets, and output the bookbinding product. The printing control apparatus further accepts the position of an insertion sheet to be inserted into the sheets for which the folding processing is executed, and controls to output a plurality of bookbinding products by using, as a reference, the accepted position of the insertion sheet.

The present invention is directed to providing a mechanism for allowing a user to easily take out print products discharged onto a plurality of sheet discharge trays in the discharge order. A control method for controlling a sheet processing apparatus for performing control to discharge sheets onto a plurality of sheet discharge trays includes storing, in a storage unit, the discharge order in which sheets have been discharged onto equal to or more than two sheet discharge trays by executing a job, and performing, upon reception of a take-out instruction for taking out in the discharge order the sheets discharged by executing the job, processing for allowing a user to take out the sheets discharged onto the equal to or more than two sheet discharge trays, in the discharge order stored in the storage unit.

An image recording apparatus includes: a recording unit for recording an image on a recording medium; a tray for supporting the recording medium recorded by the recording unit; a conveyor mechanism for conveying the recorded medium to the tray; and an alignment mechanism for aligning a plurality of recording media stacked on the tray, by application of an external force. In a period from a start to an end of recording based on one recording job, the alignment mechanism aligns the plurality of recording media stacked on the tray in a period in which image recording is not performed, and the alignment mechanism does not align the plurality of recording media stacked on the tray in a period in which image recording is being performed.

In a provided apparatus, an upper roller to be engaged with a sheet upper face and a lower roller to be engaged with a sheet lower face are arranged at a sheet discharging port in a manner capable of being pressure-contacted and being separated, the upper roller is formed with a large-diameter soft roll face and a small-diameter hard roll face, and a pressurization force of roller lifting-lowering means with which the upper roller is pressure-contacted to and is separated from the lower roller is switched to be high or low.

In a sheet storing apparatus of the present invention, a tailing end supporting member which temporarily supports a tailing end of a dropping sheet bundle is arranged between a discharging port of a processing tray to discharge the sheet bundle and the upmost sheet on a stack tray as being movable between an operating position above a sheet placement face and a waiting position outside the stack tray.

A sheet processing apparatus and a method of controlling the same align sheets stacked on a stacking unit, by causing a first alignment member and a second alignment member to come into contact with edges of a sheet stacked on the stacking unit in a sheet width direction. In a case that a second sheet that is different from a first sheet stacked on the stacking unit is to be stacked on the first sheet and aligned using the first alignment member and the second alignment member, control is performed to discharge a partition sheet onto the first sheet stacked on the stacking unit.

To provide a sheet storage apparatus for enabling sheets that are carried out of an image formation apparatus or the like on the upstream side to be loaded and stored in a predetermined position with a correct posture neatly at high speed, a sheet discharge roller and a reverse roller spaced a distance are disposed in a sheet discharge outlet and a tray, a kick member is provided to be swingable in a vertical direction passing a sheet discharge path of a sheet discharged from the sheet discharge outlet, and a posture of the kick member is controlled by shift means. The shift means controls the kick member among a waiting posture retracted upward from the sheet discharge path, an engagement posture for imposing a load on the sheet to engage, and an actuation posture dropping onto the tray together with the sheet.

The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.

Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

The stack package includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first substrate having a first modulus and at least one semiconductor chip mounted on the first substrate. The second semiconductor package stacked on the first semiconductor package and includes a second substrate having a second modulus and at least one semiconductor chip mounted on the second substrate. The second modulus is less than the first modulus. Even in the event that the first semiconductor package is under severe warpage due to a temperature change, the flexible second substrate, which includes e.g., polyimide or poly ethylene terephthalate, of the second semiconductor package may be less sensitive to the temperature change, thereby improving reliability of the stack package.

An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces at least a portion of which are connected to respective contact points on the die. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; disposing a mold on the sacrificial substrate around; introducing an insulating material into a chase of the mold; removing the mold; forming a carrier on the insulating material adjacent a device side of a die; and separating the die and the carrier from the sacrificial substrate.

In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.

An embodiment is an integrated circuit structure including a first die attached to a second die by a first connector. The first connector includes a solder joint portion between a first nickel-containing layer and a second nickel-containing layer, a first copper-containing layer between the first nickel-containing layer and the solder joint portion, and a second copper-containing layer between the second nickel-containing layer and the solder joint portion.

Systems, manufactures, methods and/or techniques for a merged fiducial for chip packages are described. According to some embodiments, an integrated circuit package may include a package substrate having a first side and a second side, a plurality of conductive traces coupled to the first side and a plurality of balls disposed on the second side. The balls may be adapted to electrically connect the laminate package to a circuit board. The integrated circuit package may include a plurality of ball pads disposed on the second side, the ball pads being adapted to electrically connect the plurality of balls to the plurality of conductive traces. One or more of the ball pads may be uniquely shaped when compared to the rest of the plurality of ball pads, optionally, to serve as a fiducial to designate an A1 pin or ball of the laminate package.

Described herein are methods and systems for providing corrective maintenance using global knowledge sharing. A method to provide corrective maintenance with a CM system includes performing a query to generate a ranking of fixable causes based on factors (e.g., symptoms, configuration, test). The ranking may be determined based on a fixable cause percent match with the factors. The ranking of fixable causes may be associated with one or more solutions for each fixable cause. The ranking can be updated based on performing tests or solutions.

Methods, systems, and structures for detecting residual material on semiconductor wafers are provided. A method includes scanning a test structure including topographic features on a surface of a semiconductor wafer. The method further includes determining, based on the scanning, that the test structure includes an amount of a residual material of a sacrificial layer that exceeds a predetermined threshold.

A base at least one principal plane of which is a nitride is prepared for use in epitaxial growth. The base is placed on a susceptor in an epitaxial growth reactor and heated to a predetermined temperature (step A). The heating is started with inactive, nitrogen gas being supplied into the reactor. Then, active, NH3 gas is supplied. Then, a growth step (step B) of a first nitride semiconductor layer is started without an intervening step of thermally cleaning the principal nitride plane of the base. In step B, the first nitride semiconductor layer is epitaxially grown on a principal nitride plane of a base without supply of an Si source material. Then, a relatively thick, second nitride semiconductor layer is epitaxially grown on the first nitride semiconductor layer by supplying an n-type dopant source material (step C).

In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.

A first impurity region is formed by ion implantation through a first opening formed in a mask layer. By depositing a spacer layer on an etching stop layer on which the mask layer has been provided, a mask portion having the mask layer and the spacer layer is formed. By anisotropically etching the spacer layer, a second opening surrounded by a second sidewall is formed in the mask portion. A second impurity region is formed by ion implantation through the second opening. An angle of the second sidewall with respect to a surface is 90°±10° across a height as great as a second depth. Thus, accuracy in extension of an impurity region can be enhanced.

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.

Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.

Embodiments generally relate to optoelectronic devices and more specifically, to textured layers in optoelectronic devices. In one embodiment, a method for providing a textured layer in an optoelectronic device includes depositing a first layer of a first material and depositing an island layer of a second material on the first layer. Depositing the island layer includes forming one or more islands of the second material to provide at least one textured surface of the island layer, where the textured surface is operative to cause scattering of light.

Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer.

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

An object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H2O, may be eliminated. An oxide insulating layer containing a large number of defects such as dangling bonds may be formed in contact with the oxide semiconductor layer, such that the impurity diffuses into the oxide insulating layer and the impurity concentration in the oxide semiconductor layer is reduced. The oxide semiconductor layer or the oxide insulating layer in contact with the oxide semiconductor layer may be formed in a deposition chamber which is evacuated with use of a cryopump whereby the impurity concentration is reduced.

A method for producing a Ga-containing group III nitride semiconductor having reduced threading dislocation is disclosed. A buffer layer in a polycrystal, amorphous or polycrystal/amorphous mixed state, comprising AlGaN is formed on a substrate. The substrate having the buffer layer formed thereon is heat-treated at a temperature higher than a temperature at which a single crystal of a Ga-containing group III nitride semiconductor grows on the buffer layer and at a temperature that the Ga-containing group III nitride semiconductor does not grow, to reduce crystal nucleus density of the buffer layer as compared with the density before the heat treatment. After the heat treatment, the temperature of the substrate is decreased to a temperature that the Ga-containing group III nitride semiconductor grows, the temperature is maintained, and the Ga-containing group III nitride semiconductor is grown on the buffer layer.

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.

A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.