An automatic lock affixed to a cargo container for interconnecting two stacked containers, and for automatically locking and unlocking without reliance upon the overcoming of a friction force to release the device.

A box stop device includes a base member and a raised member attached to the base member. The base member has a top surface and a bottom surface. The top surface may be flat. The bottom surface may be adapted to attach to a desired surface. The raised member may be attached to the base member and may extend approximately vertically from the top surface. The raised member may include a first side and a second side. The first side and the second side may be attached together at an angle of approximately 90 degrees.

A protective cap for a trailing edge of a rotor blade of a wind turbine for use during transportation, handling, or maintenance of the rotor blade is disclosed. The protective cap includes a body having a first leg, a second leg, and a cap member. The cap member connects the first and second legs. Further, the cap member may be configured to cover at least a portion of a trailing edge of the rotor blade and may be configured to provide a gap between an inner surface of the protective cap and the trailing edge. In addition, the first and second legs may resiliently engage the rotor blade.

An apparatus and method for applying an underlayment layer to trucking cargo are provided. The underlayment layer may be formed into a roll with a rod disposed therethrough. The roll may be supported by a frame. The roll can be configured to move vertically with respect to the ground. A trailer carrying trucking cargo can be stationed beneath the frame. The underlayment layer may unwound and dispensed from the roll. In order to drape the trucking cargo with the underlayment layer, the roll may be moved horizontally over the frame in addition to or alternatively to having the trucking cargo driven horizontally with respect to the roll.

An edge protector for insertion between a load to be lifted and a lifting member which facilitates the lifting of the load, preventing damage to either the load or the lifting member. The edge protector has a pair of flanges which extend from a radiused or curved center portion. Each flange has an inner surface and an outer surface. A portion of each respective outer surface of each flange is spaced from and is essentially parallel to the inner surface of the respective flange.

An apparatus relates generally to a clock generator is disclosed. The clock generator is coupled to receive an input clock signal and further coupled to provide an output clock signal. An address and control register is coupled to receive an address signal and the output clock signal. An access generator is coupled to receive the output clock signal. The clock generator includes: an input node coupled to receive the input clock signal; at least one pulse generator coupled to the input node to receive the input clock signal and further coupled to provide a clock control signal; and a control gate coupled to the input node to receive the input signal and further coupled to the at least one pulse generator to receive the clock control signal. The clock control signal is provided in a non-toggling state for a high-frequency mode and in a toggling state for a low-frequency mode.

A bridge output circuit includes an output terminal, a high side transistor, a low side transistor, a high side driver for controlling a gate voltage of the high side transistor, a low side driver for controlling a gate voltage of the low side transistor, and a controller for controlling the high side and low side drivers. The low side driver includes a first current source, a second current source, and a first assist circuit. The controller is configured to control the turning-on and turning-off states of the first current source, the second current source and the first assist circuit.

An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.

A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

An isolator circuit capable of two-way electrical disconnection and a semiconductor device including the isolator circuit are provided. A data holding portion is provided in an isolator circuit without the need for additional provision of a data holding portion outside the isolator circuit, and data which is to be input to a logic circuit that is in an off state at this moment is stored in the data holding portion. The data holding portion may be formed using a transistor with small off-state current and a buffer. The buffer can include an inverter circuit and a clocked inverter circuit.

Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.

A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

A circuit for a single differential-inductor oscillator with common-mode resonance may include a tank circuit formed by coupling a first inductor with a pair of first capacitors; a cross-coupled transistor pair coupled to the tank circuit; and one or more second capacitors coupled to the tank circuit and the cross-coupled transistors. The single differential-inductor oscillator may be configured such that a common mode (CM) resonance frequency (FCM) associated with the single differential-inductor oscillator is at twice a differential resonance frequency (FD) associated with the single differential-inductor oscillator.

The present disclosure relates to nanoresonator oscillators or NEMS (nanoelectromechanical system) oscillators. A circuit for measuring the oscillation frequency of a resonator is provided, comprising a first phase-locked feedback loop locking the frequency of a controlled oscillator at the resonant frequency of the resonator, this first loop comprising a first phase comparator. Furthermore, a second feedback loop is provided which searches for and stores the loop phase shift introduced by the resonator and its amplification circuit when they are locked at resonance by the first loop. The first and the second loops operate during a calibration phase. A third self-oscillation loop is set up during an operation phase. It directly links the output of the controllable phase shifter to the input of the resonator. The phase shifter receives the phase-shift control stored by the second loop.

A resonator element includes a substrate including a first principal surface and a second principal surface respectively forming an obverse surface and a reverse surface of the substrate, and vibrating in a thickness-shear vibration mode, a first excitation electrode disposed on the first principal surface, and a second excitation electrode disposed on the second principal surface, and being larger than the first excitation electrode in a plan view, the first excitation electrode is disposed so as to fit into an outer edge of the second excitation electrode in the plan view, and the energy trap confficient M fulfills 15.5≦M≦36.7.

A resonator element includes a substrate vibrating in a thickness-shear vibration mode, a first excitation electrode disposed on one principal surface of the substrate, and has a shape obtained by cutting out four corners of a quadrangle, and a second excitation electrode disposed on the other principal surface of the substrate, and a ratio (S2/S1) between the area S1 of the quadrangle and the area S2 of the first excitation electrode fulfills 87.7%≦(S2/S1)

A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

A self-feedback random generator comprises a digital-to-analog converter, a digital oscillator, a frequency-modulating unit and a first D-type flip-flop. The digital-to-analog converter receives a digital random-code signal and the digital random-code signal is converted to corresponding analog random signal. The frequency-modulating unit modulates frequency of first digital oscillating signal so as to increase random of frequency of first digital oscillating signal according to voltage value of the analog random signal, and accordingly outputs a second digital oscillating signal. The first D-type flip-flop receives the second digital oscillating signal and a clock signal, and reads the second digital oscillating signal through utilizing the clock signal so as to outputs the digital random-code signal, wherein frequency of the clock signal is smaller than frequency of the first digital oscillating signal, and random of frequency of the second digital oscillating signal corresponds to random of the digital random-code signal.

There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (100), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider (112) for feeding back an output of a VCO (115) of an output stage to a preceding stage is generated using an error signal from an accumulator (120). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector (140) are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider (112) is suppressed.

A digitally controlled oscillator has a high-order ΔΣ modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ΔΣ modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.

An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

The invention concerns an oscillator generating a wave composed of a frequency of on the order of terahertz from a beat of two optical waves generated by a dual-frequency optical source. The oscillator includes a modulator the transfer function of which is non-linear for generating harmonics with a frequency of less than one terahertz for each of the optical waves generated by the dual-frequency optical source, an optical detector able to detect at least one harmonic for each of the optical waves generated by the dual-frequency optical source and transforming the harmonics detected into an electrical signal, a phase comparator for comparing the electrical signal with a reference electrical signal, and a module for controlling at least one element of the dual-frequency optical source with a signal obtained from the signal resulting from the comparison.

A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string.

Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of output signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.

The present invention discloses an Oven Controlled Crystal Oscillator and a manufacturing method thereof. The Oven Controlled Crystal Oscillator comprises a thermostatic bath, a heating device, a PCB and a signal generating element, where the signal generating element is used for generating a signal of a certain frequency, the heating device, the PCB and the signal generating element are mounted in the thermostatic bath, the signal generating element is mounted in a groove formed on one side of the PCB, while the heating device is mounted against the other side of the PCB that is opposite to the groove. The signal generating element may be a passive crystal resonator or an active crystal oscillator. The Oven Controlled Crystal Oscillator according to the invention is advantageous for a small volume and a high temperature control precision.

An oscillator outputs a control signal to suppress an influence caused by temperature characteristic of f1 based on a differential signal corresponding to difference between an oscillation output f1 of a first oscillator circuit and an oscillation output f2 of a second oscillator circuit treated as a temperature detection value. A switching unit switches between a first state and a second state. The first state is a state where a first connecting end and a second connecting end are connected to a storage unit for access from an external computer to the storage unit. The second state is a state where the first connecting end and the second connecting end are connected to a first signal path and a second signal path such that the respective f1 and f2 are retrieved from the first connecting end and the second connecting end to an external frequency measuring unit.

An atomic oscillator includes: a gas cell which includes two window portions having a light transmissive property and in which metal atoms are sealed; a light emitting portion that emits excitation light to excite the metal atoms in the gas cell; a light detecting portion that detects the excitation light transmitted through the gas cell; a heater that generates heat; and a connection member that thermally connects the heater and each window portion of the gas cell to each other.

An oscillator configured to oscillate an electromagnetic wave, including: a negative resistance device; a microstrip resonator configured to determine an oscillation frequency of an electromagnetic wave excited by the negative resistance device; a resistance device and a capacitance device, which form a low-impedance circuit configured to suppress parasitic oscillation; and a strip conductor configured to connect the capacitance device of the low-impedance circuit and the microstrip resonator to each other, in which an inductance L of the strip conductor and a capacitance C of the microstrip resonator produce a resonance frequency of ½π√LC, and ¼ of an equivalent wavelength of the resonance frequency is larger than a distance between the negative resistance device and the resistance device of the low-impedance circuit via the strip conductor, is provided.

An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.

A method, an apparatus, and a computer program product are provided. The apparatus tunes a frequency provided by a VCO. The apparatus determines a relative capacitance change associated with a first frequency and a desired frequency from a look-up table. The apparatus adjusts a capacitor circuit in the VCO based on the determined relative capacitance change determined from the look-up table in order to tune from the first frequency to the desired frequency. The apparatus determines that the frequency provided by the VCO is a second frequency different than the desired frequency after adjusting the capacitor circuit. The apparatus performs an iterative search to further adjust the capacitor circuit when a difference between the second frequency and the desired frequency is greater than a threshold.

A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.

A system is disclosed for a voltage controlled oscillator (“VCO”) having a large frequency range and a low gain. Passive or active circuitry is introduced between at least one VCO cell in the voltage controlled oscillator and the voltage source for the VCO cell which reduces a gain value for the VCO to maintain stability of the system.

An oscillator includes: a piezoelectric material to vibrate; a first inverting amplifier; a second inverting amplifier; a first output electrode to apply an output signal of the first inverting amplifier to the piezoelectric material; a second output electrode to apply an output signal of the second inverting amplifier to the piezoelectric material; a first input electrode to receive a voltage signal generated by the piezoelectric material and output the voltage signal to the first inverting amplifier; and a second input electrode to receive the voltage signal and output the voltage signal to the second inverting amplifier, wherein the first and second output electrodes are coupled to the piezoelectric material so that faces of the piezoelectric material move in opposite directions, and the first and second input electrodes are coupled to the piezoelectric material so that the voltage signals are input to the first and second input electrodes.

An injection locking oscillator (ILO) comprising a tank circuit having a digitally controlled capacitor bank, a cross-coupled differential transistor pair coupled to the tank circuit, at least one signal injection node, and at least one output node configured to provide an injection locked output signal; a digitally controlled injection-ratio circuit having an injection output coupled to the at least one signal injection node, configured to accept an input signal and to generate an adjustable injection signal applied to the at least one injection node; and, an ILO controller connected to the capacitor bank and the injection-ratio circuit configured to apply a control signal to the capacitor bank to adjust a resonant frequency of the tank circuit and to apply a control signal to the injection-ratio circuit to adjust a signal injection ratio.

Embodiments of the present invention provide a temperature compensation method and a crystal oscillator, where the crystal oscillator includes a crystal oscillation circuit unit, a temperature sensor unit, an oscillation controlling unit, a relative temperature calculating unit, and a temperature compensating unit. The temperature sensor unit measures a measured temperature of the crystal oscillation circuit unit; the relative temperature calculating unit obtains a temperature difference between the measured temperature and a reference temperature; the temperature compensating unit obtains a temperature compensation value corresponding to the temperature difference from a temperature-frequency curve; and the oscillation controlling unit generates a frequency control signal, according to a frequency tracked by a communications AFC device and the temperature compensation value, thereby controlling a frequency of the crystal oscillation circuit unit to work on the tracked frequency.

Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.

A current output control device is provided that includes: a current cell array section including plural current cell circuits that are each connected in parallel between a first terminal (power source) and a second terminal (ground) that connect between the first terminal and the second terminal in by operation ON so as to increase control current flowing between the first terminal and the second terminal; and a code conversion section (decoder) that generates signals (row codes, column codes) to ON/OFF control current cells so as to change the number of current cells that connect the first terminal and the second terminal according to change in an externally input code and that inputs the generated signals to the current cell array section.

This invention discloses a crystal oscillator, in which by appropriately designing the gain of an amplifier to achieve high trans-conductance and low power consumption. This crystal oscillator includes a first pad, coupled to a first node of a crystal, for receiving a crystal oscillating signal outputted from the crystal; an amplifier, coupled to the first pad, for amplifying the crystal oscillating signal to generate an amplifying signal; an inverter, coupled to the amplifier, for inverting the amplifying signal; and a second pad, coupled to a second node of the crystal, for outputting an oscillating signal to the crystal.

A ring oscillator circuit causing a pulse signal to circulate around a circle to which an even number of inverting circuits are connected in a ring, wherein one of the inverting circuits is a first starting inverting circuit, which drives a first pulse signal according to a control signal, another of the inverting circuits is a second starting inverting circuit, which drives a second pulse signal based on a leading edge of the first pulse signal, still another is a third starting inverting circuit, which drives a third pulse signal based on the leading edge of the first pulse signal after the second pulse signal is driven, and the first to third starting inverting circuits are arranged within the circle of the inverting circuits in order of the third, second, and first pulse signals in traveling directions of the pulse signals.

An integrated oscillator circuit comprises an oscillator configured to be switched between a first frequency and a second frequency. A switching circuit receives an input representing a target frequency and switches the oscillator between the first and second frequencies at intervals determined by the input, so as to cause the average output frequency of the oscillator to approximate the target frequency.

The switching element is provided in a state of being electromagnetically coupled to the cavity resonator of the high frequency oscillator; the bias voltage applying terminal is connected to one electrode of the switching element; another electrode of the switching element is electrically connected to the cavity resonator (the anode shell in FIG. 1); the metal plate having a size enough for reflecting an electric wave to be transmitted before and after the switching element in a high-frequency manner is provided at any one end of the switching element; and by applying a bias voltage to the switching element and varying that, a reactance of the switching element is changed and a resonance frequency of the cavity resonator is varied. By this method, an oscillation frequency can be varied greatly relative to a small change in a bias voltage.

An enhanced negative resistance voltage controlled oscillator (VCO) circuit is provided, in which a parallel connection of a capacitor and a resistor configured to provide frequency-dependent transconductance is present across source nodes of a first pair of field effect transistors in which gate nodes and drain nodes are cross-coupled. The source nodes of the first pair of field effect transistors are electrically shorted to drain nodes of a second pair of field effect transistors of which the gate nodes are electrically shorted to the gate nodes of the first pair of field effect transistors. The parallel connection of the capacitor and the resistor includes a parallel connection of a capacitor and a resistor such that the net transconductance of the first pair of field effect transistors is less at low frequencies where thermal noise and flicker noise are dominant part of the phase noise than at the operational frequency range.

A vibration element includes a piezoelectric substrate including a vibrating section and a thick section having a thickness larger than that of the vibrating section. The thick section includes a first thick section provided along a first outer edge of the vibrating section, a second thick section provided along a second outer edge, and a third thick section provided along another first outer edge. An inclined outer edge section that intersects with each of an X axis and a Z' axis is provided in a tip section of the piezoelectric substrate.

Arrays of resonator sensors include an active wafer array comprising a plurality of active wafers, a first end cap array coupled to a first side of the active wafer array, and a second end cap array coupled to a second side of the active wafer array. Thickness shear mode resonator sensors may include an active wafer coupled to a first end cap and a second end cap. Methods of forming a plurality of resonator sensors include forming a plurality of active wafer locations and separating the active wafer locations to form a plurality of discrete resonator sensors. Thickness shear mode resonator sensors may be produced by such methods.

A crystal controlled oscillator includes a crystal package and an IC chip board that includes an IC chip integrating an oscillator circuit. The crystal package includes a first container, a crystal resonator, a lid body, and an external terminal at an outer bottom surface of the first bottom wall layer of the first container. The IC chip integrates an oscillator circuit disposed at an outer bottom surface of the first bottom wall layer of the crystal package. The oscillator circuit connects to the lower side excitation electrode of the crystal resonator from the external terminal to an input side with high impedance. The oscillator circuit connects to the upper side excitation electrode to an output side with low impedance. The upper side excitation electrode is a shielding electrode of the crystal resonator.

An apparatus is disclosed that includes a first cross-coupled transistor pair, a second cross-coupled transistor pair, at least one capacitance unit, and an inductive unit. The first cross-coupled transistor pair and second cross-coupled transistor pair are coupled to a pair of first output nodes and a pair of second output nodes, respectively. The at least one capacitance unit is coupled to at least one of the pair of first output nodes and the pair of second output nodes. The inductive unit is coupled to the first cross-coupled transistor pair at the first output nodes and coupled to the second cross-coupled transistor pair at the second output nodes. The inductive unit generates mutual magnetic coupling between one of the first output nodes and one of the second output nodes and between the other of the first output nodes and the other of the second output nodes.

A solenoid actuator comprising an armature member that engages a spool including a spool cap on an end of the spool that is axially movable relative to the spool. A bore in the spool allows fluid to flow from a control port to the spool cap, such that pressure is established in the spool cap. The pressure established in the spool cap acts on the spool with a force directly proportional to the control pressure and the fluid-contacting area inside the spool cap.