A box stop device includes a base member and a raised member attached to the base member. The base member has a top surface and a bottom surface. The top surface may be flat. The bottom surface may be adapted to attach to a desired surface. The raised member may be attached to the base member and may extend approximately vertically from the top surface. The raised member may include a first side and a second side. The first side and the second side may be attached together at an angle of approximately 90 degrees.

A module in the form of a pallet or a closed container includes a grouping together of the electrical devices in an avionics bay, in which the electrical devices are interconnected and attached so as to facilitate the mounting and thus limit the time it takes to mount the electrical devices in the avionics bay.

An apparatus for selectively securing a boat to a trailer may include a hull contact structure for abutting against the boat hull, and a releasable gripping structure positioned adjacent the hull contact structure to engage the boat's securing loop and selectively lock onto the loop to hold the boat to the trailer.

A novel configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations is provided. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. The configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. The configuration network is a pipelined network.

A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.

A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.

Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc.

Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.

Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.

A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.

A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.

The present invention relates to a method for downloading a binary configuration file in a programmable circuit implemented in a device. The device comprises at least one central processing unit, a plurality of connectors, and a programmable circuit enabling all or a part of the signals received by said connectors to be processed and transmitted to at least one other circuit of the device. The device analyzes the signals present on the connectors in order to define what other devices are connected and whether the connections are operational. Then, a configuration file is selected from among a set of configuration files according to the operational connections and is downloaded from a memory of the device into the programmable circuit. The invention also relates to a device having a component programmed according to the method previously described.

An integrated circuit (IC) with a novel configurable routing fabric is provided. The configurable routing fabric has signal paths that propagate signals between user registers on user clock cycles. Each signal path includes a set of configurable storage elements and a set of configurable logic elements. Each configurable storage element in the path is reconfigurable on every sub-cycle of the user clock cycle to either store an incoming signal or to pass the incoming signal transparently.

Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.

According to one embodiment, a first oscillator has an oscillation frequency that is changed depending on a temperature. A second oscillator has different temperature characteristics from the first oscillator. An on-chip heater heats the first oscillator and the second oscillator. A counter counts a first oscillation signal of the first oscillator. An ADPLL generates a third oscillation signal on the basis of a second oscillation signal of the second oscillator and corrects the frequency of the third oscillation signal on the basis of a count value of the counter.

A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (100), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider (112) for feeding back an output of a VCO (115) of an output stage to a preceding stage is generated using an error signal from an accumulator (120). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector (140) are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider (112) is suppressed.

An oscillation device is provided. The oscillation device includes: a main circuit portion, a heating unit, first and second crystal units, first and second oscillator circuits, a frequency difference detector, a first addition unit, an integration circuit unit, a circuit unit configured to control an electric power to be supplied to the heating unit, a compensation value obtaining unit, and a second addition unit. The compensation value obtaining unit is configured to obtain a frequency compensation value for compensating an output frequency of the main circuit portion based on an integrated value output from the integration circuit unit, and based on a change in the clock signal due to a difference between the temperature of the atmosphere and the temperature setting value of the heating unit. The second addition unit is configured to add the frequency compensation value to a frequency setting value.

A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.

An injection locking oscillator (ILO) comprising a tank circuit having a digitally controlled capacitor bank, a cross-coupled differential transistor pair coupled to the tank circuit, at least one signal injection node, and at least one output node configured to provide an injection locked output signal; a digitally controlled injection-ratio circuit having an injection output coupled to the at least one signal injection node, configured to accept an input signal and to generate an adjustable injection signal applied to the at least one injection node; and, an ILO controller connected to the capacitor bank and the injection-ratio circuit configured to apply a control signal to the capacitor bank to adjust a resonant frequency of the tank circuit and to apply a control signal to the injection-ratio circuit to adjust a signal injection ratio.

Embodiments of the present invention provide a temperature compensation method and a crystal oscillator, where the crystal oscillator includes a crystal oscillation circuit unit, a temperature sensor unit, an oscillation controlling unit, a relative temperature calculating unit, and a temperature compensating unit. The temperature sensor unit measures a measured temperature of the crystal oscillation circuit unit; the relative temperature calculating unit obtains a temperature difference between the measured temperature and a reference temperature; the temperature compensating unit obtains a temperature compensation value corresponding to the temperature difference from a temperature-frequency curve; and the oscillation controlling unit generates a frequency control signal, according to a frequency tracked by a communications AFC device and the temperature compensation value, thereby controlling a frequency of the crystal oscillation circuit unit to work on the tracked frequency.

A ring oscillator circuit causing a pulse signal to circulate around a circle to which an even number of inverting circuits are connected in a ring, wherein one of the inverting circuits is a first starting inverting circuit, which drives a first pulse signal according to a control signal, another of the inverting circuits is a second starting inverting circuit, which drives a second pulse signal based on a leading edge of the first pulse signal, still another is a third starting inverting circuit, which drives a third pulse signal based on the leading edge of the first pulse signal after the second pulse signal is driven, and the first to third starting inverting circuits are arranged within the circle of the inverting circuits in order of the third, second, and first pulse signals in traveling directions of the pulse signals.

The switching element is provided in a state of being electromagnetically coupled to the cavity resonator of the high frequency oscillator; the bias voltage applying terminal is connected to one electrode of the switching element; another electrode of the switching element is electrically connected to the cavity resonator (the anode shell in FIG. 1); the metal plate having a size enough for reflecting an electric wave to be transmitted before and after the switching element in a high-frequency manner is provided at any one end of the switching element; and by applying a bias voltage to the switching element and varying that, a reactance of the switching element is changed and a resonance frequency of the cavity resonator is varied. By this method, an oscillation frequency can be varied greatly relative to a small change in a bias voltage.

A vibration element includes a piezoelectric substrate including a vibrating section and a thick section having a thickness larger than that of the vibrating section. The thick section includes a first thick section provided along a first outer edge of the vibrating section, a second thick section provided along a second outer edge, and a third thick section provided along another first outer edge. An inclined outer edge section that intersects with each of an X axis and a Z' axis is provided in a tip section of the piezoelectric substrate.

An electronic oscillator circuit has a first oscillator, for supplying a first oscillation signal, a second oscillator, for supplying a second oscillation signal, a first controller for delivering the first control signal as a function of a phase difference between a first controller input and a second controller input of the first controller; a second controller for delivering the second control signal as a function of a phase difference between a first controller input of the second controller and a second controller input of the second controller; a resonator; at least a second resonance frequency, with a first phase shift dependent on the difference between the frequency of a second exciting signal and the second resonance frequency and processing means, for receiving the first oscillator signal and the second oscillator signal, determining their mutual proportion, looking up a frequency compensation factor in a prestored table and outputting a compensated oscillation signal.

In a method for operating a fluid valve for controlling or regulating a fluid, having at least one movable valve component is displaceable with the aid of at least one electrical actuating signal which contains at least one first actuating signal portion which causes an oscillating valve motion of the valve component. Pressure oscillations generated in the fluid due to the oscillating valve motion are detected, and are used for regulation of the oscillating valve motion caused by the first actuating signal portion.

A method of isolating a section of pipe includes the steps of locating a seal unit having two seal elements in a pipe via a penetration in the pipe, such as a branch or tee. The seal unit is then positioned in the pipe downstream of the penetration. The seal elements are activated using a primary activation mechanism to engage the pipe wall and then maintained in an activated condition using a secondary activation mechanism.

Water valves and methods of regulating fluid flow for low ambient pressure water sources that reduce the amount of filtration needed for valve mechanisms operating in the water source.

A drain plug assembly that has particular application for sealing a drain hole in a high voltage battery compartment on a vehicle. The plug assembly includes a plug that inserted into the drain hole. The plug assembly further includes a return spring coupled to the plug and causing the plug to be biased into the drain hole. The plug assembly also includes at least one shape memory alloy device coupled to the plug and a support structure. The SMA device receives an electrical current that causes the device to contract and move the plug out of the drain hole against the bias of the return spring.

A method for operating a collection system for printed products includes drawing off the printed products from discharge device(s) disposed at corresponding discharge point(s) in the collection system. The printed products are deposited on a collection section during a cycle period of the discharge device(s) so as to form a bundle of printed products. The bundle is transferred to a subsequent conveying mechanism having receiving pockets. It is determined whether at least one missing printed product exists due to an incorrect drawing off from the discharge point(s). A repair process is initiated and controlled in which the at least one missing printed product is drawn off from the corresponding discharge point(s) at a time corresponding to a subsequent recurrent pocket-related cycle of the subsequent conveying mechanism in a subsequent cycle period of the discharge device(s). The at least one missing printed product is inserted in the relevant receiving pocket.

A method and device for the production of books, including: moving book blocks successively along a conveying section of a book production line; supplying a stack of book cases to the book production line; identifying a marking on each of the book blocks and the book cases; transmitting an identified marking on at least one book case to a machine control of the book production line; assigning a dataset stored in the machine control for a sequence of book cases to the supplied stack; determining a sequence in the machine control for book blocks positioned on the conveying section; comparing the dataset for the sequence of the book cases to the sequence of the book blocks; and removing and/or supplying at least one book block from or to the conveying section if the sequence of the book blocks deviates from the sequence of the book cases using the machine control.

A method of producing a print product comprises: performing digital printing of each surface of the print product, sequentially and repeatedly, on a continuous paper; forming a section by cutting the printing-completed continuous paper into a paper sheet and folding the paper sheet in two; forming a section block by at least one of sections; and folding the section block in two.

In an embodiment, a processor-readable medium stores code representing instructions that when executed by a processor cause the processor to receive sheet length data for two paper sheets of a same standard dimension passing consecutively through a printing device. The processor calculates a length difference between the two paper sheets, and when the length difference exceeds a two-sheet threshold, it initiates an alignment correction cycle in a paper finishing device.

An image recording apparatus includes: a recording unit for recording an image on a recording medium; a tray for supporting the recording medium recorded by the recording unit; a conveyor mechanism for conveying the recorded medium to the tray; and an alignment mechanism for aligning a plurality of recording media stacked on the tray, by application of an external force. In a period from a start to an end of recording based on one recording job, the alignment mechanism aligns the plurality of recording media stacked on the tray in a period in which image recording is not performed, and the alignment mechanism does not align the plurality of recording media stacked on the tray in a period in which image recording is being performed.

To provide a sheet storage apparatus for enabling sheets that are carried out of an image formation apparatus or the like on the upstream side to be loaded and stored in a predetermined position with a correct posture neatly at high speed, a sheet discharge roller and a reverse roller spaced a distance are disposed in a sheet discharge outlet and a tray, a kick member is provided to be swingable in a vertical direction passing a sheet discharge path of a sheet discharged from the sheet discharge outlet, and a posture of the kick member is controlled by shift means. The shift means controls the kick member among a waiting posture retracted upward from the sheet discharge path, an engagement posture for imposing a load on the sheet to engage, and an actuation posture dropping onto the tray together with the sheet.

A multi-function binding machine is proposed. The multi-function binding machine (700) comprises a binding station (135) for binding blocks of signatures (105), and a feeding station (115) for receiving signatures in succession, opening the signatures, and feeding the signatures to the binding station; in the solution according to an embodiment of the invention, the multi-function binding machine further comprises a further feeding station (715) for receiving pre-signatures in successions, folding groups of at least one pre-signature into further signatures (729), and feeding the further signatures to the binding station.

Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via.

Methods, systems, and structures for detecting residual material on semiconductor wafers are provided. A method includes scanning a test structure including topographic features on a surface of a semiconductor wafer. The method further includes determining, based on the scanning, that the test structure includes an amount of a residual material of a sacrificial layer that exceeds a predetermined threshold.

A light emitting element array for an illumination apparatus, an illumination apparatus and method of manufacture of the same in which an array of light-emitting elements and an array of light directing optics are provided between first and second attached mothersheet substrates wherein the thermal resistance of at least one of the mothersheet substrates is reduced by means of thickness reduction so as to provide reduced LED junction temperature.

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

Embodiments generally relate to optoelectronic devices and more specifically, to textured layers in optoelectronic devices. In one embodiment, a method for providing a textured layer in an optoelectronic device includes depositing a first layer of a first material and depositing an island layer of a second material on the first layer. Depositing the island layer includes forming one or more islands of the second material to provide at least one textured surface of the island layer, where the textured surface is operative to cause scattering of light.

A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.