For a flap assembly, in particular an exhaust gas flap assembly, with the flap mounted on both sides via bearing devices in the housing, the disclosure describes a design in which a bearing body is supported radially against an annular collar of the bearing device and, by way of the annular collar, is held braced in a radially spring-loaded manner in a predefined radial position.

The present invention involves, in some embodiments, systems and methods involving fluid handling apparatus for pumping fluid to and from a patient, which may include a reusable component and a disposable pumping cartridge. The reusable component may comprise a control chamber and a pressure transducer configured to measure a gas pressure associated with the control chamber, as well as a processor. The processor may be configured to supply the control chamber with a gas at a predetermined pressure, monitor the gas pressure associated within the control chamber with the pressure transducer over a predetermined period of time, and determine if the change in gas pressure associated within the control chamber exceeds a maximum allowable predetermined limit.

A method and device for the production of books, including: moving book blocks successively along a conveying section of a book production line; supplying a stack of book cases to the book production line; identifying a marking on each of the book blocks and the book cases; transmitting an identified marking on at least one book case to a machine control of the book production line; assigning a dataset stored in the machine control for a sequence of book cases to the supplied stack; determining a sequence in the machine control for book blocks positioned on the conveying section; comparing the dataset for the sequence of the book cases to the sequence of the book blocks; and removing and/or supplying at least one book block from or to the conveying section if the sequence of the book blocks deviates from the sequence of the book cases using the machine control.

A method for operating a processing system, in which product units of different formats are processed. The processing system contains a plurality of processing devices that are arranged one after the other in a processing line. In the event of a format changeover, certain component arrangements arranged in the processing system must be adapted to the new product format. In the event of an upcoming format change, a gap in the conveyed goods is generated while the conveying operation is maintained, wherein the gap in the conveyed goods runs through the processing system along the processing devices. As soon as the gap in the conveyed goods runs through a component arrangement to be adapted to the new format, the format is changed over at the component arrangement while the gap in the conveyed goods runs through the component arrangement.

An apparatus and method are provided, for alternatively producing either small or bulk packs of napkins from a stack of folded napkins produced by one folding machine, through use of a pack dispatching arrangement having an inlet, a small pack transfer station and a bulk pack transfer station, and configured for operation in a small pack mode for dispatching a stream of spaced apart small packs of folded sheets separated from the stack of folded sheets, and received at an inlet of the pack dispatching arrangement, to the small pack transfer station, and alternatively operable in a bulk pack mode for dispatching a stream of spaced apart bulk packs of folded sheets separated from the stack of folded sheets, and received at an inlet of the pack dispatching arrangement, to the bulk pack transfer station.

A supply device (10) for a machine for transversely cutting two strips (11 and 12) of a flexible material, in particular a strip of paper, moving continuously, to produce separate stacks of documents cut transversely according to predetermined formats. The device comprises lower and upper driving mechanisms (13, 14) associated with the two strips (11, 12) of flexible material respectively, which each include a mechanically rotated first roller (13a, 14a) and a freely rotatable second bearing roller (13b and 14b). The driving mechanism is mounted on a frame (15) supported by a movable platform (16) which is rigidly connected to a linear actuator (17) arranged to be moved transversely with respect to the direction of movement of the strips (11 and 12). Optical reading cells (11a, 11b, 12a, 12b) define the operating modes of the driving servomotors (13b and 14b) and of the linear actuator (17).

The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.

Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

The stack package includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first substrate having a first modulus and at least one semiconductor chip mounted on the first substrate. The second semiconductor package stacked on the first semiconductor package and includes a second substrate having a second modulus and at least one semiconductor chip mounted on the second substrate. The second modulus is less than the first modulus. Even in the event that the first semiconductor package is under severe warpage due to a temperature change, the flexible second substrate, which includes e.g., polyimide or poly ethylene terephthalate, of the second semiconductor package may be less sensitive to the temperature change, thereby improving reliability of the stack package.

Maskless hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface with a plurality of integrated circuits thereon and having a passivation layer disposed between and covering metal pillar/solder bump pairs of the integrated circuits involves laser scribing, without the use of a mask layer, the passivation layer to provide scribe lines exposing the semiconductor wafer. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the passivation layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves thinning the passivation layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.

An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces at least a portion of which are connected to respective contact points on the die. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; disposing a mold on the sacrificial substrate around; introducing an insulating material into a chase of the mold; removing the mold; forming a carrier on the insulating material adjacent a device side of a die; and separating the die and the carrier from the sacrificial substrate.

Systems, manufactures, methods and/or techniques for a merged fiducial for chip packages are described. According to some embodiments, an integrated circuit package may include a package substrate having a first side and a second side, a plurality of conductive traces coupled to the first side and a plurality of balls disposed on the second side. The balls may be adapted to electrically connect the laminate package to a circuit board. The integrated circuit package may include a plurality of ball pads disposed on the second side, the ball pads being adapted to electrically connect the plurality of balls to the plurality of conductive traces. One or more of the ball pads may be uniquely shaped when compared to the rest of the plurality of ball pads, optionally, to serve as a fiducial to designate an A1 pin or ball of the laminate package.

A base at least one principal plane of which is a nitride is prepared for use in epitaxial growth. The base is placed on a susceptor in an epitaxial growth reactor and heated to a predetermined temperature (step A). The heating is started with inactive, nitrogen gas being supplied into the reactor. Then, active, NH3 gas is supplied. Then, a growth step (step B) of a first nitride semiconductor layer is started without an intervening step of thermally cleaning the principal nitride plane of the base. In step B, the first nitride semiconductor layer is epitaxially grown on a principal nitride plane of a base without supply of an Si source material. Then, a relatively thick, second nitride semiconductor layer is epitaxially grown on the first nitride semiconductor layer by supplying an n-type dopant source material (step C).

A method for fabricating a sensor includes: forming, on a base substrate, a pattern of a source electrode and a drain electrode, a pattern of a data line, a pattern of a receiving electrode, a pattern of a photodiode, and a pattern of a transparent electrode disposed by using a first patterning process; forming a pattern of an ohmic layer by using a second patterning process; forming a pattern of an active layer by using a third patterning process; forming a pattern of a gate insulating layer by using a fourth patterning process, wherein the gate insulating layer has a via hole above the transparent electrode; and forming a pattern of a gate electrode, a pattern of a gate line, and a pattern of a bias line connected to the transparent electrode via the via hole above the transparent electrode by using a fifth patterning process.

In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.

A first impurity region is formed by ion implantation through a first opening formed in a mask layer. By depositing a spacer layer on an etching stop layer on which the mask layer has been provided, a mask portion having the mask layer and the spacer layer is formed. By anisotropically etching the spacer layer, a second opening surrounded by a second sidewall is formed in the mask portion. A second impurity region is formed by ion implantation through the second opening. An angle of the second sidewall with respect to a surface is 90°±10° across a height as great as a second depth. Thus, accuracy in extension of an impurity region can be enhanced.

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.

Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer.

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

An object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H2O, may be eliminated. An oxide insulating layer containing a large number of defects such as dangling bonds may be formed in contact with the oxide semiconductor layer, such that the impurity diffuses into the oxide insulating layer and the impurity concentration in the oxide semiconductor layer is reduced. The oxide semiconductor layer or the oxide insulating layer in contact with the oxide semiconductor layer may be formed in a deposition chamber which is evacuated with use of a cryopump whereby the impurity concentration is reduced.

A method for producing a Ga-containing group III nitride semiconductor having reduced threading dislocation is disclosed. A buffer layer in a polycrystal, amorphous or polycrystal/amorphous mixed state, comprising AlGaN is formed on a substrate. The substrate having the buffer layer formed thereon is heat-treated at a temperature higher than a temperature at which a single crystal of a Ga-containing group III nitride semiconductor grows on the buffer layer and at a temperature that the Ga-containing group III nitride semiconductor does not grow, to reduce crystal nucleus density of the buffer layer as compared with the density before the heat treatment. After the heat treatment, the temperature of the substrate is decreased to a temperature that the Ga-containing group III nitride semiconductor grows, the temperature is maintained, and the Ga-containing group III nitride semiconductor is grown on the buffer layer.

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.

A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.

A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.

In a semiconductor device, where, with respect to a parasitic resistor in a current mirror circuit, a compensation resistor for compensating the parasitic resistor is provided in the current mirror circuit, the current mirror circuit includes at least two thin film transistors. The thin film transistors each have an island-shaped semiconductor film having a channel formation region and source or drain regions, a gate insulating film, a gate electrode, and source or drain electrodes, and the compensation resistor compensates the parasitic resistor of any one of the gate electrode, the source electrode, and the drain electrode. In addition, each compensation resistor has a conductive layer containing the same material as the gate electrode, the source or drain electrodes, or the source or drain regions.

A sensor substrate includes a blocking pattern disposed on a base substrate, a first electrode disposed on the base substrate and overlapping the blocking pattern, the first electrode including a plurality of first unit parts arranged in a first direction, each of the first unit parts including a plurality of lines connected to each other in a mesh-type arrangement, a color filter layer disposed on the base substrate, a plurality of contact holes defined in the color filter layer and exposing the first unit parts, and a bridge line between and connected to first unit parts adjacent to each other in the first direction, through the contact holes.

An opposed substrate (9') comprises: a substrate (1); a static electricity protective electrode (2), a bridging electrode (4) and a touch induction electrode (6) comprising a plurality of sub-units sequentially formed on the substrate (1), wherein the distribution of the static electricity protective electrode (2) on the substrate (1) corresponds to dummy regions between sub-units, and the static electricity protective electrode (2), the bridging electrode (4) and the touch induction electrode (6) are insulated from each other. The opposed substrate (9') has a good touching effect. A method for manufacturing the opposed substrate, and a liquid crystal display touch panel are also disclosed.

In a semiconductor device, a first interlayer insulating layer made of an inorganic material and formed on inverse stagger type TFTs, a second interlayer insulating layer made of an organic material and formed on the first interlayer insulating layer, and a pixel electrode formed in contact with the second interlayer insulating layer are disposed on a substrate, and an input terminal portion that is electrically connected to a wiring of another substrate is provided on an end portion of the substrate. The input terminal portion includes a first layer made of the same material as that of the gate electrode and a second layer made of the same material as that of the pixel electrode. With this structure, the number of photomasks used in the photolithography method can be reduced to 5.

A liquid crystal display panel, including: a pixel electrode formed on a first substrate; an alignment layer formed on the pixel electrode, wherein the alignment layer includes an alignment layer material and aligns first liquid crystal molecules in a direction substantially perpendicular to the pixel electrode; and a photo hardening layer formed on the alignment layer, wherein the photo hardening layer includes a photo hardening layer material and aligns second liquid crystal molecules to be tilted with respect to the pixel electrode, wherein the alignment layer material and the photo hardening layer material have different polarities from each other.

The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.

The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.

The present invention relates to an anti-human α9 integrin antibody. More particularly, the present invention relates to: a monoclonal antibody, a chimeric antibody, a humanized antibody and a human antibody that specifically recognize human α9 integrin; a hybridoma cell that produces the monoclonal antibody; a method for producing the monoclonal antibody; a method for producing the hybridoma cell; a therapeutic agent comprising the anti-human α9 integrin antibody; a diagnostic agent comprising the human α9 integrin antibody; and a method for screening for a compound that inhibits the activity of human α9 integrin.

Thrombospondin 1 (TSP-1), TSP-2, interleukin 17B receptor (IL-17BR) and heparin-binding epidermal growth factor-like growth factor (HB-EGF) associated with stem cell activity and use thereof.

Methods of washing adherent cells, capable of effectively suppressing cell death due to proteolytic enzyme treatment for detaching the adherent cell from a culture vessel and subsequent cell treatment; cell-washing solutions used for the washing method; methods of producing cell suspensions for transplantation using the cell-washing solution; and kits comprising the cell-washing solution. Trehalose or its derivative or a salt thereof is added to physiological aqueous solutions to prepare cell-washing solutions containing trehalose or its derivative or a salt thereof as an active ingredient. The cell-washing solutions can be used to wash adherent cells before detaching the adherent cells from a culture vessel by proteolytic enzyme treatment to suppress cell death due to the proteolytic enzyme treatment. The concentration of trehalose applied to the cell-washing solution may be a concentration capable of suppressing the cell death due to the proteolytic enzyme treatment, such as 0.1 to 20 (w/v) %.

Methods and devices for separating fluid-suspended plant somatic embryos and embryogenic tissue based on differences in their fluid drag properties are disclosed. Deposition method and device for depositing plant somatic embryos into embryo receiver comprising growth substrate by means of a fluid jet is disclosed. An automated system for processing plant somatic embryos from the bioreactor to the growth substrate is also disclosed.

Disclosed are new members of a class of non-lipid small molecule inhibitors which interfere with the interaction between phosphoinositol-3,4,5-triphosphate (PIP3) and pleckstrin homology (PH) domains. These molecules target a broad range of PIP3-dependent signaling events in vitro and exert significant anti-tumor activity in vivo, with improved activity and selectivity toward particular PH domains. The small molecule inhibitors of the invention can be used alone or together with tumor necrosis factor (TNF)-related apoptosis-inducing ligand (TRAIL) or other cancer medicament to treat cancer. Small molecule inhibitors of the invention act synergistically in combination with TRAIL and with other Akt inhibitors in treating cancer. Pharmaceutical compositions and methods for treating cancer are provided.

Monoclonal antibodies (mAbs) having thyroid stimulating activity (TSAb), especially full or considerably agonistic activity, or thyroid blocking activity (TBAb), which are obtainable by genetic immunization of mice, or fragments (F(ab')2, Fab or Fv) or humanized forms of such monoclonal antibodies or single chain forms (SCA; scFv) of such fragments, which antibodies, or their fragments, compete with bovine TSH for epitopes of the human TSHr, compete with autoantibodies from sera from Graves' patients as well as with autoantibodies from sera from patients harboring blocking autoantibodies for epitopes of the human TSHr, bind to conformational epitopes of the human TSHr located in the first 281 amino acids of the human TSHr, and usually also bind to TSFR receptors (TSHr) from different animals. Various uses of such antibodies, or of peptides corresponding to variable regions of such antibodies, are also described and claimed.

Described herein are techniques for assembling a polynucleotide encoding a transcription activator-like effector nucleases (TALEN). The techniques ligate and digest necessary modules for a TALEN assembly in one reactor or system. Methods and Kits for generating a TALEN are also described.

This invention provides recombinant DNA constructs and methods for manipulating expression of a target gene that is regulated by a small RNA, by interfering with the binding of the small RNA to its target gene. More specifically, this invention discloses recombinant DNA constructs encoding cleavage blockers, 5-modified cleavage blockers, and translational inhibitors useful for modulating expression of a target gene and methods for their use. Further disclosed are miRNA targets useful for designing recombinant DNA constructs including miRNA-unresponsive transgenes, miRNA decoys, cleavage blockers, 5-modified cleavage blockers, and translational inhibitors, as well as methods for their use, and transgenic eukaryotic cells and organisms containing such constructs.

The invention relates to genes coding for TCP family transcription factors and having a biological role in the development of axillary buds and branch growth. Furthermore, the invention relates to the promoters of the transcription of said genes, to the genetic constructs containing same and to the uses thereof, including the use of agents that modulate the expression of these genes in order to modify plant architecture.

The present invention relates to a composition useful for the diagnosis of diseases associated with aberrant expression of the genes encoding the secreted proteins Futrin 1, 2, 3 and/or 4(=R-Spondin 2, 3, 1 and 4, respectively), e.g. in connection with tumors or diseases of the muscle, kidneys or bones. The present invention also relates to a pharmaceutical composition containing a compound which is capable of modifying (a) the expression of the gene encoding Futrin 1, 2, 3 and/or 4 or (b) the activity of the Futrin 1, 2, 3 and/or 4 protein.