Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

A power conversion system may include a plurality of power devices and a sensor operably coupled to at least one of the plurality of power devices and configured to detect a voltage, current, or electromagnetic signature signal associated with the plurality of power devices. The power converter may also include circuitry operably coupled to the plurality of power devices and the sensor. The circuitry may send a respective gate signal to each respective power device of the plurality of power devices, such that each respective gate signal is delayed by a respective compensation delay that is determined for the respective power device based on a respective time delay of the respective power device and a maximum time delay of the plurality of power devices.

A device (442) for producing a dynamic reference signal (UREF) for a control circuit for a power semiconductor switch comprises a reference signal generator (442) for providing a dynamic reference signal (UREF), which has a stationary signal level after elapse of a predefined time following a switching process of the power semiconductor switch, a passive charging circuit (450) which is configured to increase a signal level of the dynamic reference signal in reaction to a switching of a control signal of the power semiconductor switch from an OFF state to ON state for at least one part of the predefined time above the stationary signal level, in order to produce the dynamic reference signal and an output (A) for tapping the dynamic reference signal (UREF).

A semiconductor apparatus may include a noise determination circuit, a strobe signal control circuit, and a reception circuit. The noise determination circuit may sense and determine noise of a reference voltage, and generate an up control signal and a down control signal. The strobe signal control circuit may adjust a transition timing of a strobe signal in response to the up control signal and the down control signal, and output a control strobe signal. The reception circuit may generate internal data signal in response to external data signal, the reference voltage, and the control strobe signal.

A connector hub assembly usable as a standalone module or as a component in a work space system. The connector hub assembly optionally includes features for connecting one or more arms of a support frame for supporting a modular workspace system including desk space, cabinet space, view screens, electronic equipment, and/or other workspace system components.

A ceiling mount intrusion detector with arbitrary direction detection capability is provided. The detector can include a pyroelectric sensor and a unitary Fresnel lens such that the unitary Fresnel lens includes a first piece of a first full Fresnel lens and a second piece of a second full Fresnel lens and such that the first piece and the second piece are spliced together. Due to the dimensions and location of the unitary Fresnel lens relative to the sensor, the sensor can output a signal indicative of an alarm condition when an object passes in front of the lens at any angle relative to the sensor.

The present invention relates to a combustion device 100 for burning refractory hazardous gases and a burning method for the combustion device. More particularly, the combustion device 110 for burning refractory hazardous gases, which is provided in a scrubber system 1 for burning waste gases, the combustion device 110 includes: a first porous body 141; a second porous body 142; and an igniter for forming a flame surface 143 at the interior of the combustion device 110, wherein the flame surface 143 formed by the igniter is located between the first porous body 141 and the second porous body 142, and so as to form the flame surface 143, at least one of the first porous body 141 and the second porous body 142 is moved to conduct excess enthalpy combustion.

A heat assisted magnetic recording (HAMR) write apparatus is described. The HAMR write apparatus is coupled with a laser that provides energy. The HAMR writer has a media-facing surface (MFS) and a laser-facing surface. The HAMR write apparatus includes a free-standing reflector and at least one waveguide. The free-standing reflector resides on the laser-facing surface and has a concave reflective surface oriented to receive the energy from the laser. The waveguide(s) are optically coupled with the free-standing reflector and direct energy from the laser toward the MFS.

An optical disk drive and a digital servo method for the optical disk drive includes controlling functions of the optical disk drive with a microprocessor. Low-pass filtered and gain adjusted versions of individual photodetector output signals resulting from an illumination of an optical disk are received. Versions of the individual photodetector output signals are digitized to produce digital signals. A focus control signal and/or a tracking control signal is determined through at least one servo algorithm executed by a digital signal processor based on a focus error and/or tracking error, respectively, determined from the digital signals. The digital signal processor is an integrated circuit structured and arranged for manipulation of digital signals in accordance with programmed commands, and in a manner that operates faster than the microprocessor.

The disclosure relates to microwave cavity plasma reactor (MCPR) apparatus and associated tuning and process control methods that enable the microwave plasma assisted chemical vapor deposition (MPACVD) of a component such as diamond. Related methods enable the control of the microwave discharge position, size and shape, and enable efficient matching of the incident microwave power into the reactor prior to and during component deposition. Pre-deposition tuning processes provide a well matched reactor exhibiting a high plasma reactor coupling efficiency over a wide range of operating conditions, thus allowing operational input parameters to be modified during deposition while simultaneously maintaining the reactor in a well-matched state. Additional processes are directed to realtime process control during deposition, in particular based on identified independent process variables which can effectively control desired dependent process variables during deposition while still maintaining a well-matched power coupling reactor state.

An improved organic photoconductor drum having a protective overcoat layer and method to make the same is provided. The protective overcoat layer is prepared from a curable composition including a crosslinkable hole transport molecule containing four radical polymerizable functional groups in combination with a crosslinkable acrylate having at least 6 functional groups.

The present invention is a reflector with a cylindrical shape which diffuses the finite point light sources in a linear array to present a substantially smooth bar of light to the viewer of the reflector.

A filter system and method use a filter housing that defines an interior chamber and that includes an inlet opening extending into the interior chamber. The outer air flow housing has an outlet conduit through which a flow of air having particles is directed toward the inlet opening of the filter housing along a flow direction toward the interior chamber of the filter housing. The outer air flow housing engages the filter housing such that the filter housing is separated from the outer air flow housing along the flow direction to permit at least some of the air to pass around an exterior of the filter housing and exit the outer air flow housing while the particles in the at least some of the air pass into the interior chamber of the filter housing through the inlet opening.

Disclosed herein is a system and method for condensing moisture in a gas stream entering or leaving a bioreactor, the system comprising: a contact condenser container fluidically coupled to the bioreactor through an exhaust line; a condensate accumulator fluidically coupled to the contact condenser container through at least a first condensate line and a second condensate line; the condensate accumulator further fluidically coupled to the bioreactor through a condensate overflow line; a first condensate control device disposed on the first condensate line and configured to control a flow of condensate leaving the contact condenser container and entering the condensate accumulator; and a second condensate control device disposed on the second condensate line and configured to control a flow of condensate leaving the condensate accumulator to be mixed with the gas stream.

A combination tractor and baler is provided to automate tractor stopping and baler wrapping while incorporating operator interaction to improve the efficiency of the tractor and baler combination in operation. Automated control systems and manual operator devices are utilized to improve the timing of the tractor stop and baler wrapping time sequences. Various methods to improve efficiency, including methods to synchronize tractor stop with wrapping activation are provided.

The present invention relates to a baler ejection system that may be used with an agricultural harvester, such as a round baler, waste baler, combine, or cotton harvester. More particularly, the bale ejection system uses the motion of two pairs of parallel arms that extend transversely from the sidewalls of a bale chamber at two sets of distinct pivot points. When activated by the operator of the bale ejection system, the two pairs of parallel arms raise simultaneously to expose an outlet through which the bale may be ejected. The bale ejection system is designed to allow a larger outlet for the bale evacuation as compared to existing bale ejection systems that employ circular motion to expose the bale outlet. A formed bale may become ejected by one or more conveyer belts that exert a rearward force on the bale within the bale chamber.

A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first prefabricated insulating film.

A method of making a semiconductor device can include providing a wafer comprising a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. A photosensitive layer can be formed over the wafer and on a backside of each of the plurality of semiconductor die within the wafer with a coating machine. An identifying mark can be formed within the photosensitive layer for each of the plurality of semiconductor die with a digital exposure machine and a developer, wherein a thickness of the identifying mark is less than or equal to 50 percent of a thickness of the photosensitive layer. The photosensitive layer can be cured. The wafer can be singulated into a plurality of semiconductor devices.

A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring.

A semiconductor mounting apparatus includes a storing unit that stores a liquid or a gas, a contact unit that comes into contact with a semiconductor chip when the storing unit is filled with the liquid or the gas, and a sucking unit that sucks up the semiconductor chip to bring the semiconductor chip into close contact with the contact unit.

A system for determining thickness variation values of a semiconductor substrate comprises a substrate vacuumed to a pedestal that defines a reference plane for measuring the substrate. A measurement probe assembly determines substrate CTV and BTV values, and defines a substrate slope angle. A thermal bonding assembly attaches a die to the substrate at a bonding angle congruent with the substrate slope angle. A plurality of substrates are measured using the same reference plane on the pedestal. Associated methods and processes are disclosed.

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; (b) ultrasonically forming tack bonds between ones of the first conductive structures and respective ones of the second conductive structures; and (c) forming completed bonds between the first conductive structures and the second conductive structures.

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.

Embodiments of the inventive concepts provide a method for manufacturing a semiconductor device. The method includes forming a stack structure including insulating layers and sacrificial layers which are alternately and repeatedly stacked on a substrate. A first photoresist pattern is formed on the stack structure. A first part of the stack structure is etched to form a stepwise structure using the first photoresist pattern as an etch mask. The first photoresist pattern includes a copolymer including a plurality of units represented by at least one of the following chemical formulas 1 to 3, wherein “R1”, “R2”, “R3”, “p”, “q” and “r” are the same as defined in the description.

A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.

A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.

Embodiments of the inventive concept provide a method for manufacturing a semiconductor device. The method includes forming a stack structure by alternately and repeatedly stacking insulating layers and sacrificial layers on a substrate, sequentially forming a first lower layer and a first photoresist pattern on the stack structure, etching the first lower layer using the first photoresist pattern as an etch mask to form a first lower pattern. A first part of the stack structure is etched to form a stepwise structure using the first lower pattern as an etch mask. The first lower layer includes a novolac-based organic polymer, and the first photoresist pattern includes a polymer including silicon.

A TFT and manufacturing method thereof, an array substrate and manufacturing method thereof, an X-ray detector and a display device are disclosed. The manufacturing method includes: forming a gate-insulating-layer thin film (3'), a semiconductor-layer thin film (4') and a passivation-shielding-layer thin film (5') successively; forming a pattern (5') that includes a passivation shielding layer through one patterning process, so that a portion, sheltered by the passivation shielding layer, of the semiconductor-layer thin film forms a pattern of an active layer (4a'); and performing an ion doping process to a portion, not sheltered by the passivation shielding layer, of the semiconductor-layer thin film to form a pattern comprising a source electrode (4c') and a drain electrode (4b'). The source electrode (4c') and the drain electrode (4b') are disposed on two sides of the active layer (4a') respectively and in a same layer as the active layer (4a'). The manufacturing method can reduce the number of patterning processes and improve the performance of the thin film transistor in the array substrate.

A method of forming a semiconductor device is provided such that a trench is formed in a semiconductor body at a first surface of the semiconductor body. Dopants are introduced into a first region at a bottom side of the trench by ion implantation. A filling material is formed in the trench. Dopants are introduced into a second region at a top side of the filling material. Thermal processing of the semiconductor body is carried out and is configured to intermix dopants from the first and the second regions by a diffusion process along a vertical direction perpendicular to the first surface.

A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor.

To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is formed on a semiconductor substrate so as to cover a gate electrode and a sidewall spacer. After heat treatment, a second insulating film is formed on the first insulating film and a resist pattern is formed on the second insulating film. Then, these insulating films are etched with the resist pattern as an etching mask. The resist pattern is removed, followed by wet washing treatment. A metal silicide layer is then formed by the salicide process.

A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.

The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.

A method of production of a semiconductor device comprising a semiconductor layer forming step of forming a semiconductor layer including an inorganic oxide semiconductor on a board, a passivation film forming step of forming a passivation film comprising an organic material so as to cover the semiconductor layer, a baking step of baking the passivation film, and a cooling step of cooling the passivation film after baking, herein, in the cooling step, a cooling speed from a baking temperature at the time of baking in the baking step to a temperature 50° C. lower than the baking temperature is substantially controlled to 0.5 to 5° C./min in range is provided.

A method is provided for making smooth crystalline semiconductor thin-films and hole and electron transport films for solar cells and other electronic devices. Such semiconductor films have an average roughness of 3.4 nm thus allowing for effective deposition of additional semiconductor film layers such as perovskites for tandem solar cell structures which require extremely smooth surfaces for high quality device fabrication.

One embodiment is a wide stripe semiconductor waveguide, which is cleaved at a Talbot length thereof, the wide stripe semiconductor waveguide having facets with mirror coatings. A system provides for selective pumping the wide stripe semiconductor waveguide to create and support a Talbot mode. In embodiments according to the present method and apparatus the gain is patterned so that a single unique pattern actually has the highest gain and hence it is the distribution that oscillates.

The present disclosure relates to an apparatus for fastening a power semiconductor using an integral springy (elastic) clip, capable of fixing a power semiconductor, such as a diode and a MOSFET, using elasticity of a U-shaped clip by integrally molding the clip onto a housing of a plastic module. The apparatus includes an elastic (springy) clip integrally molded onto a lower surface of the housing and downwardly curved into a U-like shape in a bridge module in which a bridge of the power semiconductor protrudes through a through hole of the housing to be connected to a printed circuit board, whereby the power semiconductor is fixed by a force that the housing presses the power semiconductor.

In one example, a connector includes: first and second pins protruding from opposite sides of a panel or a frame; first and second receivers on opposite sides of the other of the panel or the frame to receive the first and second pins; a first distance between the receivers shorter than a second distance between the protruding ends of the pins such that the first pin may be inserted into the first receiver and then the second pin inserted into the second receiver but both pins may not be inserted simultaneously into the receivers; and a movable retainer integral to the panel and the frame to retain the pins in the receivers. The retainer is movable between a first position to limit axial travel of the pins in the receivers and a second position to not limit axial travel of the pins in the receivers.

A portable electronic device includes a lower housing and an upper housing slidable relative to the lower housing between closed and open positions. The upper housing includes an auxiliary input device and a display. A primary flex connector electrically connects the lower and upper housings. At least one secondary flex connector may electrically connect the primary flex connector to the auxiliary input device or the display. The upper housing may include a cover plate that is removable to allow access to at least a portion of the flex connectors.

A detector with a telescopic carrier/guide rod at which a measuring probe is disposed at one end, wherein the carrier/guide rod features at least two tubes longitudinally movable inside one another, in which respectively two tubes disposed adjacently in radial direction form an outer tube and an inner tube, whereby the respective outer tube at its overlapping tube end facing the measuring probe features a clamping means for engaging the inner tube. In accordance with this invention, the clamping means is formed as a clamping device that features a profile clamp with a quick-locking device. The profile clamp comprises a holding ring with two half shell-shaped clamping ring segments that are interconnected flexibly on one side and on the opposite side they can be clamped together with a clamping lever. The holding ring features ring breakthroughs and the outer tube the corresponding tube breakthroughs for the accommodation of clamping pieces that are pressed against the inner tube when clamping the clamping ring segments together under pressure. Preferably a clamping ring segment is formed on the holding ring.

Various processes and apparatus are discussed for an ultra-high heat flux chemical reactor. A thermal receiver and the reactor tubes are aligned to 1) absorb and re-emit radiant energy, 2) highly reflect radiant energy, and 3) any combination of these, to maintain an operational temperature of the enclosed ultra-high heat flux chemical reactor. Particles of biomass are gasified in the presence of a steam carrier gas and methane in a simultaneous steam reformation and steam biomass gasification reaction to produce reaction products that include hydrogen and carbon monoxide gas using the ultra-high heat flux thermal energy radiated from the inner wall and then into the multiple reactor tubes. The multiple reactor tubes and cavity walls of the receiver transfer energy primarily by radiation absorption and re-radiation, rather than by convection or conduction, to the reactants in the chemical reaction to drive the endothermic chemical reaction flowing in the reactor tubes.

An electrical connector has two portions, a first portion connectable to a device and a second portion having a contact point which is movable in relation to the first portion. The second portion having the contact point comprises a magnet configured to attract the corresponding connector. The contact point does not require a counteracting force, whereby the side magnets may be smaller or the connector may lack the side magnets entirely.

Disclosed are electronic devices and connectors, including: a first main body, a second main body; the first magnet being arranged at a first end of the first main body and the second magnet being arranged at a second end of the second main body; the first magnet having a magnetic property opposite that of the second magnet; the first main body being pluggably connected to the second main body through the interaction between the first magnet and the second magnet; the first number of spacers is arranged at a preset position of the first magnet, and the first number of spacers is arranged at a preset positions of the second magnet; and the spacers are non-magnetic. Other embodiments, including manufacturing methods, are described and claimed.

Connector latch used to securely hold together a connector apparatus, such that the connector apparatus has at least a first connector assembly and a second connector assembly which can be mated together. Initially, after the connector latch is manufactured, the connector latch is in an undeflected position. After manufacture, the connector latch is subjected to a pre-mating deflection process, in order to move the connector latch into a preloaded position. After the pre-mating deflection process has been completed, the connector latch is locked in the preloaded position. The preloaded connector latch provides a number of desirable characteristics, including at least an extra loud “click” sound when the first connector assembly and the second connector assembly are mated together.

A connector includes a connector main member and an operation member. The operation member covers the connector main member at least in part in a plane perpendicular to a front-rear direction, The operation member is movable between a front limitation position and a rear limitation position. The operation member has, therein, a front regulating portion accommodation portion accommodating the front regulating portion, and an operated portion accommodation portion accommodating the operated portion. The front regulating portion accommodation portion is provided, therein, with a front regulated portion which is brought into abutment with the front regulating portion when the operation member is positioned at the front limitation position. When the operation member is moved to the rear limitation position, the operated portion accommodation portion is provided, therein, with an operating portion which presses the operated portion inward of the connector main portion and moves the lock portion to a released position.

In one example an electronic device comprises at least one electronic component, a chassis comprising a first section, a connector to connect the first section of the chassis to a second section, the connector comprising a housing defining a first shaft, a retention structure disposed in the shaft, and a plurality of electrical contacts positioned within a corresponding plurality of channels in the retention structure. Other examples may be described.