A solar collector (26) includes: an outer tube (64) of circular cross-section, closed at one of its ends, an absorption layer (52) arranged inside the outer tube (64), for absorbing solar radiation (Rs), and a heat pipe (56) including a hot part (58) laid out inside the outer tube (64), a cold part (60) arranged outside the outer tube (64), and a reservoir (62) containing a heat pipe fluid (63) and extending over the hot part (58) and the cold part (60). The outer tube (64) is hermetically closed around the heat pipe (56) at the other of its ends, a vacuum being formed inside said outer tube (64). For the hot part (58) of the heat pipe (56), the reservoir (62) is applied at least locally against the absorption layer (52).

A radial-flow plate heat exchanger (5) embedded in the catalytic bed of an isothermal chemical reactor (1) has heat exchange plates (10) comprising fluid passages (13) between a first metal sheet (20) and a second metal sheet (21) joined by perimeter weld seams (23) on a first surface (A) of the plate, a feeding channel (14) and a collecting channel (15) for the heat exchange fluid are formed with suitable metal sheets which are seam welded (25) directly to the opposite surface (B) of the plate, this structure allows the manufacturing of the plate (10) with an automated seam welding process, such as laser beam welding.

A semiconductor substrate for use in an integrated circuit, the semiconductor substrate including a channel defined on a surface of the substrate. The channel includes a first wall, a second wall, and a third wall. The first wall is recessed from the surface. The second wall extends from the surface to the first wall. The third wall extends from the surface to the first wall and faces the second wall across the channel. At least one of the second wall and the third wall includes a plurality of structures projecting into the channel from the second wall or the third wall.

A process for producing refractory metal alloy powders includes the steps of blending at least one powder with at least one solvent and at least one binder to form a slurry; forming a plurality of agglomerates from the slurry; screening the plurality of agglomerates; sintering the plurality of agglomerates; and melting said plurality of agglomerates to form a plurality of homogenous, densified powder particles.

A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si4+ or Ge4+ oxidation state of the surface of the Si or Ge substrate, respectively, resulting from the presence of the oxygen monolayer represents less than 50%, preferably less than 40% and more preferably less than 30% of the sum of Si1+, Si2+, Si3+ and Si4+ oxidation states or the sum of Ge1+, Ge2+, Ge3+ and Ge4+ oxidation states, respectively, as measured by XPS.

A method for slicing a plurality of wafers from a crystal includes providing a crystal of semiconductor material having a longitudinal axis, a cross section and at least one pulling edge. The crystal is fixed on a table and guided through a wire gang defined by sawing wire so as to form the wafers. The guiding is provided by a relative movement between the table and the wire gang such that entry sawing or exit sawing using the sawing wire occurs in a vicinity of the at least one pulling edge of the crystal.

A method for cooling a cylindrical workpiece during wire sawing includes applying a liquid coolant to a surface of the workpiece. The workpiece is made of semiconductor material having a surface including two end faces and a lateral face. The method includes sawing the workpiece with a wire saw including a wire web having wire sections arranged in parallel by penetrating the wire sections into the workpiece by an oppositely directed relative movement of the wire sections and the workpiece. Wipers are disposed so as to bear on the surface of the workpiece. The temperature of the workpiece is controlled during the wire sawing using a liquid coolant applied onto the workpiece above the wipers so as to remove the liquid coolant with the wipers bearing on the workpiece surface.

The present disclosure is directed to a refractory metal core for use in forming varying thickness microcircuits in turbine engine components, a process for forming the refractory metal core, and a process for forming the turbine engine components. The refractory metal core is used in the casting of a turbine engine component. The core is formed by a sheet of refractory metal material having a curved trailing edge portion integrally formed with a leading edge portion.

A device for processing a hydrocarbon resource may include a hydrocarbon processing container configured to receive the hydrocarbon resource therein and having a pair of opposing ends with an enlarged width medial portion therebetween. The device may also include a radio frequency (RF) source, and a first spirally wound electrical conductor surrounding the hydrocarbon processing container and coupled to the RF source. The device may further include a second spirally wound electrical conductor carried within the hydrocarbon processing container. The first spirally wound electrical conductor may be configured to generate magnetic fields with the hydrocarbon processing container that are parallel with an axis thereof.

A device for processing a hydrocarbon resource may include a hydrocarbon processing container configured to receive the hydrocarbon resource therein and having a pair of opposing ends with an enlarged width medial portion therebetween. The device may also include a radio frequency (RF) source, and a spirally wound electrical conductor surrounding the hydrocarbon processing container and coupled to the RF source. The spirally wound electrical conductor may be configured to generate magnetic fields within the hydrocarbon processing container that are parallel with an axis thereof.

Variant factor H binding proteins that can elicit antibodies that are bactericidal for at least one strain of Neisseria meningitidis, compositions comprising such proteins, and methods of use of such proteins, are provided.

A hybrid plasma reactor includes a reactor body having a plasma discharge space, a gas inlet, and a gas outlet; a hybrid plasma source including an inductive antenna inductively coupled to plasma formed in the plasma discharge space and a primary winding coil transformer coupled to the plasma and wound in a magnetic core; and an alternating switching power supply for supplying plasma generation power to the inductive antenna and the primary winding coil. The hybrid plasma reactor induces a plasma discharge using the inductively coupled plasma source and the transformer coupled plasma source, so that it has a wide operational area from a low pressure area to a high pressure area.

Positioning system of sectors of a device for producing an airplane fuselage in which a lamination mandrel comprises a plurality of sectors borne by a supporting structure and mobile along guides between: an expanded lamination position and a contracted disassembling position. Each guide comprises a fixed part borne by the supporting structure and a mobile part sliding along/with respect to the fixed part in a rectilinear direction H. Between a portion of each mobile part facing towards the respective sector and a stiffening structure of the sector a positioning device is provided which allows adjustment of the position of the sector with respect to the guide in two directions which lie in a plane RP perpendicular to the axis H of the guide.

A constraint system of sectors of a device for producing an airplane fuselage in which a lamination mandrel is adapted to receive and support a band of impregnated synthetic material. The lamination mandrel comprises a plurality of sectors angularly spaced about the axis and mobile between: an expanded lamination position and a contracted disassembling position. A constraint system is provided between each sector and the sectors adjacent thereto which guarantees a predetermined arrangement of the first sector with respect to the second sector adjacent thereto, preventing any translation along two directions which lie in an adjustment plane perpendicular to an axis RD which extends radially from the symmetry axis to the external surface.

A method for detaching a semiconductor chip from a foil uses a die ejector comprising plates having a straight supporting edge and an L-shaped supporting edge comprises: lifting of the plates to a height H1 above the surface of a cover plate;lowering of a first pair of plates with L-shaped supporting edge;optionally, lowering of a second pair of plates with L-shaped supporting edge;lifting of the plates that have not yet been lowered to a height H2>H1;staggered lowering of plates that have not yet been lowered, with at least one or several plates not being lowered;optionally, lowering of the plates that have not yet been lowered to a height H3

There is provided an inductively coupled plasma reactor. The inductively coupled plasma reactor is connected to a transformer with multiple magnetic cores and a primary winding, to transfer an electromotive force for plasma discharge to a plasma discharge chamber of a reactor body. Parts of magnetic core positioned in side the plasma discharge chamber are protected by being entirely covered by a core protecting tube. The primary winding is electrically connected to a power supply source providing radio frequency power. In the inductively coupled plasma reactor, since a number of magnetic core cross sectional parts are positioned inside the plasma discharge chamber, the efficiency of transferring the inductively coupled energy to be connected with plasma is very high.

A method for finding an evasive trajectory for avoiding an obstacle for a vehicle on a roadway. A component of a candidate trajectory parallel to the roadway is determined by selecting weighting coefficients of a first weighted sum of orthogonal functions of time. A component of the candidate trajectory orthogonal to the roadway is determined by selecting weighting coefficients of a second weighted sum of the orthogonal functions. An optimization parameter for the candidate trajectory is calculated. At least one coefficient of at least one of the sums is modified and the procedure is repeated when the optimization parameter does not reach a termination criterion.

A pumping unit system having vertical sampson post, a walking beam pivotally supported at the upper end of the sampson post and a horsehead affixed at a forward end thereof that supports a reciprocated sucker rod string, including a gear reducer mounted at selectable positions on the walking beam and having a horizontally extending drive shaft, a crank arm affixed to the drive shaft the spacing between a selectable length pitman rod having a first end secured to said crank arm and a second end having a pitman bearing that is selectably mountable to a plurality of pitman bearing locations and a prime mover connected to the gear reducer and wherein the characteristics of the pumping unit are determined by the selectable position of the gear reducer, the selectable length of the crank arm, the selectable length of the pitman rod, and the selectable pitman bearing location.

A case for a portable electronic device such as cell phones, cameras, MP3 players and PDAs wherein said case includes material at the corners to provide protection to the electronic device. To reduce bulk at the corners and allow the material forming the case to conform with the contours of the device, the protection at the corners includes strips of material defining apertures there between. The apertures provide reduction in bulk and allow the case to conform to the corners of the device therein. Alternately, the protection at the corners can be provided by other structures co-molded into the corners of the cases. Such structures include material that is of a reduced thickness than other material used in the case, or structures that are formed to conform to the corners of the case. Such structures can be joined to the material forming the panels of the case by co-molding.

A mooring system, and connector assembly, which in a preferred embodiment is a vessel mooring and fluid transfer system. The connector assembly has a first portion (2A) configured to be coupled to one or more mooring lines (1), and a second portion (2B) configured to be coupled to a vessel. The first and second portions are rotatable with respect to one another to permit a vessel coupling on the second portion to swivel about the mooring coupling on the first portion. In a preferred embodiment, the connector assembly comprises a guide (2E) for a conduit, which may be a fluid transfer conduit such as flexible riser (6). The invention also provides methods of use of the mooring systems described.

Described herein are methods for training a machine learning-based predictor of affective response to stimuli. The methods involve receiving samples comprising temporal windows of token instances to which a user was exposed, and target values representing affective response annotations of the user in response to the temporal windows of token instances. This data is used for the training of the predictor along with values indicative of the number of the token instances in the temporal windows of token instances, which are used to compensate for non-linear effects resulting from saturation of the user.

Forming a sector for a nacelle lip skin from a sheet metal blank via punch by placing the blank against an outer surface of the punch and clamping a trailing edge of the blank in a clamping member that grips a trailing edge of the blank without slippage; gripping a leading edge of the blank, opposite the trailing edge, in a gripping device at a location axially spaced from the punch with sufficient force to permit the blank to flow therethrough in a controlled manner; displacing the gripping device in a first direction, radially with respect to the punch while drawing the blank through the gripper; displacing the gripping device in a second direction, axially with respect to the punch, to draw the blank over the leading edge of the punch and through the gripping device.

A low power consumption semiconductor device is provided. The semiconductor device includes a decoder, a signal generation circuit, and a display device. The decoder includes an analysis circuit and an arithmetic circuit. The analysis circuit has a function of determining whether to decode the received first image data using the received data. The signal generation circuit has a function of generating a signal including an instruction on whether to decode the first image data in response to the determination of the analysis circuit. The arithmetic circuit has a function of decoding the first image data in response to the signal. The display device has a function of maintaining a second image displayed on the display device in the case where the first image data is not decoded in the arithmetic circuit.

A semiconductor device includes first to fourth terminals, a switch circuit, and an integrating circuit. The integrating circuit includes an amplifier circuit having a (−) terminal, a first (+) terminal, and a second (+) terminal. The integrating circuit is configured to integrate an input signal of the (−) terminal using an average voltage of a voltage of the first (+) terminal and a voltage of the second (+) terminal as a reference voltage. The switch circuit is configured to electrically connect the (−) terminal to the second terminal, the first (+) terminal to the first terminal, the second (+) terminal to the third terminal the (−) terminal to the third terminal, the first (+) terminal to the second terminal, and the second (+) terminal to the fourth terminal. The present semiconductor device is used as a semiconductor device sensing a current flowing through a pixel in a display panel.

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.

The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

According to one embodiment, a semiconductor storage apparatus includes a memory cell array and a read circuit. The memory cell array includes a memory cell which is connected to a word line. A threshold voltage of the memory cell corresponds to a data value of multiple bits. The read circuit receives designation of one bit among the multiple bits, applies a first reading voltage and a second reading voltage corresponding to the designated bit to the word line, senses ON or OFF of the memory cell for each reading voltage, and outputs a first sensed value and a second sensed value after performing the sensing for each reading voltage. The first sensed value is a sensing result in a case where the first reading voltage is applied. The second sensed value is a sensing result in a case where the second reading voltage is applied.

A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line.

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.

According to one embodiment, a semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The input/output (I/O) drive controller generates drive control signals and an input control signal for driving first and second global I/O lines in a first test mode or a second test mode. The data I/O unit drives the first global I/O line in response to an input data when a write operation is executed in the first test mode and to drive the first and second global I/O lines in response to the drive control signals when the write operation is executed in the second test mode. The data transmitter transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line in a memory cell array portion when the write operation is executed in the first test mode. The data transmitter also transfers the data on the first and second global I/O lines onto the first and second local I/O lines to store the data on the first and second global I/O lines in the memory cell array portion when the write operation is executed in the second test mode. Related methods are also provided.

Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

A method for fabricating a semiconductor device and a method for operating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming a first electrode layer; forming a material layer, including conductive path components, over the first electrode layer; forming a second electrode layer over the material layer; performing a forming operation, which includes initially creating, in the material layer, a conductive path that electrically connects the first electrode layer to the second electrode layer by applying one of a predetermined voltage and a predetermined current between the first and second electrode layers, the conductive path including the conductive path components; and performing a first heat-treatment process at a predetermined temperature that removes some of the conductive path components from the conductive path, wherein a resistance state of the material layer changes based on the creation or dissolution of the conductive paths.

A first wireless device may determine a bandwidth for transmitting a frame, calculate two or more Spatial Reuse (SR) parameter values for the bandwidth, set, using the SR parameter values, first and second SR fields of the frame based on the bandwidth and a channel center frequency in which the bandwidth is carried, and transmit the frame to a second wireless device on the bandwidth. The first and second SR fields may be set to a first value when the bandwidth is a 40 MHz bandwidth and the channel center frequency is in a 2.4 GHz band. The first and second SR fields may be set to the first value when the bandwidth is an 80+80 MHz bandwidth and the channel center frequency is in a 5 GHz band. The first value may be a minimum of SR parameter values for first and second bandwidths in the bandwidth.

A spring steel slip sheet for a compactor and for extending into a compression zone defined by a feed roll and a retard roll for shrinking a fabric. The slip sheet is for the compactor, extends into the compression zone defined by the feed roll and the retard roll for shrinking the fabric, and is made of spring steel. The slip sheet is sheet-like and includes a mounting portion and a compressing portion. The compressing portion extends from the mounting portion at an interface line. The mounting portion usually is flat and the compressing portion usually is arcuate. The compressing portion curves similarly as the feed roll of the compactor does, and presses the fabric against the feed roll of the compactor as the fabric enters the compression zone of the compactor.

The arrangement of driven gears on a countershaft in a main speed change mechanism is shortened in an axial direction, whereby the main speed change mechanism can be made compact in the axial direction. Driven gears on a countershaft of a main speed change mechanism are successively arranged from front to rear in descending order of speed. A sub-low-speed drive gear for a sub-speed change mechanism is provided in front of the highest-speed driven gear on the countershaft, and the next-highest-speed driven gear serves as a sub-high-speed drive gear for the sub-speed change mechanism. A sub-low-speed driven gear and a sub-high-speed driven gear for the sub-speed change mechanism are provided on an output shaft to be engaged with the sub-low-speed drive gear and the next-highest-speed driven gear, respectively, and the highest-speed driven gear, the sub-low-speed drive gear, and the next-highest-speed driven gear are caused to overlap in a fore-and-aft direction.

The present disclosure relates to various shift selector assemblies having a shift gate with a plurality of indentations corresponding to transmission shift selections. At least one of the indentations is configured to have a flexible depth so as to selectively restrict and accept a pawl pin, thereby mitigating shift position overshoot.

A tractor includes a prime mover, a driven implement selectively engaged with the prime mover, and a switch for selectively engaging and disengaging the driven implement with the prime mover. The switch has three positions including a disengaged position, a momentary position, and an engaged position located between the disengaged position and the momentary position. The prime mover can be started with the switch in the disengaged position. The prime mover can be started with the switch in the engaged position when the switch was previously moved to the momentary position before being moved to the engaged position, such that after operation of the prime mover is stopped, the prime mover can be restarted without changing the position of the switch.

The present disclosure relates to a connector using a ball and a detent and, more particularly, to a connector in a clutch connection structure used in an electrical automobile, which includes: a locking part formed at a body; a latch in contact with the locking part; a first solenoid driving part disposed on one side of the latch; and a second solenoid driving part disposed on the other side of the latch, in which the first solenoid driving part and the second solenoid driving part face each other with the latch being interposed therebetween, such that an operation of a clutch when the clutch operates becomes simple, and thus, noise, vibrations, and durability thereof are improved.

A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.

A control switch is connected to a power supply voltage and turns on based on a control signal to output a current. A clamp circuit is connected to a load and performs clamp control of the output voltage of the control switch. A current control element conducts or shuts off a current based on the output voltage to be clamp-controlled. A selector switch group includes switches, and performs switching based on a voltage varying with the current control by the current control element, thereby switching between paths for generating an internal power supply. The switch circuit connects or disconnects the coupling between the clamp circuit and the selector switch group.

A semiconductor device includes a first transistor and a clamping circuit. The first transistor is arranged to generate an output signal according to a control signal. The clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level.

An integrated circuit includes a drive circuit with a first inverter circuit with a first transistor of a first conductivity type and a second transistor of a second conductivity type. The drains of the first and second transistors are connected. An output circuit is provided having a third transistor of the second conductivity with a gate connected to the drains of the first and second transistors. A capacitor is connected between the gate and a drain of the third transistor and has a capacitance greater than 0.5 pF and less than or equal to 3.0 pF. A gate width of the first transistor when divided by a gate width of the third transistor has a value of less than 1/100. The output circuit is configured to output a transmission signal from the drain of the third transistor.