The ASUS ROG Phone 9 has recently been spotted on Geekbench where it appears to be powered by the new Qualcomm chipset.

The post ASUS ROG Phone 9 spotted on Geekbench with Qualcomm’s latest chipset appeared first on Phandroid.

In a unique online romance scam, a man in Tianjin, China, fell victim to a bizarre "marriage bed burning" ritual, costing him Rs 11 lakh.

The video features models dressed in the latest fashion, strutting like mannequins on a moving runway outside the designer store ITIB.

Children's Day, also known as 'Bal Diwas', is celebrated annually on November 14 in India. The day is celebrated to appreciate and acknowledge children as they are the future of the county.

By celebrating Children's Day as Bal Diwas, India reinforced the cultural and emotional significance of the day, making it a uniquely Indian celebration rooted in national pride and values.

Microsoft announced it has acquired Semantic Machines, a conversational AI startup providing chatbots and AI chat apps founded in 2014 having $20.9 million in funding from investors. The acquisition will help Microsoft catch up with Amazon Alexa, though the latter is more focused on enabling consumer applications of conversational AI.

Microsoft will use Semantic Machine’s acquisition to establish a conversational AI center of excellence in Berkeley to help it innovate in natural language interfaces.

Microsoft has been stepping up its products in conversational AI. It launched the digital assistant Cortana in 2015, as well as social chatbots like XiaoIce. The latest acquisition can help Microsoft beef up its ‘enterprise AI’ offerings.

As the use of NLP (natural language processing) increases in IoT products and services, more startups are getting traction from investors and established players. In June last year, Josh.ai, avoice-controlled home automation software has raised $8M.

Followed by it was SparkCognition that raised $32.5M Series B for its NLP-based threat intelligence platform.

It appears Microsoft’s acquisition of Semantic Machines was motivated by the latter’s strong AI team. The team includes technology entrepreneur Daniel Roth who sold his previous startups Voice Signal Technologies and Shaser BioScience for $300M and $100M respectively. Other team members include Stanford AI Professor Percy Liang, developer of Google Assistant Core AI technology and former Apple chief speech scientist Larry Gillick.

In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive sector. However, the transition to working with chiplets in automotive electronics is not without its challenges.

Designers must now grapple with a new set of considerations, such as die-to-die interconnect standards, complex processes, and the integration of diverse IPs. Advanced toolsets and standardized design approaches are required to meet these challenges head-on and elevate the potential of chiplets in automotive innovation. In the following discourse, we will explore in detail the significance of chiplets in the context of automotive electronics, the obstacles designers face when working with this paradigm, and how Cadence comprehensive suite of IPs, tools, and flows is pioneering solutions to streamline the chiplet design process.

Unveiling Chiplets in Automotive Electronics

For automotive electronics, chiplets offer a methodology to modularize complex functionalities, integrate different chiplets into a package, and significantly enhance scalability and manufacturability. By breaking down semiconductor designs into a collection of chiplets, each fulfilling specific functions, automotive manufacturers can mix and match chiplets to rapidly prototype new designs, update existing ones, and specialize for the myriad of use cases found in vehicles today.

The increasing significance of chiplets in automotive electronics comes as a response to several industry-impacting phenomena. The most obvious among these is the physical restriction of Moore's Law, as large die sizes lead to poor yields and escalating production costs. Chiplets with localized process specialization can offer superior functionality at a more digestible cost, maintaining a growth trajectory where monolithic designs cannot. Furthermore, chiplets support the assembly of disparate technologies onto a single subsystem, providing a comprehensive yet adaptive solution to the diverse demands present in modern vehicles, such as central computing units, advanced driver-assistance systems (ADAS), infotainment units, and in-vehicle networks. This chiplet-based approach to functional integration in automotive electronics necessitates intricate design, optimization, and validation strategies across multiple domains.

The Complexity Within Chiplets

Yet, with the promise of chiplets comes a series of intricate design challenges. Chiplets necessitate working across multiple substrates and technologies, rendering the once-familiar 2-dimensional design space into the complex reality of multi-layered, sometimes even three-dimensional domains. The intricacies embedded within this design modality mandate devoting considerable attention to partitioning trade-offs, signal integrity across multiple substrates, thermal behavior of stacked dies, and the emergence of new assembly design kits to complement process design kits (PDKs).

To effectively address these complexities, designers must wield sophisticated tools that facilitate co-design, co-analysis, and the creation of a robust virtual platform for architectural exploration. Standardizations like the Universal Chip Interconnect Express (UCIe) have been influential, providing a die-to-die interconnect foundation for chiplets that is both standardized and automotive-ready. The availability of UCIe PHY and controller IP from Cadence and other leading developers further eases the integration of chiplets in automotive designs.

The Role of Foundries and Packaging in Chiplets

Foundries have also pivoted their services to become a vital part of the chiplet process, providing specialized design kits that cater to the unique requirements of chiplets. In tandem, packaging has morphed from being a mere logistical afterthought to a value-added aspect of chiplets. Organizations now look to packaging to deliver enhanced performance, reduced power consumption, and the integrity required by the diverse range of technologies encompassed in a single chip or package. This shift requires advanced multiscale design and analysis strategies that resonate across a spectrum of design domains.

Tooling Up for Chiplets with Cadence

Cadence exemplifies the rise of comprehensive tooling and workflows to facilitate chiplet-based automotive electronics design. Their integrations address the challenges that chiplet-based SoCs present, ensuring a seamless design process from the initial concept to production. The Cadence suite of tools is tailored to work across design domains, ensuring coherence and efficiency at every step of the chiplet integration process.

For instance, Cadence Virtuoso RF subflows have become critical in navigating radio frequency (RF) challenges within the chiplets, while tools such as the Integrity 3D-IC Platform and the Allegro Advanced Multi-Die Package Design Solution have surfaced to enable comprehensive multi-die package designs. The Integrity Signal Planner extends its capabilities into the chiplet ecosystem, providing a centralized platform where system-wide signal integrity can be proactively managed. Sigrity and Celsius, on the other hand, offer universally applicable solutions that take on the challenges of chiplets in signal integrity and thermal considerations, irrespective of the design domain. Each of these integrated analysis solutions underscores the intricate symphony between technology, design, and packaging essential in unlocking the potential of chiplets for automotive electronics.

Cadence portfolio includes solutions for system analysis, optimization, and signoff to complement these domain-specific tools, ensuring that the challenges of chiplet designs don't halt progress toward innovative automotive electronics. Cadence enables designers to engage in power- and thermal-aware design practices through their toolset, a necessity as automotive systems become increasingly sophisticated and power-efficient.

A Standardized Approach to Success with Chiplets

Cadence’s support for UCIe underscores the criticality of standardized approaches for heterogeneous integration by conforming to UCIe standards, which numerous industry stakeholders back. By co-chairing the UCIe Automotive working group, Cadence ensures that automotive designs have a universal and standardized Die-to-Die (D2D) high-speed interface through which chiplets can intercommunicate, unleashing the true potential of modular design.

Furthermore, Cadence champions the utilization of virtual platforms by providing transaction-level models (TLMs) for their UCIe D2D IP to simulate the interaction between chiplets at a higher level of abstraction. Moreover, individual chiplets can be simulated within a chiplet-based SoC context leveraging virtual platforms. Utilizing UVM or SCE-MI methodologies, TLMs, and virtual platforms serve as first lines of defense in identifying and addressing issues early in the design process before physical silicon even enters the picture.

Navigating With the Right Tools

The road to chiplet-driven automotive electronics is one paved with complexity, but with a commitment to standards, it is a path that promises significant rewards. By leveraging Cadence UCIe Design and Verification IP, tools, and methodologies, automotive designers are empowered to chart a course toward chiplets and help to establish a chiplet ecosystem. With challenges ranging from die-to-die interconnect to standardization, heterogeneous integration, and advanced packaging, the need for a seamless integrated flow and highly automated design approaches has never been more apparent. Companies like Cadence are tackling these challenges, providing the key technology for automotive designers seeking to utilize chiplets for the next-generation E/E architecture of vehicular technology.

In summary, chiplets have the potential to revolutionize the automotive electronics industry, breathing new life into the way vehicles are designed, manufactured, and operated. By understanding the significance of chiplets and addressing the challenges they present, automotive electronics is poised for a paradigm shift—one that combines the art of human ingenuity with the power of modular and scalable microchips to shape a future that is not only efficient but truly intelligent.

Learn more about how Cadence can help to enable automakers and OEMs with various aspects of automotive design.

We are currently setting up the Tempus flow and have ran into some mismatched data regarding ECO and timing reports. I generated a timing report before running ECO and saw six total setup violations. When running opt_signoff -setup, the initial setup summary that was printed in the shell only showed one violation. I can see that violation from the initial setup summary in my pre-ECO timing report and it is not the worst path. Upon further investigation, I forced the tool to try to fix setup on one of the other five violations from the timing report using the opt_signoff_select_setup_endpoints attribute and the tool said that the endpoint had positive slack and would be ignored.

Has anyone experienced something like this before?

I'm trying to do what I believe should be a very simple and straightforward thing but after much reading appears to be quite complicated.

I'm test-benching the digital portion of a mixed-signal circuit that's instantiated a few hundred times. Each instance has some digital controls, and an analog portion. To greatly speed up the simulation, I'd like to hide the analog portion, which is neatly contained in one or two cell views deep down the hierarchy, and then unhide it after simulation has ended so it doesn't mess up other peoples' sims

Just as an example, say there's an op-amp that from the top level is contained in instance "I<0:511>/I3/I15/I0". First off, I don't know how to iterate through the 512 instantiations of the top level cell, but let's say we're just working with the I0 instance. I thought it would just be

schIgnore(?objectId "I<0:511>/I3/I15/I0" ?setIgnore t)

Of course this doesn't work. I can get the top level cell dbId with

cv = dbOpenCellViewByType("library" "cell" "schematic" "" "a")

And then I can grab the instance ID with

inst = dbFindAnyInstByName(cv "I0")

This gives me something, but then I'm lost from here. If I use the ~>master to get an Id from inst, I cannot recursively use dbFindAnyInstByName to traverse down the hierarchy. Also the value this returned seems to be meaningless, it can't be used by the schIgnore command. I'm not sure what the schIgnore command is actually even looking for.

So I guess I'm trying to loop through two things, one is to traverse down the hierarchy and grab the ID of a child instance so I can schIgnore it, and another is to iterate through all the top level instances to hide the child instance within each of them.

Hi,

I have a string "[@global_vddi:%:vddi!]" which I need to process to remove "@[]" chars. The desired result is "global_vddi:%:vddi!". I tried the following in CIW

netExpr = "[@global_vddi:%:vddi!]"
rexCompile("\([a-zA-Z0-9_:!%]+\)")
t
rexExecute(netExpr)
t
rexSubstitute( "\0" )
"global_vddi:%:vddi!"

and I achieved the desired value. I added the same code to my script but it didn't work. In my script rexExecute returns 't' but rexSubstitute returns 'nil' 

Here is the snippet from my script

netExpr = dbGetTermNetExpr(term)
if(netExpr then
rexCompile("\([a-zA-Z0-9_:!%]+\)")
rexExecute(netExpr)
netExpr1 = rexSubstitute( "\0" )

...

. ..)  and trace log showing the variable values as the code executes

stopped before evaluating dbGetTermNetExpr(term)
after evaluating dbGetTermNetExpr(term)==> "[@global_vddi:%:vddi!]"
after evaluating (netExpr = dbGetTermNetExpr(term))==> "[@global_vddi:%:vddi!]"
stopped before evaluating if(netExpr then rexCompile("\([a-zA-Z0-9_:!%]+\)") rexExecute(netExpr) (netExpr1 = rexSubstitute("\0")) ... )
stopped before evaluating rexCompile("\([a-zA-Z0-9_:!%]+\)")
after evaluating rexCompile("\([a-zA-Z0-9_:!%]+\)")==> t
stopped before evaluating rexExecute(netExpr)
after evaluating rexExecute(netExpr)==> t
stopped before evaluating (netExpr1 = rexSubstitute("\0"))
stopped before evaluating rexSubstitute("\0")
after evaluating rexSubstitute("\0")==> nil
|[2]netExpr1 set to nil, was nil

Any help or suggestions as to why the code executes differently in CIW and when called from a SKILL script file will be much appreciated.

I also tried a different approach using rexReplace instead of rexSubstitute but couldn't get the regex pattern correct. The code I tried in CIW using rexReplace is as follows

a = "[@global_vddi:%:vddi!]"
"[@global_vddi:%:vddi!]"
rexCompile("\([@\[\]]*\)")
t
rexReplace(a "" 0)
"global_vddi:%:vddi!]"

Only '@[' get replaced and ']' is still present. The regex pattern contains '\]' to match the closing square bracket yet it is not replaced. Please let me know what I'm missing in these 2 scenarios.

Any help is much appreciated!!

Regards,

Confused SKILL user 

Artificial intelligence (AI) is everywhere. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making your breakfast. Verification is never truly complete; it is over when you run...(read more)

It has become challenging to ensure that the designs are complete, correct, and adhere to necessary coding rules before handing them off for RTL verification and implementation. RTL Designer Signoff Solution from Cadence helps the user identify RTL bugs at a very early development stage, saving a lot of effort and cost for the design and verification team. Our reputed customers have confirmed that using RTL signoff for their design IP helped save up to 4 weeks and reduce the late-stage RTL changes by up to 80%.(read more)

This November, the engineering and simulation community is set to converge in China for an event that promises to be nothing short of revolutionary. The 2024 BETA CAE Systems China Open Meeting, taking place in the vibrant cities of Beijing and Shanghai on November 5 and 7 , respectively, is a must-attend for anyone looking to stay at the forefront of technological innovation in simulation solutions. Prepare to be inspired by Ben Gu , the visionary Corporate VP of Research and Development at Cadence. He will lead both meetings in Beijing and Shanghai with his keynote on " A New Millennium in Multiphysics System Analysis ." This thought-provoking keynote is expected to provide attendees with a glimpse into the future of engineering simulation and analysis. What sets the BETA CAE Systems Open Meetings apart is not just the high caliber of speakers but also the hands-on training sessions designed to enhance your technical expertise with the BETA CAE software suite. Whether you are an inexperienced individual seeking to acquire fundamental knowledge or an accomplished professional endeavoring to hone your expertise, these training sessions following the open meetings are meticulously tailored to meet your needs. Join Us at the BETA CAE Systems Open Meeting in Beijing The BETA CAE Systems Open Meeting in Beijing will feature a keynote speech by Peng Qiao , Senior Engineer at Great Wall Motors Co., Ltd, on Multidisciplinary Optimization Techniques for Automotive Control Arms . ( View detailed agenda for Beijing. ) When: November 5, 2024 Where: Grand Metropark Hotel Beijing If this sounds interesting, register today for the BETA CAE Systems Beijing Open Meeting by clicking the button below. Don't Miss Out on the BETA CAE Systems Open Meeting in Shanghai After the BETA CAE Systems Open Meeting in Beijing, the next meeting in China will be in Shanghai. During this event, Liu Deping, CAE Engineer from Zhejiang Geely Automobile Research Institute Co., Ltd, will deliver a keynote speech on the Application of ANSA in the Simulation Development Cycle . ( View detailed agenda for Shanghai. ) When: November 7, 2024 Where: InterContinental Shanghai Jing'an Following the open meeting on November 7 will be an exclusive training day on November 8. This session will provide attendees with practical experience using the BETA CAE software to improve their technical skills and provide hands-on knowledge of the software. If you find this intriguing, register now for the BETA CAE Systems Shanghai Open Meeting by clicking the button below. Why Attend? Gain firsthand insights into the latest developments in simulation technology Learn from real-world applications and success stories from various industries Connect and exchange ideas with experts in a collaborative environment Mark your calendars for this unparalleled opportunity to explore the forefront of simulation technology. Whether you're aiming to broaden your knowledge, enhance your technical skills, or connect with industry leaders, the BETA CAE Systems Open Meetings are your gateway to the future of engineering. Join us and be part of shaping the next wave of innovation in the simulation world.

Hi,

Current and valid TCAs for Functional Safety are readily available at the FuSa "one-stop shop".

But I have not been able to find any archive repository for access to the obsoleted versions.

I would need to have also v1.4 of Xcelum TCA to investigate exact changes wrt previous projects.

Anyone knows how to find it?

Best regards,  Lars

Do you know if it is possible to define localized back etching (LBE) in EMX? It should be associated to a layer which defines the holes done in the substrate. I've not found any reference for this in the .proc syntax. 

--> Answer found. This is not possible because EMX considers the same dielectric in all x-y plane

Hello Team,
I am currently following this AWR script posted on them, to run a python script directly from inside AWR using VBA script.

Launching Python from AWRDE VBA Script - AWR Scripts - AWR Knowledgebase

Following all the basic steps with no changes to the code. I have Vscode and python-3.12.2 installed in my system. 

This is the error I am getting while running this code. 

Thank you for your help 

Best Regards

SID

Hi everyone,

I'm currently working on my thesis, which involves a beamformer system using CMOS 65nm technology. I'm trying to use the EMX tool for EM simulation but have encountered a few problems. Before diving into my questions about EMX, let me briefly explain how I conduct EM simulations with other software (ADS).

In ADS, I use the EM simulator with the Momentum microwave engine. However, my EM layout is quite large, and the mesh generated is extremely detailed, making it difficult to simulate the entire system. As a workaround, I divide the system into smaller parts and simulate each one individually. I've attached a snapshot of my setup, which includes an amplifier and a 1-to-2 Wilkinson power divider. I've separated these circuits and placed pins to facilitate EM simulations for each. I also placed ground pins at the boundaries of each circuit to connect them to the ground plane.

Here’s the link to the image (I'm unable to upload it due to an error): https://drive.google.com/file/d/13Qn4-DvMBj_K1JQLXrTWaWZ8uaLJr15u/view?usp=sharing

Now, moving on to EMX (version 6.3). For a maximum frequency of 31 GHz, I set the edge mesh = thickness = 0.4 µm (approximately the skin depth). However, when I simulate the circuit (amplifier + divider), the mesh on the ground plane becomes very dense, which makes running the simulation impossible due to excessive memory requirements. I reverted to my ADS approach and divided the circuit into two parts, placing ports to connect them. Unfortunately, EMX doesn't allow me to place multiple edge ports on the same edge for the ground plane, which has left me confused. Here are a couple of questions I have:

1. Is breaking the circuit into smaller parts a valid approach? Given the large ground plane, the mesh size for the ground is significant, making simulations challenging. Are there any methods to manage this issue?

2. Regarding the ground pins, why can't I place multiple edge ports to connect the ground planes of both circuits as I did in ADS? If this approach is incorrect, could you suggest alternative methods for simulating individual circuits and connecting them to estimate system performance?

Any insights would be greatly appreciated. Thank you in advance for your help!

An AMS Designer Flex simulation gives you the most immediate access to the latest simulation technology on either side, gets out of the way of the core engines and allows the engine performance to shine while providing access to new features. Check out this blog to know more.

This blog introduces the new Voltus-XFi Custom Power Integrity Solution, a transistor-level EM-IR tool that enables designers to complete comprehensive analysis and debugging easily and quickly.(read more)

Kenya’s cabinet secretary for the national treasury and planning, Ukur Yatani, discusses the country’s agenda of fiscal reforms and the importance of constructing an east-west Africa highway.

AstraZeneca will set up a R&D centre and an AI innovation centre in Shanghai, as well as create a $1bn fund that would invest in healthcare start-ups.

German chemical giant BASF has begun construction of its $10bn mega project in southern China, which will be the country’s first wholly foreign-owned chemical complex. 

Sino-European foreign direct investment is converging, according to data from fDi Markets.

Sardar Popalzai, president of the Balochistan Economic Forum, talks about the blue economy and the Pakistani province’s tourism potential.

Up to 18 countries across Latin America have joined China’s new Belt and Road Initiative, hoping to boost their infrastructure development and investment.  

Nurlan Kussainov, CEO of Kazakhstan’s AIFC Authority, discusses the financial centre’s achievements to date, and describes its ambitions to become a reference point in central Asia for capital markets and the fintech sector. 

Rustam Issatayev, deputy CEO of Kazakhstan’s national investment promotion agency, talks to fDi about the country’s new FDI strategy, which involves a proactive approach to attracting investment instead of simply talking up the country.

Data from fDi Markets shows that after a lean few years Chile's FDI landscape is recovering in impressive fashion.

FDI project numbers from China into the EU are on a downward trend, but Europe is still a popular destination for Chinese investment.

New rule changes mean Australian dairy establishments exporting to Chile will no longer be required to undergo periodic in-country audits by Chilean officials.

Kuwait has extended the shelf-life limit of chilled vacuum-packed beef from 90 days to 120 days.

As of Nov. 12, Apple’s 2024 MacBook Air with the new M3 chip is $200 off at Amazon, priced at $899.

Australian food and beverages wowed the crowd at the 2022 Private Label Trade Show in Chicago.

Australia’s Capricornia Contact Lens has signed a A$4.74 million joint venture with Guangzhou Ruitai Biotech to set up EPICON, an entity that will conduct R&D and manufacture scleral lens and other ophthalmic products.

The Australian Government welcomes today’s announcement by China to re-register two of Australia’s important barley exporters.

Today Australia has been reincluded on China’s list of approved outgoing group travel destinations.

Auxin Solar named more than a dozen companies in its petition to Commerce Department officials.

Ten years ago I was posted to South Korea to cover news.

THIS year marks the 75th anniversary of diplomatic relations between China and Hungary, with both nations elevating their ties to a comprehensive strategic partnership. As the Guest Country of Honor at

CHINA yesterday urged the United States to stop attacking and slandering the country, following the release of a US presidential memorandum that identified China as one of the major drug transit or illicit

CHINA’S first domestically built luxury cruise ship, the “Adora Magic City,” will set sail from the Shanghai Wusongkou International Cruise Liner Terminal on January 1, 2024. Passengers can make reservations

CHINA contributed nearly one-third of the academic papers published in the most influential international journals in 2022, marking the first time it surpassed the United States to secure the top position,

HOST China snapped up more gold medals at the Hangzhou Asian Games yesterday. A shooting world record fell to Chinese teenager Sheng Lihao in the men’s 10-meter air rifle with his 253.3 points surpassing

THAILAND extended a warm welcome to the first batch of visa-exempt flights from China yesterday, marking the launch of the nation’s fresh initiative to reinvigorate its Chinese tourist market. Approximately

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DESPITE the sweltering summer heat, tourists visiting Harbin, capital of northeast China’s Heilongjiang Province, now has a new attraction to explore — the world’s largest indoor ice and snow theme park. The