A photocurable material for sealing including (A) an oligomer having a weight average molecular weight of 10,000 to 30,000 and having (meth)acryloyl group(s), (B) a (meth)acrylate monomer, (C) a polythiol compound, and optionally (D) a carbodiimide compound enables the provision of a sealing material that has high compression recovery performance, high tensile strength and excellent flexibility, can have low hardness if required, and therefore has excellent sealing properties including air-tightness performance and water-proof performance and undergoes the formation of little surface tacks and the like.

A method includes configuring a processing circuit to perform: receiving a control word for an I/O operation, forwarding a transport command control block (TCCB) from the channel subsystem to a control unit, gathering data associated with the I/O operation, and transmitting the gathered data to the control unit in the I/O processing system. Gathering the data includes accessing entries of a list of storage addresses that collectively specifying the data. Based on an entry of the list comprising a not-set first flag and a corresponding first storage address, gathering data from a corresponding storage location, and based on an entry of the list comprising a set first flag and a corresponding second storage address, obtaining a next entry of the list from a second storage location.

Provided are a storage device, controller, and method for using host transfer rates to select a recording medium transfer rate for transferring data to a recording medium. A host transfer rate of data with respect to a buffer is measured. Provided are a plurality of recording medium transfer rates at which data is transferred between the buffer and the recording medium. A determination is made of an amount of decrease in the host transfer rate. The recording medium transfer rate is selected based on the amount of decrease in the host transfer rate. A transfer rate at which the storage device transfers data is set to the selected recording medium transfer rate.

An information processing apparatus includes a plurality of modules connected in a ring shape via a bus, and each module processes a packet flowing in a single direction on the ring in a predetermined order. The module includes a communication unit for transmitting a packet received from a first direction in the ring via the bus to a second direction, a discrimination unit for discriminating a packet from among the packets received from the first direction as a processing packet to be processed by the module, and a processing unit which is connected with the communication unit one by one and configured to process the processing packet. The communication unit transmits the packet processed by the processing unit at an interval equivalent to processing time or more for a processing packet processed by a module in a latter stage in the predetermined order among packets transmitted by the communication unit to the second direction.

Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.

A method for efficient dispatch/completion of a work element within a multi-node data processing system. The method comprises: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ.

The systems and methods described herein may be used to implement a shared dynamic-sized data structure using hardware transactional memory to simplify and/or improve memory management of the data structure. An application (or thread thereof) may indicate (or register) the intended use of an element of the data structure and may initialize the value of the data structure element. Thereafter, another thread or application may use hardware transactions to access the data structure element while confirming that the data structure element is still part of the dynamic data structure and/or that memory allocated to the data structure element has not been freed. Various indicators may be used determine whether memory allocated to the element can be freed.

An electronic device for using pause to manage resources is described. The electronic device includes a processor and instructions stored in memory. The electronic device monitors a pause duration and determines whether to perform a resource management operation based on the pause duration. The electronic device performs the resource management operation based on the pause duration.

By employing a two-tier load balancing scheme, embodiments of the present invention may reduce the overhead of shared resource management, while increasing the potential aggregate throughput of a thread pool. As a result, the techniques presented herein may lead to increased performance in many computing environments, such as graphics intensive gaming.

Disclosed is an information processing device and a task switching method that can reduce the time required for switching of tasks in a plurality of coprocessors. The information processing device (30) includes a processor core (301); coprocessors (311 to 31n) including operation units (321 to 32n) that perform operation in response to a request from the processor core (301) and operation storage units (331 to 22n) that store the contents of operation of the operation units (321 to 32n), save storage units (351 to 35n) that store the saved contents of operation, a task switching control unit (302) that outputs a save/restore request signal when switching a task on which operation is performed by the coprocessors (311 to 31n), and save/restore units (341 to 34n) that perform at least one of saving of the contents of operation in the operation storage units (331 to 33n) to the save storage units (351 to 35n) and restoration of the contents of operation in the save storage units (351 to 35 n) to the operation storage units (331 to 33n) in response to the save/restore request signal.

The present invention provides a method for separating halocarbons. In particular, the invention provides a method for separating halogenated olefin impurities from 2-chloro-1,1,1,2-tetrafluoropropane (HCFC-244bb) using a solid adsorbent, particularly activated carbon. More particularly the invention pertains to a method for separating 2-chloro-3,3,3-trifluoro-propene (HCFO-1233xf) from HCFC-244bb, which are useful as intermediates in the production of 2,3,3,3-tetrafluoropropene (HFO-1234yf).

Process for producing silica-comprising dispersions comprising a polyetherol or a polyether amine, which comprises the steps of (i) admixing an aqueous silica sol (K) having an average particle diameter of from 1 to 150 nm and a silica content, calculated as SiO2, of from 1 to 60% by weight and a pH of from 1 to 6 with at least one polyetherol (b1) and/or polyether amine (b2) based on ethylene oxide and/or propylene oxide and having an average OH or amine functionality of from 2 to 6 and a number average molecular weight of from 62 to 6000 g/mol,(ii) distilling off at least part of the water,(iii) admixing the dispersion with at least one compound (S) having at least one at least monoalkoxylated silyl group and at least one alkyl, cycloalkyl or aryl substituent, where this substituent may have groups which are reactive toward an alcohol, an amine or an isocyanate in an amount of from 0.1 to 20 μmol of (S) per m2 of surface area of (K), where steps (i) and (iii) can be carried out simultaneously or in succession in any order, (iv) optionally adjusting the pH of the silica-comprising dispersions obtained to a value of from 7 to 12 by adding a basic compound, where step (iv) can also be carried out between steps (ii) and (iii).

Methods of increasing the solubility of a base in supercritical carbon dioxide include forming a complex of a Lewis acid and the base, and dissolving the complex in supercritical carbon dioxide. The Lewis acid is soluble in supercritical carbon dioxide, and the base is substantially insoluble in supercritical carbon dioxide. Methods for increasing the solubility of water in supercritical carbon dioxide include dissolving an acid or a base in supercritical carbon dioxide to form a solution and dissolving water in the solution. The acid or the base is formulated to interact with water to solubilize the water in the supercritical carbon dioxide. Some compositions include supercritical carbon dioxide, a hydrolysable metallic compound, and at least one of an acid and a base. Some compositions include an alkoxide and at least one of an acid and a base.

The present invention relates to compositions for use in refrigeration, air-conditioning, and heat pump systems wherein the composition comprises E-1,2-difluoroethylene. The compositions of the present invention are useful in processes for producing cooling or heat, as heat transfer fluids, foam blowing agents, aerosol propellants, and power cycle working fluids.

The present invention relates to compositions for use in refrigeration, air-conditioning, and heat pump systems wherein the composition comprises Z-1,2-difluoroethylene (Z-HFO-1132a). The compositions of the present invention are useful in processes for producing cooling or heat, as heat transfer fluids, foam blowing agents, aerosol propellants, and power cycle working fluids.

Particular aspects provide compositions comprising an electrokinetically altered oxygenated aqueous fluid, wherein the oxygen in the fluid is present in an amount of at least 25 ppm. In certain aspects, the electrokinetically altered oxygenated aqueous fluid comprises electrokinetically modified or charged oxygen species present in an amount of at least 0.5 ppm. In certain aspects the electrokinetically altered oxygenated aqueous fluid comprises solvated electrons stabilized by molecular oxygen, and wherein the solvated electrons present in an amount of at least 0.01 ppm. In certain aspects, the fluid facilitates oxidation of pyrogallol to purpurogallin in the presence of horseradish peroxidase enzyme (HRP) in an amount above that afforded by a control pressure pot generated or fine-bubble generated aqueous fluid having an equivalent dissolved oxygen level, and wherein there is no hydrogen peroxide, or less than 0.1 ppm of hydrogen peroxide present in the electrokinetic oxygen-enriched aqueous fluid.

The disclosure relates to methods of making polymer particles, said methods including the steps of: making an aqueous gel reaction mixture; forming an emulsion having dispersed aqueous phase micelles of gel reaction mixture in a continuous phase; adding an initiator oil comprising at least one polymerization initiator to the continuous phase; and performing a polymerization reaction in the micelles. Further, the initiator oil is present in a volume % relative to a volume of the aqueous gel reaction mixture of between about 1 vol % to about 20 vol %. The disclosure also relates to methods of making nucleic acid polymer particles having the same method steps and wherein the aqueous gel reaction mixture includes a nucleic acid fragment, such as a primer.

A data processing apparatus includes multiple processing means that are connected in a ring shape via corresponding communication means respectively. Each communication means includes a reception means for receiving data from a previous communication means, and a transmission means for transmitting data to a next communication means. Connection information is assigned to each of the reception means and the transmission means. The communication means, when receiving a packet that has same connection information as one assigned to its reception means, causes the corresponding processing means to perform data processing on the packet, sets the connection information assigned to its transmission means to the packet, and transmits the packet to the next communication means, and when receiving a packet that has connection information that is not same as one assigned to its reception means, transmits the packet to the next communication means without changing the connection information of the packet.

A statue management section of a control section is provided with a corresponding real number storage section that stores a real number converted from a logical number by a configuration number converting section. When the corresponding real number storage section has stored configuration information with a real number of the next transition state, the state management section directly supplies the real number to the configuration information storage section in the next or later processing cycle.

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index, and then, the register file pointed to by said index is accessed based on said index; an execution stage where an access result of said decode stage is received, and computations are implemented according to the access result of the decode stage.

A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target.

A method of extending advanced process control (APC) models includes constructing an APC model table including APC model parameters of a plurality of products and a plurality of work stations. The APC model table includes empty cells and cells filled with existing APC model parameters. Average APC model parameters of the existing APC model parameters are calculated, and filled into the empty cells as initial values. An iterative calculation is performed to update the empty cells with updated values.

A computing machine is disclosed having a memory system for storing a collection of execution nodes, a head for reading a sequence of symbols in the execution nodes in the memory system, and writing a sequence of symbols in the memory system. The machine is configured to execute a computation with a collection of pairs of execution nodes. Each pair of execution nodes represents a machine instruction. One execution node in the pair represents input of the machine instruction represented by the execution nodes. Another execution node in the pair represents output of the machine instruction represented by the execution nodes. Each execution node has a state of the machine, a sequence of symbols and a number.

The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced. The disclosure reduces the cycle delay of the slave processor in accessing the dual-port RAM and the register, thereby effectively reducing the dynamic power consumption of the chip, improving the processing capability of the slave processor and enhancing the effective performance of the slave processor.

A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.

A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.

Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.

In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state.

A method of applying formal verification methodologies to event processing applications is provided herein. The method includes the following stages: representing an event processing application as an event processing network, being a graph with event processing agents as nodes; generating a finite state machine based on the event processing network, wherein the finite state machine is an over-approximation of the event processing application; expressing stateful rules and policies that are associated with the event processing application using temporal logic, to yield a temporal representation of the event processing application; combining the temporal representation and the finite state machine into a model; generating a statement associated with a user-selected verification-related property of the event processing application, wherein the statement is generated using the temporal representation; and applying the statement to the model, to yield an indication for: (i) a correctness of the statement or (ii) a counter example, respectively.

An aspect of the present invention identifies differences between source codes (e.g. of different versions of a software), when each source code is organized using incorporated files. In one embodiment, in response to receiving identifiers of a first and second source codes (each source code being organized as a corresponding set of code files), listings of the instructions in the first and second source codes are constructed. Each listing is constructed, for example, by replacing each incorporate statement in the source code with instructions stored in a corresponding one of code files. The differences between the first and second source codes are then found by comparing the constructed listings of instructions.

An information processing system, computer readable storage medium, and method for automatically generating human readable and meaningful documentation for one or more source code files. A processor of the information processing system receives one or more source code files containing source code artifacts (SCA) and infers semantics therefrom based on predefined rules. The processor, based on the inferred semantics, extracts documentation from another source code file. The extracted documentation and the inferred semantics are used to generate new human readable and meaningful documentation for the SCA, such new documentation being previously missing from the SCA. The generated new documentation is included with the SCA in one or more source code files.

Disclosed is a novel computer implemented system, on demand service, computer program product and a method that leverages combined concrete and symbolic execution and several fault-localization techniques to automatically detects failures and localizes faults in PHP Hypertext Preprocessor (“PHP”) Web applications.

A method is provided for providing consistent logical code across specific programming languages. The method incorporates preprocessor macros in a source computer program code to generate a program control flow. The preprocessor macros can be used to describe program control flow in the source programming language for execution in the source computer program code. The preprocessor macros can also be used to generate control flow objects representing the control flow, which converts the source computer program code into a general language representation. The general language representation when executed is used to output computer programming code in specific programming languages representing the same logical code as that of the source computer program code.

In one embodiment of the invention, a method is disclosed for modifying a pre-existing application program for multi-processing and/or distributed parallel processing. The method includes searching an application program for a computational loop; analyzing the computational loop to determine independence of the computational transactions of the computational loop; and replacing the computational loop with master code and slave code to provide master-slave execution of the computational loop in response to analyzing the computational loop to determine independence of the computational transactions of the computational loop. Multiple instances of the modified application program are executed to provide multi-processing and/or distributed parallel processing.

Methods and systems to identify and reproduce concurrency bugs in multi-threaded programs are disclosed. An example method disclosed herein includes defining a data type. The data type includes a first predicate associated with a first thread of a multi-threaded program that is associated with a first condition, a second predicate that is associated with a second thread of the multi-threaded program, the second predicate being associated with a second condition, and an expression that defines a relationship between the first predicate and the second predicate. The relationship, when satisfied, causes the concurrency bug to be detected. A concurrency bug detector conforming to the data type is used to detect the concurrency bug in the multi-threaded program.

A process for making particles comprising a hydrophobic dopant for subsequent release therefrom is disclosed. The process comprises providing an emulsion comprising a hydrophilic phase and a hydrophobic phase dispersed in the hydrophilic phase, and reacting the precursor material to form the particles comprising the dopant therein. The hydrophobic phase comprises a precursor material and the dopant.

Recovery of ethanol from a crude ethanol product obtained from the hydrogenation of acetic acid using an extractive distillation column. A diluted acid stream, comprising less than 30 wt. % acetic acid, is used as the extractive agent and is fed at a point above the crude feed stream. The column yields a residue that comprises ethanol, acetic acid, and water. The diluted acid stream may be separated from the residue and returned to the extractive distillation column.

A process for selective formation of ethanol from acetic acid by hydrogenating acetic acid in the presence of a catalyst comprises a first metal on an acidic support. The acidic support may comprise an acidic support material or may comprise an support having an acidic support modifier. The catalyst may be used alone to produced ethanol via hydrogenation or in combination with another catalyst. In addition, the crude ethanol product is separated to obtain ethanol.

A process is disclosed for producing ethanol comprising contacting acetic acid and hydrogen in a reactor in the presence of a catalyst comprising a binder and a mixed oxide comprising nickel and tin.

Disclosed herein are processes for alcohol production by reducing an esterification product, such as ethyl acetate. The processes comprise esterifying acetic acid and an alcohol such as ethanol to produce an esterification product. The esterification product may be recovered using an extractive separation. The esterification product is reduced with hydrogen in the presence of a catalyst to obtain a crude reaction mixture comprising the alcohol, in particular ethanol, which may be separated from the crude reaction mixture.

The present invention relates to an apparatus for coproducting iso-type reaction product and alcohol from olefin, and a method for coproducting using the apparatus, in which the hydroformylation reactor provides a sufficient reaction area due to the broad contact surface area between the olefin and the synthesis gases that are the raw materials by a distributor plate installed in the reactor, and the raw materials can be sufficiently mixed with the reaction mixture due to the circulation of the reaction mixture so that the efficiency of the production of the aldehyde is excellent; and also the hydrogenation reactor suppresses the side reaction so that the efficiency for producing aldehyde and alcohol are all increased, and also iso-type reaction product and alcohol can be efficiently co-produced.

Disclosed herein are processes for alcohol production by reducing ethyl acetate produced by hydrogenating acetic acid in the presence of a suitable catalyst. The product of the acetic acid hydrogenation is fed directly to a decanter to separate the hydrogenation product into an aqueous phase comprising water and ethanol and an organic phase comprising ethyl acetate. The organic phase is reduced with hydrogen in the presence of a catalyst to obtain a crude reaction mixture comprising the alcohol, in particular ethanol, which may be separated from the crude reaction mixture. Thus, ethanol may be produced from acetic acid through an ethyl acetate intermediate without an esterification step. This may reduce the recycle of ethanol in the hydrogenolysis process and improve ethanol productivity.

An optically active bicyclic compound is efficiently produced by optical resolution using an optically active amine.

A navigation system having a central device which uses a link shape compression unit to compress information of altitude changes of a road link obtained from a three-dimensional road map, and calculates a geometry parameter based on variation of energy of a vehicle travelling on the road link. An on-board terminal device estimates the vehicle's average travelling pattern by using a travel-pattern-estimation unit based on the geometry parameter calculated by the central device, a link-travelling time estimated from statistically-stored traffic information, and a link length. The on-board terminal device further calculates fuel consumption of the vehicle travelling on each road link based on the estimated travelling pattern and parameters of the vehicle by using a fuel-consumption calculation unit, and then, searches a fuel-efficient route by using the fuel consumption as a link cost. The on-board terminal device has a vehicle-type selector for selecting a type of the vehicle.

There is a provided a method for car navigating using traffic signal data. The method for car navigating is characterized of providing an optimized route for the earliest arrival to destinations by using signal system data of one or more traffic signals existing on a certain route.