A scan driving apparatus includes a plurality of sequentially arranged scan driving blocks, each including: a first node configured to receive a first clock signal; a second node configured to receive an input signal according to a second clock signal input; a first transistor having a gate electrode coupled to the first node, a first electrode configured to receive a power source voltage, and a second electrode coupled to an output terminal; and a second transistor having a gate electrode coupled to the second node, a first electrode for receiving a third clock signal, and a second electrode coupled to the output terminal. Each scan driving block is configured to receive the first, second, and third clock signals as a corresponding three clock signals among four clock signals sequentially shifted by a first period, and to output the third clock signal by being synchronized with the input signal.

A stage circuit and a scan driver using the same that is capable of concurrently (e.g., simultaneously) or progressively supplying a scan signal to a plurality of scan lines. The stage circuit includes a progressive driver and a concurrent driver.

Methods, systems and devices are provided for displaying monitored activity data in substantial real-time on a screen of a computing device. One example method includes capturing motion data associated with activity of a user via an activity tracking device. The motion data is quantified into a plurality of metrics associated with the activity of the user. The method includes connecting the activity tracking device with a computing device over a wireless data connection, and sending motion data from the activity tracking device to the computing device for display of one or more of the plurality of metrics on a graphical user interface of the computing device. At least one of the plurality of metrics displayed on the graphical user interface is shown to change in substantial real-time based on the motion data.

A scanning circuit, comprising first signal lines, second signal lines, third signal lines, a drive unit configured to drive the first signal lines, first buffers configured to drive the second signal lines in accordance with signals of the first signal lines, second buffers configured to drive the third signal lines in accordance with the signals of the first signal lines, and a shift register having a first part to be driven by signals of the second signal lines and a second part to be driven by signals of the third signal lines, wherein the first to third signal lines include two signal lines arranged in parallel to each other and configured to transmit the in-phase signals.

Methods, devices and system are provided. One method includes capturing activity data associated with activity of a user via a device. The activity data is captured over time, and the activity data is quantifiable by a plurality of metrics. The method includes storing the activity data in storage of the device and, from time to time, connecting the device with a computing device over a wireless communication link. The method defines using a first transfer rate for transferring activity data captured and stored over a period of time. The first transfer rate is used following startup of an activity tracking application on the computing device The method also defines using a second transfer rate for transferring activity data from the device to the computing device for display of the activity data in substantial-real time on the computing device.

A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhance operation speed and reduced power consumption.

A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.

A shift register circuit includes a first shift register string and a second shift register string. The first shift register string is configured to receive a first start signal and output a first-stage control signal. The second shift register string, electrically connected to the first shift register string, is configured to receive the first-stage control signal and a second start signal and output the first pulse of a first-stage scan signal according to the first-stage control signal and the second start signal and consequently output the second pulse of the first-stage scan signal according to the second start signal; wherein the first and second pulses are configured to have different pulse widths. A driving method of a shift register circuit is also provided.

A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

A stage constituent circuit of a display device drive circuit includes a first-node to a third-node, a thin-film transistor that changes a potential of a scanning signal toward a VDD potential when a potential of the first-node is in a HIGH level, a thin-film transistor that changes a potential of a different stage control signal toward a potential of a clock when a potential of the second-node is in the HIGH level, a capacitor between the first-node and the second-node, and a capacitor between the second-node and the third-node. The potential of the first-node is raised on the basis of a different stage control signal output from the stage constituent circuit in the different stage, and then the potential of the second-node and a potential of the third-node are sequentially raised. Herein, an amplitude of the clock is set to be smaller than an amplitude of the scanning signal.

An active level shift (ALS) driver circuit and a liquid crystal display apparatus including the ALS driver circuit are disclosed. The ALS driver circuit includes an input unit configured to apply a first polarity voltage to a first node and to apply a second polarity voltage to a second node, a level compensation unit configured to adjust the voltages of the first node and the second node, and an output unit configured to alternately output a first power voltage and a second power voltage according to the adjusted voltages of the first and second nodes.

A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (fs) and the destination frequency (fd). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.

One of the most important RF building blocks today is the frequency synthesizer, or more particularly the programmable frequency divider (divider). Such dividers preferably would support unlimited range with continuous division without incorrect divisions or loss of PLL lock. The inventors present multi-modulus dividers (MMDs) providing extended division range against the prior art and without incorrect divisions as the division ratio is switched back and forth across the boundary between two different ranges. Accordingly, the inventors present MMD frequency dividers without the drawbacks within the prior art.

A stage circuit including an output unit for supplying first or second power source to an output terminal is disclosed. The stage circuit may comprise a bidirectional driver for respectively supplying signals supplied to first and second input terminals, a first driver, and a second driver. The second driver controls the output unit to output the second power source to the output terminal without any voltage loss, corresponding to a second clock signal.

A display apparatus and a method for generating gate signal thereof are provided. The display apparatus includes a timing controller and a display panel. The timing controller is used for providing a plurality of timing signals. The display panel includes a pixel array and a gate drive circuit. The pixel array has a plurality of pixels. The gate drive circuit is electrically connected to the timing controller and the pixel array and including a plurality of shift register circuits. The shift register circuit includes a first shift register and a second shift register. The first shift register is configured for generating a corresponding primary gate signal. The second shift register is configured for generating a corresponding secondary gate signal. The timing controller adjusts overlapping relations of the timing signals according to a frame rate of the display apparatus.

A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.

A system for optimizing storage in an enclosed transport trailer (6), having transverse bearing beams (2) for supporting a load such as loaded pallets (12, 13) at a mid height of the trailer such that two storage levels are available. The beams have a wheel (10) at each end that runs in a horizontal track (11) attached to each side wall of the trailer, the track enclosing the wheels to prevent them from disengaging from the track. Adjacent beams can be attached together at variable spacings using a spacer bar (15) to suit a particular pallet or load size. The track has a junction adjacent the open end (20) of the trailer that leads up to another track (18) immediately below the roof line where the beams can be moved to an out of the way storage position (19) when not required.

A vehicle restraint system includes a strap assembly configured to be positioned on a portion of a tire of a vehicle to secure the vehicle to a deck of a transport. The strap assembly is also configured to be coupled to the deck of the transport on a first side of the tire of the vehicle. The system also includes a mandrel assembly operable to be coupled to the strap assembly on a second side of the tire of the vehicle, opposite the first side. The system further includes a winch assembly configured to be coupled to the deck of the transport and the mandrel assembly on the second side of the tire of the vehicle, the winch assembly configured to rotate the mandrel assembly to produce a tightening force to tighten the strap assembly around the portion of the tire. The system still further includes a release mechanism disposed between the winch assembly and the mandrel assembly and configured to create a coupling between the winch assembly and the mandrel assembly in a manner that transmits the tightening force from the winch assembly to the mandrel assembly. The release mechanism is configured to release the coupling between the winch assembly and the mandrel assembly when a force greater than or equal to a predetermined force is produced against the release mechanism.

There is provided a transport vehicle for transporting wind power installation rotor blades and/or pylon segments. The transport vehicle has a transport support structure having a main frame, a receiving frame fixedly connected to the main frame at a first angle, and a rotary displacement unit which is fixed with one end to the receiving frame and which at its second end has a blade adaptor for receiving a rotor blade or a pylon segment. The main frame spans a main plane. The rotary displacement unit has at least one first rotary mounting, wherein there is provided a second angle between the second rotary plane of the second rotary mounting.

A bull ring for a vehicle comprises a top plate coupled to a rotating plate having a tie-down. Two opposing rail flanges extend from the rotating plate and a fastener selectively couples the rotating plate in a securing position relative to the top plate. The rail flanges extend beyond an outer edge of the top plate to define a clamping region with the top plate.

Some embodiments of the invention relate to function elements for fixing in seat rails of aircraft. The function element according to the invention may include: a fixing rail with a web running in the x direction and a multiplicity of extensions which protrude beyond the web in a y direction to form a T profile, wherein the fixing rail is formed corresponding to the seat rail such that the fixing rail can be inserted in the seat rail and moved along the x direction into a holding position in which the extensions sit between the holes below the slots, at least one fixing peg which is arranged mobile on the fixing rail and can be brought into a blocking position in which the fixing peg engages in a hole of the seat rail so that the function element is fixed in the x direction.

A fixture for attachment of an end of a member, such as a wind turbine tower section, blade or hub for a wind turbine characteristically has an end flange. To enable clamping while being able to compensate for different hole patterns in the flanges, by the invention, the fixture provides for retaining of ends of members with flanges, regardless of flange diameter and hole patterns, and which is also quickly and easily installed. Additionally, it is possible to firmly clamp the flange end to upstanding frame parts of the fixture with fastening elements, thereby providing a stable connection between a console of the fixture and the upstanding frame parts.

Method and apparatus for handling aerogenerator blades that provide a versatile means for handling aerogenerator blades without an unbalanced distribution of the loads in the blade. The method comprises positioning an upper mounting part (103) over the blade after the upper mold has been retracted; lifting the blade with the upper mounting part from the under mold using a lifting means; positioning the blade over an under mounting part (104) which is fixedly attached to an inferior movable support (102); attaching the upper mounting part to the under mounting part, wherein the upper and under mounting parts together have the inner surface substantially corresponding to the shape of the blade outer profile section. The invention further comprises an apparatus for handling aerogenerator blades.

An example wheel restraint includes a track to be positioned adjacent a vehicle approach path of a loading dock. A shuttle is pivotally coupled to the track via a track follower and pivots between a home position and a deployed position about a shuttle axis substantially parallel to and offset relative to a longitudinal axis of the track. A barrier is pivotally coupled to the shuttle and pivots between a non-blocking position and a blocking position about a pivot axis substantially parallel to and spaced apart from the longitudinal axis of the track such that the shuttle rotates in a first direction about the shuttle axis when the shuttle moves from the home position to the deployed position and bather rotates in a second direction about the pivot axis when the barrier moves from the non-blocking position to the blocking position, where the first direction being different than the second direction.

An apparatus and method for applying an underlayment layer to trucking cargo are provided. The underlayment layer may be formed into a roll with a rod disposed therethrough. The roll may be supported by a frame. The roll can be configured to move vertically with respect to the ground. A trailer carrying trucking cargo can be stationed beneath the frame. The underlayment layer may unwound and dispensed from the roll. In order to drape the trucking cargo with the underlayment layer, the roll may be moved horizontally over the frame in addition to or alternatively to having the trucking cargo driven horizontally with respect to the roll.

An edge protector for insertion between a load to be lifted and a lifting member which facilitates the lifting of the load, preventing damage to either the load or the lifting member. The edge protector has a pair of flanges which extend from a radiused or curved center portion. Each flange has an inner surface and an outer surface. A portion of each respective outer surface of each flange is spaced from and is essentially parallel to the inner surface of the respective flange.

A novel configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations is provided. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. The configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. The configuration network is a pipelined network.

A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

A bridge output circuit includes an output terminal, a high side transistor, a low side transistor, a high side driver for controlling a gate voltage of the high side transistor, a low side driver for controlling a gate voltage of the low side transistor, and a controller for controlling the high side and low side drivers. The low side driver includes a first current source, a second current source, and a first assist circuit. The controller is configured to control the turning-on and turning-off states of the first current source, the second current source and the first assist circuit.

An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.

Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc.

A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.

Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current.

Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.

A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.

An impedance tuning circuit includes a calibration unit and a post-processing unit. The calibration unit generates an initial pull-up code and an initial pull-down code by performing a calibration operation using an external resistor during an initial impedance tuning operation. The post-processing unit outputs the initial pull-up code and the initial pull-down code as a final pull-up code and a final pull-down code during the initial impedance tuning operation, and generates the final pull-up code and the final pull-down code by using the initial pull-up code and the initial pull-down code during a subsequent impedance tuning operation.

A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.

A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

The present invention relates to a method for downloading a binary configuration file in a programmable circuit implemented in a device. The device comprises at least one central processing unit, a plurality of connectors, and a programmable circuit enabling all or a part of the signals received by said connectors to be processed and transmitted to at least one other circuit of the device. The device analyzes the signals present on the connectors in order to define what other devices are connected and whether the connections are operational. Then, a configuration file is selected from among a set of configuration files according to the operational connections and is downloaded from a memory of the device into the programmable circuit. The invention also relates to a device having a component programmed according to the method previously described.

The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

An integrated circuit (IC) with a novel configurable routing fabric is provided. The configurable routing fabric has signal paths that propagate signals between user registers on user clock cycles. Each signal path includes a set of configurable storage elements and a set of configurable logic elements. Each configurable storage element in the path is reconfigurable on every sub-cycle of the user clock cycle to either store an incoming signal or to pass the incoming signal transparently.

A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.

The present disclosure relates to nanoresonator oscillators or NEMS (nanoelectromechanical system) oscillators. A circuit for measuring the oscillation frequency of a resonator is provided, comprising a first phase-locked feedback loop locking the frequency of a controlled oscillator at the resonant frequency of the resonator, this first loop comprising a first phase comparator. Furthermore, a second feedback loop is provided which searches for and stores the loop phase shift introduced by the resonator and its amplification circuit when they are locked at resonance by the first loop. The first and the second loops operate during a calibration phase. A third self-oscillation loop is set up during an operation phase. It directly links the output of the controllable phase shifter to the input of the resonator. The phase shifter receives the phase-shift control stored by the second loop.

A resonator element includes a substrate including a first principal surface and a second principal surface respectively forming an obverse surface and a reverse surface of the substrate, and vibrating in a thickness-shear vibration mode, a first excitation electrode disposed on the first principal surface, and a second excitation electrode disposed on the second principal surface, and being larger than the first excitation electrode in a plan view, the first excitation electrode is disposed so as to fit into an outer edge of the second excitation electrode in the plan view, and the energy trap confficient M fulfills 15.5≦M≦36.7.

A resonator element includes a substrate vibrating in a thickness-shear vibration mode, a first excitation electrode disposed on one principal surface of the substrate, and has a shape obtained by cutting out four corners of a quadrangle, and a second excitation electrode disposed on the other principal surface of the substrate, and a ratio (S2/S1) between the area S1 of the quadrangle and the area S2 of the first excitation electrode fulfills 87.7%≦(S2/S1)