An LCD is integrated with the cover glass of a wrist watch radio paging receiver which indicates the time data with a dial plate and hands, and a message is displayed on the cover glass by controlling this LCD. In this message display, the parts of the characters indicating the message are made transparent and the remaining parts intercept light. In this manner, message display is made possible by the difference in light transmissivity.

A system includes a system time counter associated with a micro controller and a secure clock module having a real time clock and an elapsed time counter. The system synchronizes operation between the secure clock module and the system time counter. The synchronized time entered into the system time counter is utilized in the operation of the system. The real time clock time can be caused to be entered into the elapsed time counter at certain point in the operation of the system. The relationship of the time provide enhanced systems security.

PCT No. PCT/CH96/00292 Sec. 371 Date May 22, 1998 Sec. 102(e) Date May 22, 1998 PCT Filed Aug. 23, 1996 PCT Pub. No. WO97/08592 PCT Pub. Date Mar. 6, 1997A method by which an elastomer is applied to a model (1) with relief marks to be reproduced. The purpose of the elastomer once set is to form a mold membrane (14) and incorporate within its own material the shape of the marks on the model. The mold membrane is then separated from the model and filled with a setting material, and the mold membrane is applied to a support in order to transfer the marks after preliminary pasting.

An apparatus for measuring a time interval between a start signal edge and a stop signal edge provides a stable clock signal as input to a delay line formed by a series of similar logic gates. The output signal of the last gate of the series is phase locked to the clock signal by adjusting a bias signal controlling the switching speed of all gates. The clock signal and the output signal of each gate form a set of phase distributed periodic timing signals applied to a start time measurement unit (TMU) and a similar stop TMU. The start TMU counts edges of one of the timing signals occurring between an edge of an arming signal and the start signal edge and generates output data representing a time delay between the arming signal and the start signal edge. The data represents the start delay as a whole and fractional number of clock signal periods by conveying the counter output and by indicating which of the timing signals had an edge most closely following the start signal edge. The stop TMU similarly produces output data indicating a whole an fractional number of clock cycles occurring between the arming signal and the stop signal edge. The delay represented by the start TMU output data is subtracted from the delay represented by the stop TMU output data to determine the interval between the start and stop signal edges.

A first circuit having a first coil electrically charges a second circuit having a second coil through electromagnetic coupling of the two coils. When data signals are to be transferred between the first and second circuits, signal transfer is started only after the second circuit has been charged for a predetermined period of time. The position relationship between the coils is also detected, and a charging/transfer selector changes a duty ratio between charge transfer and data transfer in accordance with the detected result. The charge is transferred in an intermittent manner, and the charging rate is adjusted according to the difference between the voltage of a secondary battery observed during a charging phase and the voltage of the secondary battery observed a certain time after interruption of the charging phase, or vice versa.

A yo-yo has a recess in one of its faces accommodating a timepiece. The yo-yo is be releasably accommodated in a base, and the base may be worn on a user's person by various means including a wristband in the manner of a wristwatch, a fob or a watch chain in the manner of a pocket watch, a necklace in the manner of a necklace watch, or a holster.

An object of the present invention is to provide a method for producing a display device by which a substrate is thinned efficiently. Onto one original substrate having an area for a plurality of display devices, the other original substrate is bonded via a sealing resin layer, the pair of bonded original substrates is divided and separated into a plurality of pairs of substrates of a size of each individual display device, and thereafter a substrate thinning process of thinning the substrates is performed in a state where the substrates are held by substrate holding means.

In an electromagnetic converter comprising a rotor arranged by including a permanent magnet, a yoke disposed in the vicinity of the rotor for flowing magnetic flux and a coil wound around the yoke, at least a portion of the yoke is composed of an amorphous metal magnetic material. The amorphous metal magnetic material is a Co amorphous metal or a Fe amorphous metal. The electromagnetic converter is a small generator, a motor and the like. In an electronic timepiece provided with a generator device, the Co amorphous metal magnetic material is used for a first yoke (stator) and the Fe amorphous metal magnetic material is used for a second yoke (coil core). In an electronically-controlled mechanical watch, the Co amorphous metal magnetic material is used for a yoke. Portable electronic equipment is a timepiece provided with the electromagnetic converter, and so forth

A mechanism for determining whether the sun is visible at a diurnal solar event and for mechanically triggering actions based upon the sun being visible during the diurnal solar event is disclosed. The mechanisms of the invention can perform these operations without intervention or supervision for long periods of time. Certain embodiments have been applied to provide a diurnal solar event trigger based upon sidereal noon for a clock providing accurate timing for 10,000 years without intervention or supervision.

An electronic data system for use with sporting impliments for providing a user with an electronic device integrated into sport gloves to perform various functions unique to that particular sport. The electronic data system for use with sporting impliments includes a glove member designed for substantially enveloping a hand of a user. The glove member has a notch portion in a back side of the glove member. The notch portion is for facilitating insertion and removal of the user's hand from the glove member. The glove member has a tab portion positioned adjacent to a first side of the notch portion. A data assembly has a housing. The housing is operationally coupled to the glove member. The data assembly has a display for presenting a visual representation of information to the user.

A network is described for providing estimates of the current time. The network includes multiple computer systems each configured to provide an estimate of the current time in response to a received request. The computer systems are logically arranged to form a hierarchical structure, wherein the hierarchical structure includes multiple levels ranked with respect to one another. Each of the computer systems is assigned one of multiple levels of trust, and occupies one of the levels of the hierarchical structure dependent upon the assigned level of trust. The level of trust assigned to a given computer system is dependent upon a timekeeping dependability of the given computer system. The assigned level of trust may also be dependent upon a timekeeping security of the given computer system, where the timekeeping security is dependent upon a tamper resistance of the time clock of the given computer system. Methods for delegating a level of trust to a new computer system (i.e., a computer system not part of the network) and for adding a new computer system to the network are also described.

A method and device for synchronizing the time between at least two integrated circuits (201, 202), which receive the same pulse signal. In the integrated circuits (201, 202) a counter (204, 206) is used to count the number of pulses in the received pulse signal to synchronize the common time between said integrated circuits.

The device consists in compensating for the distortion of the characters marked on the dial caused by a lens, by writing the characters with a reverse pin cushion or barrel distortion.

A system and method for tracking and informing about a physical, emotional, or physiological cycle, such as a menstrual cycle, includes at least one definition entry and at least one date indicator. Each definition entry defines indicia such as color to represent a stage of a physical, emotional, or physiological cycle. Each date indicator includes a date section and a tracking section corresponding to each date section. The date section of the date indicator indicates at least one date, wherein the tracking section is capable of being marked so as to indicate indicia corresponding to a definition entry to signify the stage of the physical, emotional, or physiological cycle for each date. According to one embodiment, the date indicators are arranged according to phases of the moon to allow correlation of a user's cycle to the lunar cycle.

A musical rhythm is expressed by the number of the timing marks (for example, three timing marks when in simple triple time); and a musical tempo is expressed by the distance among the timing marks and a timing ball that moves at a fixed speed among those timing marks. Accordingly, a player may easily grasp the tempo of the music and easily determine the rhythm of the music in a sound game.

A method for detecting and conveying an alarm signal, when an absorbent article is unfastened or, completely removed from the body of the wearer. The method is intended to be used in parallel with a method for detecting wetness in the absorbent article and further relates to an integrated detection-and-alarm method for detecting unfastening and/or wetness in an absorbent article. A system for detecting and conveying an alarm signal when an absorbent article is unfastened or removed from the body of the wearer and/or when the article is wet. The system includes (a) and absorbent article having at least one absorbent layer, the object to be displaced, such as a fastening system, one or more sensoring devices, one or more transmitting devices, and (b) a remote receiver. Furthermore, the system relates to the use of the system in the care of children and adults suffering from incontinence and/or psychological illnesses.

Smoking cessation lighter is configured for lighting cigarettes for a smoker, and learning software is provided for monitoring smoking behavior of a smoker during a first data collection period and guiding a smoker's smoking cessation by directing the smoker when the smoker is to smoke a cigarette based on data collected during the first data collection period. The learning software monitors user behavior and collects data during use of the lighter by the smoker after the initial data collection period in order to analyze and further guide the smoker based on the smoker's cheating behavior, the smoker's behavior of lighting a cigarette for a friend, and the smoker's behavior of skipping use of the lighter at a time when the smoker has been directed to light a cigarette by the lighter.

Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage module operable within a communication network to present the plurality of physical storage devices as a virtual storage device to a plurality of network computing elements that are coupled to the communication network. The virtual storage device comprises a plurality of virtual storage volumes, wherein each virtual storage volume is communicatively coupled to the physical storage devices via the storage module. The storage module comprises maps that are used to route read/write requests from the network computing elements to the virtual storage volumes. Each map links read/write requests from at least one network computing element to a respective virtual storage volume within the virtual storage device.

A memory storage apparatus, a memory controller and method for transmitting and identifying data streams are provided. The memory controller passes at least a portion of a data stream received from a host system to a smart card chip of the memory storage apparatus. Then, the host system accurately receives a response message from the smart card chip by executing a plurality of read commands. The memory controller is capable of adding a first verification code to a response data stream sent to the host system, and is capable of adding a write token to each of data segments of the response data stream. The host system confirms the accuracy of the response data stream by verifying the first verification code or by verifying the write token of each of the data segments.

A controller receives a request to perform a release space operation. A determination is made that a new discard scan has to be performed on a cache, in response to the received request to perform the release space operation. A determination is made as to how many task control blocks are to be allocated to the perform the new discard scan, based on how many task control blocks have already been allocated for performing one or more discard scans that are already in progress.

For a plurality of input/output (I/O) operations waiting to assemble complete data tracks from data segments, a process, separate from a process responsible for the data assembly into the complete data tracks, is initiated for waking a predetermined number of the waiting I/O operations.

A flash memory file system including a plurality of flash modules. Each of the plurality of flash modules includes a respective cache memory, a respective flash memory, and a respective flash controller in communication with the respective cache memory and the respective flash memory. A first flash module of the plurality of flash modules is configured to receive a file lookup message including a path name for file data stored on a second flash module of the plurality of flash modules. A third flash module of the plurality of flash modules is configured to select the second flash module based on the path name and a directory table, and generate a file metadata message responsive to the file lookup message. The file metadata message identifies the second flash module as containing the file data.

Systems, processors, and methods for keeping uncacheable data coherent. A processor includes a multi-level cache hierarchy, and uncacheable load memory operations can be cached at any level of the cache hierarchy. If an uncacheable load misses in the L2 cache, then allocation of the uncacheable load will be restricted to a subset of the ways of the L2 cache. If an uncacheable store memory operation hits in the L1 cache, then the hit cache line can be updated with the data from the memory operation. If the uncacheable store misses in the L1 cache, then the uncacheable store is sent to a core interface unit. Multiple contiguous store misses are merged into larger blocks of data in the core interface unit before being sent to the L2 cache.

Provided is a method and system for reducing duplicate buffers in buffer cache associated with a storage device. Reducing buffer duplication in a buffer cache includes accessing a file reference pointer associated with a file in a deduplicated filesystem when attempting to load a requested data block from the file into the buffer cache. To determine if the requested data block is already in the buffer cache, aspects of the invention compare a fingerprint that identifies the requested data block against one or more fingerprints identifying a corresponding one or more sharable data blocks in the buffer cache. A match between the fingerprint of the requested data block and the fingerprint from a sharable data block in the buffer cache indicates that the requested data block is already loaded in buffer cache. The sharable data block in buffer cache is used instead thereby reducing buffer duplication in the buffer cache.

A heterogeneous memory system includes a main memory arrangement, a first-level cache, and a memory management unit (MMU). The first-level cache includes an SRAM arrangement and a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the SRAM arrangement or the DRAM arrangement for storage of the first data and stores the first data in the selected one of the SRAM arrangement or DRAM arrangement. The MMU reads second data from one of the SRAM arrangement or DRAM arrangement and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.

Techniques for handling version information using a copy engine. In one embodiment, an apparatus comprises a copy engine configured to perform one or more operations associated with a block memory operation in response to a command. Examples of block memory operations may include copy, clear, move, and/or compress operations. In one embodiment, the copy engine is configured to handle version information associated with the block memory operation based on the command. The one or more operations may include operating on data in a cache and/or modifying entries in a memory. In one embodiment, the copy engine is configured to compare version information in the command with stored version information. The copy engine may overwrite or preserve version information based on the command. The copy engine may be a coprocessing element. The copy engine may be configured to maintain coherency with other copy engines and/or processing elements.

In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity to help determine whether a reallocation of resources between nodes may improve memory affinity for a logical partition or for the computer system. If so, the reallocation of resources is performed so memory affinity for the logical partition or computer system is improved. Memory affinity is computed relative to the physical layout of the resources according to a hardware domain hierarchy that includes a plurality of primary domains and a plurality of secondary domains.

A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit.

A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range.

An optical backup apparatus is provided and includes an optical storage device, an interface module to connect with at least one type of external storage medium, and a control unit to back up data from the external storage medium to the optical storage device in response to an external remote control operation.

Machine implemented method and system for generating a disaster recovery copy of an expandable storage volume having a namespace for storing information for accessing data objects stored at a data constituent volume is provided. A transfer operation for transferring a point in time copy of the expandable storage volume from a first location to a second location is generated. Information regarding the expandable storage volume from the first location is retrieved and a destination expandable storage volume is resized to match components of the expandable storage volume at the first location. Thereafter, the point in time copy of the expandable storage volume is transferred from the first location to the second location and configuration information regarding the point in time copy is copied from the first location to the second location.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

A method and computer-readable storage media are provided for rearranging data in physical memory units. In one embodiment, a method may include monitoring utilization counters. The method may further include, comparing the utilization counters for a match with an instance in a first table containing one or more instances when data may be rearranged in the physical memory units. The table may further include where the data should be relocated by a rearrangement. The method may also include, continuing to monitor the utilization counters if a match is not found with an instance in the first table. The method may further include, rearranging the data in the physical memory units if a match between the utilization counters and an instance in the first table is found.

Proposed are a management apparatus and a management method capable of improving the stability of the overall computer system. In a computer system which manages a storage area provided by each of a plurality of mutually connected storage apparatuses as a logical pool, provides to a host computer a virtual volume associated with the logical pool, and assigns a real storage area from the logical pool to the virtual volume when the host computer writes into the virtual volume, when a storage apparatus is added to the plurality of storage apparatuses, the host computer is controlled to switch the access path to the added storage apparatus.

Various systems and methods are described for configuring a logical data storage container. In one embodiment, an instruction to perform an operation to modify an attribute of the logical data storage container that is an abstraction of a plurality of pertinent storage containers is received. A translated instruction to perform a sub-operation associated with the operation is transmitted to each of a number of the plurality of pertinent storage containers. A level of success of the performing of the operation on the logical data storage container is detected based on a comparison of a threshold value to a level of success of the performing of the sub-operation on each of the number of the plurality of pertinent storage containers. A report of the detected level of success is communicated.

A dispersed storage (DS) unit for use within a dispersed storage network is capable of self-configuring using registry information provided to the DS unit. The registry information includes a slice name assignment indicating a range of slice names corresponding to a plurality of potential data slices of potential data objects to be stored in the DS unit. Based on the registry information, the DS unit allocates a portion of physical memory to store the potential data slices.

System and method for conversion of virtual machine files without requiring copying of the virtual machine payload (data) from one location to another location. By eliminating this step, applicant's invention significantly enhances the efficiency of the conversion process. In one embodiment, a file system or storage system provides indirections to locations of data elements stored on a persistent storage media. A source virtual machine file includes hypervisor metadata (HM) data elements in one hypervisor file format, and virtual machine payload (VMP) data elements. The source virtual machine file is converted by transforming the HM data elements of the source file to create destination HM data elements in a destination hypervisor format different from the source hypervisor format; maintaining the locations of the VMP data elements stored on the persistent storage media constant during the conversion from source to destination file formats without reading or writing the VMP data elements; and creating indirections to reference the destination HM data elements in the destination hypervisor format and the existing stored VMP data elements.

The invention pertains to a memory management unit for a microprocessor system, the memory management unit being connected or connectable to at least one processor core of the microprocessor system and being connected or connectable to a physical memory of the microprocessor system. The memory management unit is adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware The memory management unit comprises a first register table indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other; a second register table indicating an allowed address range of physical addresses accessible to a process running in or under supervisor mode; wherein the memory management unit is adapted to prevent write access to the second register table by a process not in hypervisor mode. The memory management unit is further adapted to allow write access to the first register table of a process running in or under supervisor mode to reconfigure the physical address information indicated in the first register table with memory mapping information relating to at least one physical address, if the at least one physical address is in the allowed address range, and to prevent write access to the first register table of the process running in or under supervisor mode if the at least one physical address is not in the allowed address range. The invention also pertains to a microprocessor system and a method for managing memory.

Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.

A prefetch optimizer tool for an information handling system (IHS) may improve effective memory access time by controlling both hardware prefetch operations and software prefetch operations. The prefetch optimizer tool selectively disables prefetch instructions in an instruction sequence of interest within an application. The tool measures execution times of the instruction sequence of interest when different prefetch instructions are disabled. The tool may hold hardware prefetch depth constant while cycling through disabling different prefetch instructions and taking corresponding execution time measurements. Alternatively, for each disabled prefetch instruction in the instruction sequence of interest, the tool may cycle through different hardware prefetch depths and take corresponding execution time measurements at each hardware prefetch depth. The tool selects a combination of hardware prefetch depth and prefetch instruction disablement that may improve the execution time in comparison with a baseline execution time.

A data processing entity that includes a mass memory with a plurality of memory locations for storing memory blocks. Each of a plurality of software images includes a plurality of memory blocks with corresponding image addresses within the software image. The memory blocks of software images stored in boot locations of a current software image are relocated. The boot blocks of the current software image are stored into the corresponding boot locations. The data processing entity is booted from the boot blocks of the current software image in the corresponding boot locations, thereby loading the access function. Each request to access a selected memory block of the current software image is served by the access function, with the access function accessing the selected memory block in the associated memory location provided by the control structure.

Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.

A method and system for dynamic distributed data caching is presented. The system includes one or more peer members and a master member. The master member and the one or more peer members form cache community for data storage. The master member is operable to select one of the one or more peer members to become a new master member. The master member is operable to update a peer list for the cache community by removing itself from the peer list. The master member is operable to send a nominate master message and an updated peer list to a peer member selected by the master member to become the new master member.

The present invention provides α-keto alkylperacids and methods for producing and using the same. In particular, α-keto alkylperacids are useful as antimicrobial agents.

A reaction system suitable for production of a methionine salt contains a reactive rectification column containing a weir having a height of 100 mm or more.

According to one embodiment, an actinic-ray- or radiation-sensitive resin composition includes any of the compounds (A) of general formula (I) below that when exposed to actinic rays or radiation, generates an acid and a resin (B) whose rate of dissolution into an alkali developer is increased by the action of an acid. (The characters used in general formula (I) have the meanings mentioned in the description.)

The invention features methods and compositions for the synthesis of multimerizing agents. An exemplary method for producing AP20187 may comprise: (a) coupling 2-N,Ndimethylaminomethyl-1,3-diaminopropane with AP20792 to produce the dimeric alcohol, AP20793; and (b) coupling the AP20793 so produced with API7362 to yield AP20187. In particular embodiments, the method further includes the step of producing API7362 by coupling API7360 with methyl-L-pipecolic acid, or a salt thereof.

An ammonium hydroxyfluoroalkanesulfinate is obtained by using an organic base while sulfinating a bromofluoroalcohol with a sulfinating agent. An ammonium hydroxyfluoroalkanesulfonate is obtained by oxidizing the ammonium hydroxyfluoroalkanesulfinate. An onium fluoroalkanesulfonate is obtained by converting the ammonium hydroxyfluoroalkanesulfonate into an onium salt through esterification. This onium fluoroalkanesulfonate is useful as a photoacid generator in chemically amplified resists and the like.

A carbonylation process for making acetic acid using a metallic co-catalyst composition, effective as a rhodium stabilizer and/or rate promoter, at molar ratios of metal/rhodium of about 0.5 to 40. The process includes reacting methanol with carbon monoxide in the presence of a rhodium-based catalytic metal complex with about 1 to 20 weight percent methyl iodide, less than about 8 weight % water and about 0.5 to about 30 weight percent methyl acetate. The crude acetic acid is flashed and further purified.

The present invention relates to a method for increasing L-methionine productivity and organic acid productivity. More particularly, the present invention relates to a method which involves adding a mixture containing methyl mercaptan and dimethyl sulfide at a appropriate ratio to O-acetyl homoserine or O-succinyl homoserine and to an enzyme having an activity of converting methionine precursor into L-methionine, so as to perform an enzyme reaction, to thereby improve the conversion rate of L-methionine and organic acid from the L-methionine precursor, and thus increasing L-methionine yield as compared to conventional method.