A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. Test wrappers may also be configured to test multiple IP blocks comprising a test partition.

A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.

A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. This encoding scheme allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for an implementation adapted to shift a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.

A communication device includes a storage unit to store quotients and remainders associated with multiplication values obtained by multiplying a specified integer number, which is expressed in a form of (2β+α) where β is a positive integer number and α is a positive integer number other than integral multiples of 2, respectively, the quotients and the remainders being obtained by dividing the multiplication values by 2β, respectively, a first unit to divide a dividend by 2βand calculate a quotient and a remainder, a second unit to obtain a quotient, which corresponds to the remainder from the storage unit, and a third unit to determine that the data length of the packet data is normal, when a combination of the quotient and the remainder calculated by the first unit is in the storage unit.

A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.

A bridge circuit of an embodiment includes: a command transfer portion which is configured by wired logic into which a host controller capable of sending a command that corresponds to each of a plurality of devices inputs the command, and which is configured to transfer the inputted command to the plurality of devices; a command analysis portion which is configured by wired logic, and which is configured to analyze the command from the host controller; and a response reply portion which is configured by wired logic, and which is capable of reading out a response based on an analysis result of the command analysis portion from a register that holds a response corresponding to the command and sending the response to the host controller.

In a multiprocessor system, in general, a processor assigned with a larger amount of tasks is apt to perform a larger amount of communication with other processors assigned with tasks, than a processor assigned with a smaller amount of tasks. Thus in order for each processor to be able to perform the routing process efficiently, tasks are assigned such that, when there are a first processor and a second processor, the number of processors each assigned with one or more tasks and directly connected with the second processor being smaller than the number of processors each assigned with one or more tasks and directly connected with the first processor, the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor.

A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.

This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.

An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

A method of creating a datasheet includes obtaining integrated circuit data from at least one data source, creating a data structure including the integrated circuit data obtained from the at least one data source, and creating a datasheet using data contained in the data structure. The datasheet is created in a human-readable format.

A circuit-design support method includes obtaining information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output via the logic circuit; obtaining information concerning a control circuit that has a first flip-flop for scanning and that can control a value of a given signal line by a value set by the first flip-flop; selecting, based on the circuit information, a second flip-flop at an output destination of a signal from the logic circuit, among second flip-flops of the circuit; and generating, based on the control circuit information, information indicating a serial connection of the control circuit between an output source of the signal of the given signal line and the given signal line and a connection of a data input terminal of the first flip-flop and an output terminal of the selected second flip-flop.

A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.

A layout-legalizing system modifies a portion of a circuit layout that is selected by a user to generate a modified portion that satisfies a set of technology constraints and a set of design constraints. The system receives as input the set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes. The system also receives a set of design constraints from the user which restricts how objects in the portion of the circuit layout can be modified to satisfy the set of technology constraints. The system can further receive a selection input from the user which identifies the portion of the circuit layout which is to be legalized. The system then modifies the identified portion of the circuit layout to obtain a modified portion which satisfies the set of design constraints and at least a subset of the set of technology constraints.

Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.

A phosphazene compound having a vinyl group is manufactured by a reaction between a vinyl compound and a phosphazene compound having a hydroxyl group and added to a resin composition for manufacturing a prepreg or a resin film so as to be applicable to copper-clad laminates and printed circuit boards to thereby achieve satisfactory circuit laminate properties, namely low coefficient of thermal expansion, low dielectric properties, heat resistant, fire resistant, and halogen-free.

A method and device for synchronizing the time between at least two integrated circuits (201, 202), which receive the same pulse signal. In the integrated circuits (201, 202) a counter (204, 206) is used to count the number of pulses in the received pulse signal to synchronize the common time between said integrated circuits.

The present invention provides for an electronic device having cryptographic computation means arranged to generate cryptographic data within the device for enhancing security of communications therewith, the device including an onboard power supplying means arranged to provide for the driving of the said cryptographic computational means, and so as to provide a device by way of a manufacturing phase and a post manufacturing phase arranged for distribution and/or marketing of the device, and wherein the step of generating the cryptographic data occurs during the post manufacturing phase.

An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.

Disclosed are various embodiments involving correction of signals generated by a crystal oscillator. An age of an integrated circuit or a time of use of the integrated circuit may be determined. A signal generated from a crystal of the integrated circuit may be modified based at least in part on the determined age of the integrated circuit or the determined time of use of the integrated circuit.

Aspects of the invention provide for reducing power consumption during manufacturing testing of an IC. In one embodiment, aspects of the invention include a method for reducing power consumption during a manufacturing test of an integrated circuit (IC), the method including: providing a plurality of domains, each domain associated with a clock phase; grouping, based on each domain, a first plurality of scan chains into a first test group; grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously; and performing the manufacturing test of the IC.

This invention is directed to a polymer thick film UV-curable thermoformable dielectric composition. Dielectrics made from the composition can be used in various electronic applications to protect electrical elements and particularly to insulate and protect both the conductive thermoformable silver and the polycarbonate substrate below it in capacitive switch applications. The thermoformed capacitive switch circuit may be subsequently subjected to an injection molding process.

Method and system are disclosed for statistical circuit simulation. In one embodiment, a computer implemented method for statistical circuit simulation includes providing descriptions of a circuit for simulation, wherein the descriptions include variations of statistical parameters of the circuit, partitioning the circuit into groups of netlists according to variations of statistical parameters of the circuit, simulating the groups of netlists using a plurality of processors in parallel to generate a plurality of output data files, and storing the plurality of output data files in a memory. The method of partitioning the circuit into groups of netlists includes forming the groups of netlists to be simulated in a single instruction multiple data environment, and forming the groups of netlists according to proximity of variations of statistical parameters of the circuit.

The present invention aims to simulate a response more similar to a actual machine while inhibiting load increase in analog operation. Program configuration of the present invention is a component of a simulation program for circuit design, which is executed by a computer. The computer includes an operation portion, a storage portion, a manipulation portion, and a display portion, so that the computer exerts a function of a circuit design simulator, and as a macro model of an operational amplifier for use in the circuit design simulator, enabling the computer to act by simulating a response of the operational amplifier on the circuit design simulator. The macro model of the operational amplifier includes a control portion (LMT1) for generating output exception in the event of input exception or power supply exception of the operational amplifier.

Methods and apparatuses for circuit design are described. In one embodiment, the method comprises determining a distribution of nets of a circuit, the distribution of the nets comprising numbers of blocks that each of the nets has in each of a plurality of partitions of the circuit in a partitioning solution, moving a first block of the circuit from a source partition to a destination partition to modify the partitioning solution, and updating the distribution of the nets after the moving.

An adhesion promotion process and composition for enhancing adhesion between a copper conducting layer and a dielectric material during manufacture of a printed circuit board. The composition contains a corrosion inhibitor, an inorganic acid, and an alcohol which is effective to increase copper-loading in the composition.

A method and system for improving high excess air combustion system efficiency, including induration furnaces, using a re-routing of flue gas within the system by gas recirculation. Flue gas is drawn from hot system zones including zones near the stack, for re-introduction into the process whereby the heat recovery partially replaces fuel input. At least one pre-combustion drying zone, at least one combustion zone, and at least a first cooling zone exist in these furnaces. At least one exhaust gas outlet is provided to each pre-combustion drying and combustion zone. At least part of the gaseous flow from each system zone exhaust outlet is selectively delivered to an overall system exhaust, the remaining flow being selectively delivered via recirculation to cooling zones. Recirculation flow is adjusted to meet required system temperatures and pressures. The method and system provide efficiency improvements, reducing fuel requirements and greenhouse gas emissions.

Ball screws are described that may be incorporated into other devices such as a pulley assembly or a differential device. The ball screws include a threaded shaft defining a central longitudinal axis with a threaded nut threadedly coupled thereto to define at least one track in between them. Each track forms a continuous loop around an infield protrusion and is filled with a plurality of rolling elements filling. Each rolling element has the same radius from the central longitudinal axis such that the nut can rotate at higher speeds without the rolling elements locking up as a result of centripetal force.

A method for making a circuit board includes separating a plurality of versatile circuit boards from a collective board by cutting a connecting portion of the collective board, the plurality of versatile circuit boards being connected each other via the connecting portion, and cutting a part of a wiring formed on each of the plurality of versatile circuit boards to produce the circuit board. The cutting of the part of the wiring is conducted within the separating of the plurality of versatile circuit boards.

An optical transceiver of one embodiment includes a transmitter optical subassembly to transmit an optical signal, a receiver optical subassembly to receive an optical signal, a mother board, a daughter board, and a housing. The mother board mounts electronic circuits that electrically communicate with the optical transmitter optical subassembly and the receiver optical subassembly. The daughter board mounts other electronic circuits that electrically communicate with the optical transmitter optical subassembly and the receiver optical subassembly. The daughter board has an extra area mounting a portion of the other electronic circuits. The housing defines a space for installing the optical transmitter optical subassembly, the receiver optical subassembly, the mother board, and the daughter board. The extra area is disposed outside the space.

A switching circuit (400) comprising an inductive component (406) including at least one winding; and a switch (404) is configured to transfer power from a voltage source (402) to the inductive component (406) in accordance with a switch control signal (412). The switching circuit (400) also comprises a controller (408) configured to integrate the voltage across the inductive component (406) in order to generate a signal representative of magnetic flux in the inductive component (406); and use the signal representative of the magnetic flux in the inductive component to account for a peak magnetization current value in order to control the switch (404).

Embodiments include circuits and methods to determine peak current for current regulation. A control signal circuit monitors a current on the primary side of a transformer based a turn on time of a switch coupled to the primary side. The control signal circuit determines whether the monitored current exceeds an over-current protection threshold, and determines a duration that the monitored current exceeds the over-current protection threshold. The control signal circuit determines a peak primary current in the primary side based on the over-current protection threshold, the duration that the monitored current exceeds the over-current protection threshold, and the turn on time of the switch. The control signal circuit controls the turn on time for the switch based on the determined peak primary current.

A noise suppression circuit for a power adapter is disclosed. The noise suppression circuit can reduce or eliminate adapter-induced noise that could interfere with an electronic device powered by the adapter. In one example, the noise suppression circuit can include an active circuit to detect and attenuate or cancel the induced noise. In another example, the noise suppression circuit can include an RLC circuit in parallel with the adapter choke to suppress the induced noise at the operating frequencies of the powered electronic device. In still another example, the noise suppression circuit can include a modified adapter Y capacitor connection so as to bypass the adapter choke, thereby reducing or eliminating the choke's induced noise.

A power source circuit includes a switching circuit 4 that converts a direct current voltage obtained by converting an alternating voltage from an alternating power source input through a pair of power supply lines 2 and 3 into a predetermined direct current voltage by a switching operation. A fuse 5 is provided on one power supply line 2. A series circuit 9 including a first line bypass capacitor 7 and a resistor element 8 is connected between one power supply line 2 and a ground 6. A second line bypass capacitor 10 is connected between the other power supply line 3 and the ground 6. Imbalance of the circuit by an excess current protection element is prevented to reduce common mode noise.

Systems and methods are provided for pre-charging the DC bus on a motor drive. Pre-charging techniques involve pre-charge circuitry including a manual switch, an automatic switch, and pre-charge control circuitry to switch the automatic switch between pre-charge and pre-charge bypass modes in response to an initialized pre-charge operation, input voltage sags, and so forth. In some embodiments, the pre-charge operation may be initialized by switching the manual switch closed. In some embodiments, the pre-charge operation may also be initialized by a detected voltage sag on the DC bus. The pre-charge circuitry may also be configured to disconnect to isolate a motor drive from the common DC bus under certain fault conditions.

A flex circuit including a dual sided interconnect structure to connect electrical components on a head or suspension assembly to head circuitry is described. The dual sided interconnect structure described has application for providing an electrical connection to one or more transducer elements on a slider and one or more elements of a heat assisted magnetic recording HAMR unit. In an illustrated embodiment, a flexible structure or insulating base layer includes one or more slider and heat assisted magnetic recording traces coupled to one or more slider or HAMR bond pads on an interconnect portion. As disclosed, the slider bond pads are on the obverse side of the flexible structure and the HAMR bond pads include a reverse side bonding surface to form reverse side bond pads to connect to one or more electrical or heating elements on the HAMR unit.

The invention relates to an electronic circuit and a method for feeding power to at least one electrode of an alternating-current electric-arc furnace, particularly for melting metal. Known circuits of this type typically comprise a series connection with a transformer for providing a supply voltage for the electric-arc furnace from a power grid (1) and a AC power controller (8) connected between the transformer (6) and the electrode (11) for regulating the current through the electrode (11). According to the invention, a further development for such electronic circuits is proposed, which development has a simple design, is inexpensive and prevents overload of the AC power controller (8) even in operating modes of the electric-arc furnaces at high electrode currents. This further development provides to bypass the AC power controller with a bypass switch (9) that is opened or closed with the help of a controller as a function of the amount of current flowing through the electrode (11).

A variable-voltage variable-frequency power source for an electric motor that drives a re-circulation pump for a boiling water nuclear reactor. The power source has a semiconductor electric power converter and a speed controller for controlling the semiconductor electric power converter. When a part of the semiconductor electric power converter comes into an inoperative state, that part is electrically disconnected, and the variable-voltage variable-frequency power source temporarily stops outputting power, thereby idling the re-circulation pump. Thereafter, the power source re-starts outputting power before the re-circulation pump completely stops. Thus, the re-circulation pump keeps operating, without stopping.

One form of the invention is directed to an apparatus that comprises step-down circuitry to better match impedance between an input and an output that includes a number of stages each electrically coupled to another and each including a charge storage device. The circuitry further includes a number of switching devices operable in a first electrical connectivity state to connect the charge storage device of each of the stages in series to receive electrical charge from the input and in a second electrical connectivity state opposite the first state to connect the charge storage device of each of the stages in parallel to discharge electricity through the output. This circuitry can be used in connection with a radioisotopic conversion cell.

There is provided a flexible circuit board capable of preventing corrosion and elution of a conductor layer constituting a current collector even under high-temperature and high-voltage working conditions while achieving sufficient electric connection with an MEA. A flexible circuit board having a current collector of a fuel cell provided thereon includes an insulating flexible base material 1, a plurality of openings 5 that supply fuel or air, the openings 5 being provided in a specified region so as to penetrate through the flexible base material 1 in a thickness direction, a plating film 6 that constitutes the current collector, the plating film 6 being formed on front and back surfaces of the flexible base material 1 in the specified region and on inner walls of the openings 5, a surface treatment film 9 formed on the plating film 6 and having corrosion resistance higher than that of the plating film.

A backlight module includes a carrier plate, a plurality of light sources, a plurality of circular Fresnel lenses, and a plurality of cylinder Fresnel lenses. The circular Fresnel lenses are arranged in an array form on the carrier plate. The light sources correspond to the circular Fresnel lenses, and are located in a side away from the carrier plate. One cylinder Fresnel lens is set between every two adjacent circular Fresnel lenses. A length direction of each cylinder Fresnel lens is parallel to an extending direction of adjacent column of the circular Fresnel lens. The circular and cylinder Fresnel lenses are used to reflect a light incident into their surfaces, and to increase an emission angle of the reflected light.

The present invention provides a method and system for secured remote provisioning of a universal integrated circuit card of a user equipment. A system includes a user equipment for initiating a request for remote provisioning of an universal integrated circuit card (UICC) in the user equipment, where the request for remote provisioning includes a machine identifier (MID) associated with the user equipment and a public land mobile network (PLMN) identifier (ID) associated with an network operator. The system also includes at least one shared key management server for dynamically generating security keys and an operator shared key using the security keys, the MID. Moreover, the system includes an operator network for generating a subscription key using the operator shared key and an international mobile subscriber identity (IMSI), and provisioning the IMSI in a secured manner to the UICC of the user equipment using the security keys.

An interesting section identifying device for identifying an interesting section of a video file based on an audio signal included in the video file, the interesting section being a section in which a user is estimated to express interest, includes an interesting section candidate extracting unit that extracts an interesting section candidate from the video file, the interesting section candidate being a candidate for the interesting section, a detailed structure determining unit that determines whether the interesting section candidate includes a specific detailed structure, and an interesting section identifying unit that identifies the interesting section by analyzing a specific section when the detailed structure determining unit determines that the interesting section candidate includes the detailed structure, the specific section including the detailed structure and being shorter than the interesting section candidate.

A device and method are provided for saving power and electricity in a charging device such for external power supplies and battery chargers having a primary circuit and a secondary circuit where a switch is located in the primary circuit and a current sensing device in the secondary circuit to sense when there is a drop in current in the secondary circuit or no current in the secondary circuit because the load or a cell phone is charged and when this occurs the switch in the primary circuit is opened and the primary circuit no longer draws power from the source of power until the switch in the primary circuit is closed by activation of a user of the charging device.

Embodiments include systems and methods of powering a mobile device using a sink device. The method may include detecting a coupling of the mobile device to the sink device and transmitting an acknowledgement in response to a query, the acknowledgement confirming that the sink device has charging capability. Power may be selectively provided in response to the power request. According to some embodiments, the method includes transmitting a query by a communications transmitter to determine if a sink device has charging capability, and deactivating a driver for a power line and transmitting a power request using the communications transmitter in response to receiving an acknowledgement signal from the sink device. The method may further include selectively providing power received from the sink device to a charging circuit of the mobile device. The mobile device may include an HDMI transmitter for communicating through a transmission line to an HDMI sink device.

A boost converter with a multiple input and with improved efficiency has two or more inputs. A DC voltage source can be connected to each input. A common output carries a DC voltage whose value is greater than or equal to that of the input voltages. The common output is in each case connected to each of the plurality of inputs via a positive lead branch and a negative lead branch. At least one inductor is arranged in the positive lead branch and/or the negative lead branch from each input, and at least one rectification element is arranged in the positive lead branch and/or the negative lead branch from each input. Furthermore, the inputs can be connected in series by means of two or more switching elements via the inductors, wherein at least two of the inductors can in each case be connected in parallel.

An inverter circuit contains a first and second DC sources for providing a DC voltage, a common step-up converter for boosting the DC voltage, an intermediate circuit capacitor connected between the outputs of the common step-up converter, and an inverter for converting the DC voltage provided by the capacitor into an AC voltage. The common step-up converter contains a series circuit having a first inductance and a first rectifier element and is connected between an output of the first DC source and one side of the intermediate circuit capacitor as well as a series circuit which includes a second inductance and a second rectifier element and is connected between an output of the second DC source and another side of the intermediate circuit capacitor. The common step-up converter further contains a common switching element which is connected between the first and second DC sources.