Improved understanding of the coupled natural-human coastal system will help promote resilience of coastal communities and ecosystems under rapidly changing environmental conditions and support informed decision-making, says a new report from the National Academies of Sciences, Engineering, and Medicine.

Cold-chain management—an essential aspect of many snack and bakery operations today—has entered a brave new world characterized by sophisticated temperature monitoring and tracking technology connected by the Internet of Things (IoT).

Resolution 93 - (Hammamet, 2016) - Interconnection of 4G, IMT-2020 networks and beyond

Designations for interconnections among operators' networks

Quality of service norms for time-division multiplexing interconnection between telecom networks

Nominal amplitude of video signals at video interconnection points

Nominal amplitude of video signals at video interconnection points

Guidelines for international short message service (SMS) interconnection

ITU-T D.170 - Supplement on guidelines for contents of an international interconnection agreement

Framework for interconnection between VoLTE-based network and other networks supporting emergency telecommunications service (ETS)

Application of the ISDN User Part of CCITT signalling system No. 7 for international ISDN interconnections

Signalling requirements and architecture for interconnection between trustable network entities

The interconnected impacts of the Iraq war Expert comment LJefferson 22 March 2023

Relying on weak intelligence for invading Iraq has had a negative impact on US and UK credibility with several consequences that persist to this day.

20 years on from the fateful decision to invade Iraq, it is generally accepted that the US and UK governments overstated the evidence available for them to justify military action. The central claim to defend invading Iraq was that the country had continued its illicit nuclear weapons programme and had retained illegal stockpiles of biological and chemical weapons. None of these claims supported an imminent threat justification nor could any hidden caches of WMD be found by the US Iraq Survey Group after the invasion.  

In the US, President George W. Bush and Vice President Dick Cheney hinted at additional evidence which could not be shared publicly to suggest that if only people knew what the government knew, they would agree that Iraq posed a significant threat to the West and needed to be disarmed.

In the UK, the Blair government acted similarly, focusing on a narrow interpretation of the evidence provided by the intelligence services and ignoring many of the dire warnings offered by academics and other experts. The Chilcot Inquiry found that the Blair government greatly exaggerated the threat Iraq posed to the UK, and that government arguments were based on the prime minister’s personal beliefs, as well as his promise to President Bush to support the US invasion. 

Relying on inadequate information and a biased analysis for invading Iraq has had a negative impact on US and UK credibility in the international security policy environment and domestically with ramifications that persist to this day.  

Impacts on soft power and trust

The invasion had an impact on US and UK soft power due to negative perceptions of the decision to go to war and the competence of the UK and US: public opinion polling by the Pew Center showed that perceptions of the US declined significantly as a result of the invasion of Iraq, especially in the Middle East and Central Asia.

This is undoubtedly a challenge for the US, but arguably an even bigger challenge for the UK, which due to its size and power relies much more on diplomacy and coalition-building in order to achieve its goals within various international treaty frameworks.   

Over nearly two decades, the US and the UK no longer seemed to enjoy the same foundation of trust, even with close allies, as they did previously. This changed in February 2022.

Towards the end of 2021, both the US and the UK were sounding the alarm about an impending Russian invasion of Ukraine based on information and analysis from their intelligence services. Despite the amassing of Russian troops, tanks and artillery on the border clearly visible from the air and by satellite imagery, several allies remained unconvinced until the invasion happened.  

This was in part due to their own assessments which indicated that Russia would stop short of an invasion, and in part because allies were unwilling to take US and UK statements on faith, without being able to assess the information themselves.

US officials found this frustrating as it meant that NATO and the EU were slower off the mark with support for Ukraine than they might otherwise have been. However, the accuracy of the US/UK intelligence on Russia’s invasion, coupled with their sharing it openly, may well have restored faith in their capabilities and analysis.  

A more open approach to intelligence  

Over the last few years, there seems to have been a change in accepted practice regarding sharing and using intelligence. The UK Ministry of Defence has taken a much more open approach to intelligence in the war in Ukraine, sharing the most recent defence information publicly in order to counter Russian disinformation.  

This is a positive step to ensure that intelligence can be discussed and assessed critically. Being more open about secret intelligence may also be linked to the increasing capabilities of open-source intelligence (OSINT). Non-governmental and international organizations and the media all now have access to data from, for example, imaging satellites and can independently verify information coming from governments. 

Perceived double standards 

A reduction of trust in US and UK intelligence was not the only impact of the invasion of Iraq. Russia and China have repeatedly called out the US and UK for acting without a second UN Security Council mandate. Putin uses the decision to invade Iraq, as well as the NATO humanitarian intervention in Kosovo, to justify Russia’s actions in Crimea. He invokes parallel language to spread disinformation about a ‘responsibility to protect life’ of the (‘ethnically Russian’) Crimean population. Russia has also repeatedly used the WMD trope to create false narratives around Ukrainian biosecurity laboratories to justify Russian military actions against Ukraine.  

Deciding to invade Iraq under what turned out to be a false pretext has weakened the application of the international rule of law and has led to a perceived double standard whereby powerful states can use UN processes in their favour, or completely disregard them if they do not deliver their goals.

As the Chilcot Inquiry found, there was very little preparation for the post-invasion period either in the US or the UK. Confirmation bias led not only to trusting shaky intelligence but also to believing in a best-case scenario and a ‘relatively benign security environment’ once the invasion had prevailed. Mismanaging the country’s occupation afterwards also led to the perception that the UK and US are less competent than projected. 

Problems for the international order  

The Iraq War has left many smaller and medium-sized states outside Europe and North America with the impression that powerful states are not committed to an equitable international system and instead will bend the rules to suit them while nonetheless holding other states to account. This dynamic poses a serious problem for the international system. 

It opens the door to ‘whataboutism’ in Russia’s false justifications for invading Ukraine and undermines faith in international law, destabilizing the international order in the longer term. Beyond the immediate challenges of dealing with the war in Ukraine, reforming and strengthening the international order to make it more equitable will be one of the most significant challenges the US and UK will face over the next decade. 

A trust deficit  

Domestically, for already disappointed citizens, the deceit over intelligence it is yet another piece of evidence which suggests that their government is not trustworthy and may not have their best interests at heart. This has profound implications for US and UK democracies, making it harder for governments to counter citizens’ susceptibilities to disinformation campaigns. 

IEEE / Institute of Electrical and Electronics Engineers Incorporated

U.S. energy regulators rejected an amended interconnection agreement for an Amazon data centre connected directly to a nuclear power plant in Pennsylvania

The Dutch education system and the skills of the Dutch population are very strong overall. But there are concerns that too many people in the Netherlands are not developing the “right” skills to succeed or taking sufficient responsibility for maintaining and further developing their skills in adulthood.

Improved understanding of the coupled natural-human coastal system will help promote resilience of coastal communities and ecosystems under rapidly changing environmental conditions and support informed decision-making, says a new report from the National Academies of Sciences, Engineering, and Medicine.

In this paper we analyze a continuous version of the maximal covering location problem, in which the facilities are required to be interconnected by means of a graph structure in which two facilities are allowed to be linked if a given distance is not exceed. We provide a mathematical programming framework for the problem and different resolution strategies. First, we propose a Mixed Integer Non Linear Programming formulation, and derive properties of the problem that allow us to project the continuous variables out avoiding the nonlinear constraints, resulting in an equivalent pure integer programming formulation. Since the number of constraints in the integer programming formulation is large and the constraints are, in general, difficult to handle, we propose two branch-&-cut approaches that avoid the complete enumeration of the constraints resulting in more efficient procedures. We report the results of an extensive battery of computational experiments comparing the performance of the different approaches.

A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane.

A via disposition information acquiring unit acquires via disposition information indicating a disposition of the plurality of first vias (212). A second conductor information acquiring unit acquires second conductor information indicating disposition positions of a plurality of second conductors (232) repeatedly disposed in the second conductor layer (230). A via extracting unit extracts an extraction via with respect to each of the plurality of second conductors (232). The extraction via is each of the first vias (212) overlapping the second conductor (232). A via selecting unit selects a selection via with respect to each of the plurality of second conductors (232). The selection via is each of first vias (212) selected in a predetermined number from the extraction vias. An opening introducing unit introduces a first opening (234) to each of the plurality of second conductors (232). The first opening (234) overlaps the extraction via not selected by the via selecting unit in plan view.

A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.

Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

A method including depositing an alloying layer along a sidewall of an opening and in direct contact with a seed layer, the alloying layer includes a crystalline structure that cannot serve as a seed for plating a conductive material, exposing the opening to an electroplating solution including the conductive material, the conductive material is not present in the alloying layer, applying an electrical potential to a cathode causing the conductive material to deposit from the electroplating solution onto the cathode exposed at the bottom of the opening and causing the opening to fill with the conductive material, the cathode includes an exposed portion of the seed layer and excludes the alloying layer, and forming a first intermetallic compound along an intersection between the alloying layer and the conductive material, the first intermetallic compound is formed as a precipitate within a solid solution of the alloying layer and the conductive material.

The invention provides optical interconnects of data-processing cores of multicore chips by means of digital planar holographic microchips. The method comprises delivering “N” laser lights to “N” data-processing cores on the host chip, coding the obtained optical signals by modulating them with the core-generated data, and then delivering the modulated and coded optical signals to a holographic microchip formed on the same substrate of the host chip as the data-processing cores, splitting the modulated and coded optical signals into (N−1)N modulated optical copy signals, delivering the copy signals to all data-processing cores except the one that generates the copy signals, and decoding the data obtained from the output signals delivered to the processing cores by the receivers. The method is efficient in that it allows replacing electrical interconnects between the cores with optical interconnects and can be matched to current semiconductor production technology.

A flex circuit including a dual sided interconnect structure to connect electrical components on a head or suspension assembly to head circuitry is described. The dual sided interconnect structure described has application for providing an electrical connection to one or more transducer elements on a slider and one or more elements of a heat assisted magnetic recording HAMR unit. In an illustrated embodiment, a flexible structure or insulating base layer includes one or more slider and heat assisted magnetic recording traces coupled to one or more slider or HAMR bond pads on an interconnect portion. As disclosed, the slider bond pads are on the obverse side of the flexible structure and the HAMR bond pads include a reverse side bonding surface to form reverse side bond pads to connect to one or more electrical or heating elements on the HAMR unit.

A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width.

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.

A back electrode type solar cell in which a no-electrode-formed region where no electrode is placed is provided in a part of a peripheral portion of a back surface of the back electrode type solar cell such that a line connecting end portions of a plurality of electrodes to one another includes a partially inwardly recessed region and the no-electrode-formed region is located adjacent to each of an electrode for n-type and an electrode for p-type adjacent to each other, a solar cell module, a method of manufacturing a back electrode type solar cell with interconnection sheet, and a method of manufacturing a solar cell module are provided.

An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

A port of a first device includes remote device detection logic to detect, on a link, a remote second device, determine, from a voltage generated at the port, whether the second device is direct current (DC)-coupled or alternating current (AC)-coupled to the link, and select one of first settings or second settings to be applied at the port in communications over the link with the second device based on whether the second device is DC-coupled or AC-coupled.

Presented herein are an interconnect structure and method for forming the same. The interconnect structure includes a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer including a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 μm.

A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

The present invention provides a kiln for the combustion of agricultural waste. The kiln includes a central cylindrical combustion chamber. The central cylindrical combustion chamber includes a system for the control of combustion air to the combustion chamber. The kiln includes a second concentric cylinder surrounding the central cylindrical combustion chamber. The second concentric cylinder includes a system for the flow of cooling water through the first annulus between the central cylindrical combustion chamber and the second concentric cylinder. The kiln includes a system for the feeding of the agricultural waste into the central combustion chamber. The kiln includes a temperature sensing device to measure and display the temperature within the central combustion chamber during the combustion of the agricultural waste. The kiln includes a system for the recovery of ash from the kiln. In operation, the temperature of combustion is controlled to between 550° C. and 650° C. by a combination of increasing the supply of combustion air when the temperature in the central combustion chamber falls to near 550° C. and the introduction of cooling flowing water when the temperature in the central combustion chamber approaches 600° C.

In an example arrangement an apparatus includes a semiconductor substrate having a front side surface including circuitry and a backside surface opposing the front side surface; a plurality of metal conductors formed over a front side surface of the semiconductor substrate; at least one cavity opening etched in a backside surface of the semiconductor substrate; and a radiator formed in a portion of the metal conductors and configured to radiate signals through the cavity opening in the backside surface. Methods and additional apparatus arrangements are also disclosed.

A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

The present invention is to provide a chassis switch, which comprises a chassis for accommodating a designated number of line cards therein; a backplane installed on the back side of the chassis and having a plurality of connectors disposed thereon; at least one line card plugged into one of the connectors corresponding thereto via a front side of the chassis and each having an access switch chip adapted to switch local network signals and an interconnect switch chip adapted to switch the signals between ports of the at least one line card; and a loop adapted to connect the corresponding ports of the access switch chip and the interconnect switch chip respectively through the connectors, so as to enable each line card plugged into the chassis switch to perform a local network switching function and a switching function between the at least one line card.

DAILY BRIEFING: Police allege a motorcyclist was doing more than 200km/h, and Tasmania's Basslink interconnector will be back up and running by Monday.

Dans le cadre de sa conférence InterConnect qui se tient à Las Vegas du 19 a 23 mars, à laquelle assistent 20 000 clients, développeurs et partenaires issus du monde entier, IBM annonce :

Invitation Only Research Event

Event participants