In a driving circuit, one output circuit has a scanning signal line, a first transistor which controls electrical connection between the scanning signal line and a clock signal line which has a gate connected to a first node, the first node which is at an active potential in a first time period including a time period during which the active potential is output to the scanning signal line, a second transistor which electrically connects the first node and an inactive signal line which has a potential to open the transistor in a second time period other than the first time period, and the second transistor has a gate connected to a second node, wherein the second node has two kinds of timings to be charged for retaining the active potential.

A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal.

A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.

A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

A stage constituent circuit of a display device drive circuit includes a first-node to a third-node, a thin-film transistor that changes a potential of a scanning signal toward a VDD potential when a potential of the first-node is in a HIGH level, a thin-film transistor that changes a potential of a different stage control signal toward a potential of a clock when a potential of the second-node is in the HIGH level, a capacitor between the first-node and the second-node, and a capacitor between the second-node and the third-node. The potential of the first-node is raised on the basis of a different stage control signal output from the stage constituent circuit in the different stage, and then the potential of the second-node and a potential of the third-node are sequentially raised. Herein, an amplitude of the clock is set to be smaller than an amplitude of the scanning signal.

To provide a pulse signal output circuit and a shift register which have lower power consumption, are not easily changed over time, and have a longer lifetime. A pulse signal output circuit includes a first input signal generation circuit; a second input signal generation circuit; an output circuit which includes a first transistor and a second transistor and outputs a pulse signal in response to a signal output from the first and second input signal generation circuits; a monitor circuit which obtains the threshold voltages of the first and second transistors; and a power supply output circuit which generates a power supply potential raised by a potential higher than or equal to a potential which is equal to or substantially equal to the threshold voltage and supplies the power supply potential to the first and second input signal generation circuits. A shift register includes the pulse signal output circuit.

A display apparatus and a method for generating gate signal thereof are provided. The display apparatus includes a timing controller and a display panel. The timing controller is used for providing a plurality of timing signals. The display panel includes a pixel array and a gate drive circuit. The pixel array has a plurality of pixels. The gate drive circuit is electrically connected to the timing controller and the pixel array and including a plurality of shift register circuits. The shift register circuit includes a first shift register and a second shift register. The first shift register is configured for generating a corresponding primary gate signal. The second shift register is configured for generating a corresponding secondary gate signal. The timing controller adjusts overlapping relations of the timing signals according to a frame rate of the display apparatus.

The invention concerns an oscillator generating a wave composed of a frequency of on the order of terahertz from a beat of two optical waves generated by a dual-frequency optical source. The oscillator includes a modulator the transfer function of which is non-linear for generating harmonics with a frequency of less than one terahertz for each of the optical waves generated by the dual-frequency optical source, an optical detector able to detect at least one harmonic for each of the optical waves generated by the dual-frequency optical source and transforming the harmonics detected into an electrical signal, a phase comparator for comparing the electrical signal with a reference electrical signal, and a module for controlling at least one element of the dual-frequency optical source with a signal obtained from the signal resulting from the comparison.

An oscillator module includes a first MOS transistor and a capacitor. The capacitor is coupled between a gate and source of the first MOS transistor. The drain of the first MOS transistor receives a first bias current and generates an oscillating output signal. A switching circuit operates in response to the oscillating output signal to selective charge and discharge the capacitor. A current sourcing circuit is configured to generate the bias current. The current sourcing circuit includes a second MOS transistor which has an identical layout to the first MOS transistor and receives a second bias current. A resistor is coupled between a gate and source of the second MOS transistor. The current sourcing circuit further includes a current mirror having an input configured to receive a reference current passing through the resistor and generate the first and second bias currents.

The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.

The present invention provides an apparatus for enhancing Q factor of an inductor. The apparatus includes a negative resistance generator coupled to the inductor for providing a negative resistance, and a bias circuit coupled to the negative resistance generator for biasing the negative resistance generator.

A designer-adaptive visual code (32, 32', 32″) includes a user-selected set glyphs (36, 36', 36″, 36'−), a user-selected set of allowable glyph orientations relative to a user-selected reference angle, and a user-selected spatial arrangement of the glyphs (36, 36', 36″, 36'″). The user-selected set of glyphs (36, 36', 36″, 36'″) has a size sufficient to recover geometric characteristics of at least one repeating code portion so as to generate an analyzable image when captured via a camera-equipped mobile device (26). The user-selected spatial arrangement of the glyphs (36, 36', 36″, 36'″) includes the at least one repeating code portion (34) to be visible on a surface from at least two different areas of the surface.

A system and method for reading a bar code are disclosed which may include transmitting light pulsed at a selected frequency to illuminate the bar code; converting light received at the bar code reader from the bar code into an electrical signal; transmitting the electrical signal through a signal conditioning circuit to filter and amplify the electrical signal, to thereby provide a conditioned electrical signal; sampling the conditioned electrical signal at the selected frequency; removing energy due to light scattering within a housing of the bar code reader from the sampled, conditioned electrical signal; generating one of a logical “1” and a logical “0” output based on a value of the signal generated by the step of removing; and resolving output from the step of generating into data indicative of information on the bar code.

An output buffer comprises a series connection of a first field effect transistor and a second field effect transistor, wherein the first field effect transistor is connected to a first supply potential terminal and the second field effect transistor is connected to a second supply potential terminal. An output terminal is connected to a common connection of the first transistor and the second transistor. The output buffer has a series connection of a resistive element and a capacitive element, wherein the capacitive element is connected to the output terminal, and a control circuit, to which an input signal is provided. The control circuit controls the transistors in such a way that turning off of a transistor is performed immediately, while turning on of a transistor is performed depending on the charging or discharging of the capacitive element, thus achieving a defined slew rate of the output signal at the output terminal.

In one example implementation, the present disclosure provides a direct current (DC) restoration circuit for restoring the DC component of a synchronization signal provided over an alternating current (AC) coupled link from a transmitting circuit to a receiving circuit. During a period of inactivity in the synchronization signal, the synchronization signal may experience a drift towards the common mode, and may affect the ability for the synchronization signal to properly trigger the receiving circuit. The DC restoration circuit is configured to hold the synchronization signal steady during the period of inactivity, and allow the AC component of the synchronization signal pass through to the receiving circuit during the period of activity to alleviate the problem of baseline drift in the synchronization signal.

A blade for a rotor of a wind turbine is manufactured with a root region with a substantially circular or elliptical profile closest to the hub, an airfoil region with a lift generating profile furthest away from the hub and a transition region having a profile gradually changing the root region to the airfoil region. A first blade design is used for the first base part on a first longitudinal section of an airfoil region of a second blade, so that an induction factor of the first base part on the second blade deviates from a target induction factor. The first longitudinal section of the second blade is provided with flow altering devices so as to adjust the aerodynamic properties of the first longitudinal segment to substantially meet the target induction factor at the design point on the second blade.

A method of transmitting a training signal in a Wireless Local Area Network (WLAN) system includes generating one or more first training signals for a first destination station and one or more second training signals for a second destination station by applying a mapping matrix P to a training signal generation sequence, mapping the first training signals and the second training signals to a plurality of antennas according to an antenna mapping matrix, and performing Inverse Fast Fourier Transform (IFFT) on each of the first training signals and the second training signals mapped to the plurality of antennas and transmitting the training signals through the plurality of antennas.

In an angle modulated radio transmitter, the total power is the same when modulated or unmodulated. Angle modulation produces multiple sideband pairs. The power in the sidebands is derived from the carrier. When a complex modulating waveform is used, the power (and therefore the amplitude) of the carrier varies. A system and method is provided for dramatically minimizing, to nearly zero, the bandwidth needed to transmit digital information using sideband suppression of angle modulated signals. The systems described use various techniques to suppress sideband pairs, leaving the carrier signal. The amplitude variations of the carrier are used to convey information. In some examples, techniques are used to filter and/or phase out one or more sideband pairs, leaving the carrier signal.

A communication apparatus with a multiple-input and multiple-output (MIMO) channel, includes a minimum mean square error (MMSE) detector configured to estimate quadrature amplitude modulation (QAM) symbols based on signals received through the MIMO channel. The apparatus further includes a QAM demodulator configured to demodulate the estimated QAM symbols, and estimate a first posterior probability of each of encoded bits of the estimated QAM symbols, and a first module configured to remove a first prior probability of each of the encoded bits from the first posterior probability to generate soft estimates of the encoded bits. The apparatus further includes a channel decoder configured to decode the encoded bits based on the soft estimates, and generate an improved posterior probability of each of the encoded bits, and a second module configured to generate a second prior probability of each of the encoded bits based on the improved posterior probability.

A digital broadcasting receiving system is provided. A receiving module receives an M number of symbols each carrying an N number of subcarriers of a control signal. A converting module performs FFT on respective kth subcarriers of an ith symbol and an (i+1)th symbol to generate an (i, k)th converted value and an (i+1, k)th converted value. A demodulating module performs differential demodulation on the (i, k)th and (i+1, k)th converted values to generate an (i, k)th demodulation value. A combining module soft-combines the (i, 1)th demodulation value through the (i, N)th demodulation value to generate an ith prediction value corresponding to the ith symbol. A determining module identifies a synchronization segment in the control signal according to the 1st prediction value to the (M−1)th prediction value.

Various embodiments associated with an at least fourth-order cumulant of a signal are described. The at least fourth-order noise-insensitive cumulant of the signal can be taken and compared against an at least fourth-order noise-insensitive cumulant of known signals. A match can be found between the signal and a known signal and from this match, a demodulation scheme of the signal can be determined. The demodulation scheme can be used to demodulate the signal.

A system that incorporates the subject disclosure may include, for example, a process that includes adjusting a filter in electrical communication between an input terminal and a demodulator. The filter is applied to an information bearing signal, e.g., to mitigate interference, received at the input terminal, resulting in a filtered signal. An error signal is received, indicative of errors detected within information obtained by demodulation of a modulated carrier of the filtered signal. A modified filter state is determined in response to the error signal and the filter is adjusted according to the modified filter state, e.g., to improve mitigation of the interference. Other embodiments are disclosed.

A receiving circuit, use, and method for receiving an encoded and modulated radio signal is provided. The circuit comprise a demodulator and a digital filter connected downstream of the demodulator for moving averaging. The filter has at least two FIFO registers and subtractors. Whereby for subtracting an output value of the FIFO register from an input value of the FIFO register a subtractor is connected to each FIFO register. Wherein the filter has a weighting unit, which is connected downstream of each FIFO register, and wherein the filter has an integrator, which is connected downstream of the subtractors for integration.

Systems and methods for discrete signal synchronization based on a known bit pattern are described. In one aspect of the present subject matter, a discrete signal synchronization system is configured to synchronize a preprocessed discrete signal with a modified discrete signal. The system comprises a processor and a synchronization module coupled to the processor. The synchronization module comprises an extraction module and comparison module. The extraction module determines a bit pattern from the modified discrete signal using Discrete Wavelet Transformation (DWT) and Singular Value Decomposition (SVD). The comparison module compares the determined bit pattern with a known bit pattern of the preprocessed discrete signal and records a time point at which the determined bit pattern matches with the known bit pattern of the preprocessed discrete signal as a synchronization point.

The present invention relates to a wireless transmission system for signals intended more specifically for a domestic environment. It includes a central terminal comprising at least m transmission channels and n directive transmission antennas intended to transmit first signals at least one client terminal having at least one reception channel connected to a reception antenna in order to receive the first signals said central terminal and said client terminal communicating in a transmission channel having a predetermined frequency band, and an estimation device able to generate an item of information representative of the reception quality of first signals in at least one point of a predetermined geographic zone associated with the client terminal and a return channel in order to transmit said at least one item of information to the control means of the central terminal.

A mobile wireless device maintains a radio sector database. When receiving no response or a negative response from a radio sector to a transmitted signaling message, the mobile wireless device adds or updates the radio sector database. When receiving a positive response from the radio sector, the mobile wireless device deletes the radio sector from the radio sector database. Before transmitting signaling messages to a radio sector, the mobile device determines a time delay value if the radio sector is in the radio sector database. The mobile wireless device discards the signaling message when an elapsed time since a most recently transmitted signaling message to the radio sector does not exceed the determined time delay value. In an embodiment, each radio sector in the radio sector database includes a failure count value, and the determined time delay value depends on the failure count value.

Multiple-Input and Multiple-Output (MIMO)-Orthogonal Frequency Division Multiplexing (OFDM) communication is provided which allows high accuracy estimation of frequency offset, high accuracy estimation of a transmission path fluctuation and high accuracy synchronization/signal detection. Pilot symbol mapping is provided for forming pilot carriers by assigning orthogonal sequences to corresponding subcarriers among OFDM signals which are transmitted at the same time from respective antennas in the time domain. Even when pilot symbols are multiplexed among a plurality of channels (antennas), this allows frequency offset/phase noise to be estimated with high accuracy.

A radio communication device capable of randomizing both inter-cell interference and intra-cell interference. In this device, a spreading section (214) primarily spreads a response signal in a ZAC sequence set by a control unit (209). A spreading section (217) secondarily spreads the primarily spread response signal in a block-wise spreading code sequence set by the control unit (209). The control unit (209) controls the cyclic shift amount of the ZAC sequence used for the primary spreading in the spreading section (214) and the block-wise spreading code sequence used for the secondary spreading in the spreading section (217) according to a set hopping pattern. The hopping pattern set by the control unit (209) is made up of two hierarchies. An LB-based hopping pattern different for each cell is defined in the first hierarchy in order to randomize the inter-cell interference. A hopping pattern different for each mobile station is defined in the second hierarchy in order to randomize the intra-cell interference.

The present invention relates to a system, method, and apparatus that include a novel way of automatically assigning materials to 3D CAD models. A predefined material template specifies that a particular part or material name is assigned to a particular material such that all instances of the particular part name are assigned or modified automatically by the material template. By having a consistent naming convention for the parts in the CAD file, this material assignment can be performed automatically when the CAD file is imported or viewed.

A three dimensional (3D) branchline coupler using through silicon vias (TSV), methods of manufacturing the same and design structures are disclosed. The method includes forming a first waveguide structure in a first dielectric material. The method further includes forming a second waveguide structure in a second dielectric material. The method further includes forming through silicon vias through a substrate formed between the first dielectric material and the second dielectric material, which connects the first waveguide structure to the second waveguide structure.

An attenuation reduction control structure for high-frequency signal transmission lines of a flexible circuit board includes an impedance control layer formed on a surface of a substrate. The impedance control layer includes an attenuation reduction pattern that is arranged in an extension direction of the high-frequency signal transmission lines of the substrate and corresponds to bottom angle structures of the high-frequency signal transmission lines in order to improve attenuation of a high-frequency signal transmitted through the high-frequency signal transmission lines. An opposite surface of the substrate includes a conductive shielding layer formed thereon. The conductive shielding layer is formed with an attenuation reduction pattern corresponding to top angle structures of the high-frequency signal transmission lines.

A signal transmission cable includes a multi-layer parallel transmission path, a single-layer parallel transmission path, and a single-layer/multi-layer conversion section. The multi-layer parallel transmission path includes two or more dielectric waveguides stacked in upper and lower directions. Each dielectric waveguide includes a dielectric layer formed of a dielectric substance, two conductive layers formed to sandwich the dielectric layer, and two quasi-conductive walls. The two quasi-conductive walls include a plurality of via-holes electrically connected to the two conductive layers. The dielectric waveguides are arranged sharing the conductive layers in contact in the upper and lower directions. The single-layer parallel transmission path includes the two or more dielectric waveguides arranged in left- and right-hand directions on the same dielectric layer and conductive layer. The single-layer/multi-layer conversion section transmits a signal transmitted by each dielectric waveguide in the single-layer parallel transmission path to each dielectric waveguide in the multi-layer parallel transmission path.

A de-noise circuit and a de-noise method for differential signals and a chip for receiving differential signals are provided. The de-noise circuit includes a filter and a register. Both the filter and the register are disposed in the chip. The chip receives a differential signal through a first input terminal and a second input terminal. The filter is coupled between the first input terminal and the second input terminal of the chip. The filter filters out noises in the differential signal. The filter includes at least one filter unit. Each filter unit has at least one resistance value or at least one capacitance value. The register is coupled to the filter. The register receives and stores a control value. The register controls the resistance value or the capacitance value of at least one of the filter units based on the control value.

A nanogap device includes a first insulation layer having a nanopore formed therein, a first nanogap electrode which may be formed on the first insulation layer and may be divided into two parts with a nanogap interposed between the two parts, the nanogap facing the nanopore, a second insulation layer formed on the first nanogap electrode, a first graphene layer formed on the second insulation layer, a first semiconductor layer formed on the first graphene layer, a first drain electrode formed on the first semiconductor layer, and a first source electrode formed on the first graphene layer such as to be apart from the first semiconductor layer.

A method is disclosed for controlling at least one machining device which is coupled to a machine tool by means of an encoder signal, the machine tool having at least one motion control device. In order to improve the accuracy of the encoder connection, at least one additional variable which characterizes the transport is digitally transmitted from the motion control device to the at least one machining device and is used to correct the encoder signal.

In an embodiment, a method of generating a pulse-width modulated signal from an input signal includes calculating a finite number of basis functions of a first pulse-width modulated signal based on the input signal, and forming an electronic output based on the calculated finite number of basis functions.

A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.

A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal. The mismatch compensator is configured to receive the signal generator output signal and compensate a frequency mismatch between a desired signal generator output frequency and the signal generator output frequency generated by the oscillator by providing the fine tuning signal for changing the state of the fine tuning circuit of the oscillator and by providing the coarse tuning signal for changing a state of the coarse tuning circuit of the oscillator. The mismatch compensator provides the coarse tuning signal during a guard period defined in the given communication protocol, during which no RF-signals are transmitted by the transmitter or no RF-signals are to be received by the receiver, such that the state of the coarse tuning circuit is changed within the guard period.

A PWM circuit that can have two refresh rates, including: a first PWM signal generator and a second PWM signal generator; wherein the first PWM signal generator and the second PWM signal generator respectively control refresh rates in two dimensions of an output data generated from a target apparatus. A PWM signal generation method that can have two refresh rates, including: generating a first PWM signal; generating a second PWM signal; and controlling refresh rates in different dimensions of an output data generated from a target apparatus respectively by using the first PWM signal and the second PWM signal.

Techniques and mechanisms for configuring logic to implement a signal modulation. In an embodiment, the logic includes a finite impulse response (FIR) module comprising circuitry. The selection circuitry may be operable to concurrently receive signals from latch circuitry of the FIR module and, based on the signals, to select an input group of the selection circuitry and to output a voltage identifier. In another embodiment, configuration logic is operable to set an operational mode which determines a total number of concurrent input signals, received by the FIR module, which the FIR module will use to select an input group for generating an output representing a voltage level.

A device for mixing multiple (N) pulse density modulated (PDM) bit streams of a bit rate, the device comprises an input logic, an error accumulation circuit, an error correction circuit and an adder of more than N bits; wherein the device is arranged to output an output PDM bit stream that represents a mixture of the multiple input PDM bit streams; wherein the output PDM bit stream comprises a plurality of output PDM bits, wherein a certain output PDM bit of a plurality of output PDM bits that form the output PDM bit stream is generated during a certain clock cycle; wherein the input logic is arranged to select, during each fraction of the certain clock cycle, a current bit of a selected PDM bit stream, wherein different PDM bit streams are selected during different fragments of the certain clock cycle; wherein the error accumulation circuit is arranged to store intermediate values during a first fraction till a penultimate fraction of the certain clock signal and to store a last value during a last fraction of the certain clock signal.

Provided is a method of generating a driving signal for driving a dual mode supply modulator for a power amplifier. The method includes obtaining an envelope of a complex baseband signal to be transmitted, comparing the envelope of the complex signal with a preset threshold value, when a current envelope of the complex signal is the preset threshold value or greater or when there is a result having the preset threshold value or greater in previous N comparisons, outputting a digital board output signal configured with a first logic level through a digital-to-analog converter; and when the current envelope of the complex signal is smaller than the preset threshold value and when there is no result having the preset threshold value or greater in the previous N comparisons, outputting a digital board output signal configured with a second logic level through the digital-to-analog converter.

An apparatus for coding a signal by means of amplitude shift keying comprises a class E amplifier including a switching transistor, to whose gate is supplied a voltage having an operating frequency for operating the class E amplifier. For achieving an amplitude shift keying in the output signal of the class E amplifier, a circuit for switching the operating frequency of the voltage supplied to the gate of the switching transistor, or the resonance frequency of the class E amplifier, between a first value and a second value is provided and in order to switch a deviation degree between the operating frequency and the resonance frequency between a first value and a second value.

In an embodiment, a method of producing a multi-level RF signal includes producing plurality of pulse-width modulated signals based on an input signal. The method further includes driving a corresponding plurality of parallel amplifiers with the plurality of pulse-width modulated signals by setting a parallel amplifier to have a first output impedance when a corresponding pulse-width modulated signal is in an active state and setting the parallel amplifier to have a second output impedance when the corresponding pulse-width is in an inactive state. The method also includes phase shifting the outputs of the plurality of parallel amplifiers, wherein phase shifting transforms the second output impedance into a third impedance that is higher than the second output impedance, and combining the phase shifted outputs.

In a method of transmitting a data stream from a transmitter in a multiple-input-multiple-output (MIMO) wireless communication system, where the transmitter comprises a plurality of transmit antennas, a discrete Fourier transform (DFT) is applied to the data stream to generate a plurality of symbol sequences; symbols of a first symbol sequence from the plurality of symbol sequences are paired with symbols of a second symbol sequence from the plurality of symbol sequences to generate a plurality of symbol pairs, wherein the pairing results in an orphan symbol; a space-time block code (STBC) is applied to the symbol pairs to generate a plurality of sets of STBC symbols, each set of STBC symbols being associated with a corresponding one of the plurality of antennas; a cyclic delay diversity (CDD) operation is applied to the orphan symbol to generate a plurality of CDD symbols, each CDD symbol being associated with a corresponding one of the plurality of antennas; and each one of the antennas transmits the corresponding set of STBC symbols and the corresponding CDD symbol.

A method for phase modulation of a carrier signal from a transmitter to a contactless transponder in which data is coded as consecutive symbols, each corresponding to a predefined number of carrier cycles, and in which a symbol time is at least two cycles of the carrier signal includes, at the transmitter, spreading a phase jump of a symbol in relation to a preceding symbol over a first part of the symbol time. The establishment of the phase jump is completed in the first part of the symbol time. The periods of the cycles are constant during a second part of the symbol time.

A PWM signal generating circuit, printer, and PWM signal generating method are described. The PWM signal generating circuit includes: a single counter configured to count values expressed in N bits; and at least one arithmetic device configured to generate a PWM signal, each of the at least one arithmetic device including a pulse width data storage unit for storing N-bit pulse width data representing a pulse width of the PWM signal to be generated, and an adder for calculating a carry value from a most significant bit obtained when adding the count value and the pulse width data. A signal having a level corresponding to the carry value is output at every change in the count value so that the PWM signal having the pulse width of the pulse width data is generated.

A spout assembly is provided. The spout assembly includes a spout and a spout base. The spout base has a cross-sectional area that is smaller than a spout sized to enclose an electrical switching apparatus electrical coupling. That is, the spout base includes a CT support surface with a cross-sectional area that is smaller than the spout cross-sectional area. Current transformers are disposed upon the spout base CT support surface.

A communications device may include a near-field communication (NFC) circuit device, and a radio frequency (RF) signal blocking member adhesively coupled with the NFC device. The RF signal blocking member may be configured to block RF signal communication by the NFC device while coupled therewith. The RF signal blocking member may comprise an electrical conductor. In accordance with an example, the RF signal blocking member may comprise a frangible layer. In another example, a pressure sensitive adhesive layer may be included for adhesively securing the RF signal blocking member with the NFC device.

An interface between a receptacle body and an insert designed, in particular, as a tool or workpiece insert, comprises a receptacle body (2) having a cylindrical receiving bore (4), which is circumscribed by a first plane surface (6) extending at a right angle to the bore axis and in which a first cone surface (9) is arranged, said first cone surface being coaxial with the bore axis and being arranged so that its tapered end faces toward the plane surface. The insert (3) has a pin (15) that is disposed to be plugged into the receiving bore (4) and is circumscribed by a second plane surface (22). At an axial distance from the second plane surface (22), said pin has a second cone surface (22), the tapered end of said second cone surface being arranged so as to face toward the second plane surface. With the pin (15) inserted in the receiving bore (4), the two plane surfaces are in superimposed contact while the two cone surfaces (9, 22) can be biased relative to each other by limited twisting of the insert relative to the receptacle body.