Provided are a negative active material, a method of preparing the same, and a lithium battery including the negative active material. The negative active material includes a carbonaceous core that has a sulfur content of about 10 ppm to 900 ppm; and an amorphous carbon layer continuously formed on a surface of the carbonaceous core, wherein the carbonaceous core has a crystalloid plate structure, and a crystallite size measured from a full width at half maximum of the peak with respect to the surface (002) of about 10 nm to about 45 nm in an X-ray diffraction spectrum of the carbonaceous core. The lithium battery including a negative electrode including the negative active material has improved capacity characteristics and ring lifetime characteristics.

In a method for fabricating a graphene structure, there is formed on a fabrication substrate a pattern of a plurality of distinct graphene catalyst materials. In one graphene synthesis step, different numbers of graphene layers are formed on the catalyst materials in the formed pattern. In a method for fabricating a graphene transistor, on a fabrication substrate at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor channel and at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor source, and at a substrate region specified for synthesizing a graphene transistor drain. Then in one graphene synthesis step, at least one layer of graphene is formed at the substrate region for the graphene transistor channel, and at the regions for the transistor source and drain there are formed a plurality of layers of graphene.

Device for forming, on a nanowire made of a semiconductor, an alloy of this semiconductor with a metal or metalloid by bringing this nanowire into contact with electrically conductive metal or metalloid probes and Joule heating the nanowire at the points of contact with the probes so as to form an alloy such as a silicide. Application to the production of controlled-channel-length metal-silicide transistors.

Disclosed are soft, high refractive index, acrylic device materials. The materials contain a copolymeric additive for glistening resistance.

The present invention relates to a process for the production of a ready-to-use epoxy composition having a filler content of at least 55 vol.-%, relative to the complete ready-to-use epoxy composition, which comprises: providing a liquid A, which comprises at least one epoxy resin,providing a liquid B, which comprises at least one curing agent,providing a solid component C, which comprises at least one filler,wherein in a first step one of the liquids A or B is filled in a mixing container,in a second step the solid component C is deposited on top of the liquid in the mixing container,in a third step the remaining liquid A or B is deposited on top of the solid component C, andin a fourth step the components are mixed to obtain the ready-to-use epoxy composition.

The invention provides a method for preventing discoloration of pyrithione-containing materials, in particular plastic materials or other material such as paints, coatings, adhesives or textiles which are exposed to an outdoor environment. The method is likewise suited for preventing discoloration of other pyrithione-containing materials such as personal care compositions like shampoos. A discoloration inhibitor that includes dehydroacetic acid or a salt thereof is added to the pyrithione-containing material. The discoloration is prevented without the addition of a cyclic organic phosphoric acid ester or an organic phosphite. Use of the discoloration inhibitor does not interfere with the antimicrobial effect of the pyrithione.

Stone is formed from 5 to 60% by weight of polymerised, low-viscosity, transparent or low-colour-resin, 20 to 90% by weight of spherical alumina trihidrate Al2O3.3H2O containing less regular particles containing, advantageously 0 to 100% by weight of a transparent or translucent substitute of alumina trihydrate, and/or with 0 to 20% or pre-prepared particulate, filled resin of a chosen colour, and/or mineral particles and less than 2% by weight of luminophor. These individual components are mixed intensely whilst extracting included gaseous parts. Extraction is carried out whilst mixing, and/or after mixing, and/or before mixing. The mixture is initiated by introducing a starter and intensely mixing it into the mixture. The mixture is poured into a mould or onto a moving endless belt. The cured synthetic stone is removed from the mould or the hardened composite is taken off the the belt. Synthetic stone can be used in products as a light carrier.

Amphiphilic biomimetic phosphorylcholine-containing silicone compounds for use in both topical and internal applications as components in biomedical devices. The silicone compounds, which include zwitterionic phosphorylcholine groups, may be polymerizable or non-polymerizable. Specific examples of applications include use as active functional components in ophthalmic lenses, ophthalmic lens care solutions, liquid bandages, wound dressings, and lubricious and anti-thrombogenic coatings.

Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from multiple blocks and buffered in a buffer. The buffer's output is operatively coupled to one or more high-speed serial I/O interfaces via muxing logic during debug test operations. The buffered data is encoded as serialized data and sent over the one or more high-speed serial I/O interfaces to a logic device that receives serialized data and de-serializes it to generate parallel debug data that is provided to a debugger. The buffer may be configured as a bandwidth-adapting buffer that facilitates transfer of debug data that is received at a variable combined data rate outbound via the one or more high-speed serial I/O interfaces at a data rate corresponding to the bandwidth of the serial I/O interfaces.

A double data rate memory physical interface having self checking loopback logic on-chip is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of generating a set of test data values that comprise at least two data bits. Also disposed on the chip is a second linear feedback shift register. The second linear feedback shift register is capable of generating a set of expected data values that match the test data values. Further, an internal loopback error check element is disposed on the chip. The internal loopback error check element is used to compare the set of expected data values with the set of test data values.

The present invention intends to provide a method for removing radioactive cesium, or radioactive iodine and radioactive cesium that is simple and low-cost, further does not require an energy source such as electricity, moreover can take in and stably immobilize the removed radioactive substances within a solid, and can reduce the volume of radioactive waste as necessary, and to provide a hydrophilic resin composition using for the method for removing radioactive cesium, or radioactive iodine and radioactive cesium, and the object of the present invention is achieved by using a hydrophilic resin composition containing: at least one hydrophilic resin selected from the group consisting of a hydrophilic polyurethane resin, a hydrophilic polyurea resin, and a hydrophilic polyurethane-polyurea resin each having at least a hydrophilic segment; and a zeolite dispersed therein in a ratio of at least 1 to 200 mass parts relative to 100 mass parts of the hydrophilic resin.

A process for encapsulating a radioactive object to render the object suitable for shipment and/or storage, and including the steps of preparing a plastic material, causing the plastic material to react with a foaming agent, generating a foaming plastic, encapsulating the radioactive object in the foaming plastic, and allowing the foaming plastic to solidify around the radioactive object to form an impervious coating.

Degradation of phosphate esters, particularly neurotoxins and pesticides, is performed using high oxidative state molybdenum complexes, more particularly molybdenum(VI) complexes. A molybdenum(VI) complex is dissolved in water and then reacted with a phosphate ester. The phosphate esters can include, but are not limited to, VX, VE, VG, VM, GB, GD, GA, GF, parathion, paraoxon, triazophos, oxydemeton-methyl, chlorpyrifos, fenitrothion and pirimiphos-methyl, representing both chemical warfare agents as well as pesticides and insecticides.

Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. This encoding scheme allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for an implementation adapted to shift a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.

An independently functioning or centrally controlled wall light switch is configured to operate in normal mode and a Jewish holiday mode wherein the state of the light is fixed, regardless of the user's physical manipulation of the light switch. The control system automatically activates holiday mode by combining a geographically determined Jewish religious clock executed by software and hardware that utilizes the current time, date and geographical location of the apparatus in accordance with the Jewish definition of time and laws for calculating numerous religiously significant shifting daily points in time. The control system further incorporates several energy saving and preference modes by utilizing a particular day's calculated religious points in time in conjunction with holiday behavior patterns common to most Jewish families to provide the user with a greatly simplified means of programming an automatically adjusting on/off light timer and dimming overlay functionality during holiday mode.

The invention provides a method for the manufacture of a catheter comprising a hydrophilic gel. The method comprising the steps of combining a polymeric photoinitiator of the general formula (I): R1(A1)r-(R2(A2)m-O)o—(R3(A3)n-O)p—R4(A4)s (I) with one or more gel-forming polymers and/or gel-forming monomers to form a matrix composition, curing the matrix composition by exposing it to UV radiation, exposing the matrix composition to a swelling medium and incorporating the hydrophilic gel into a catheter. The invention also provides autocuring of the polymeric photoinitiator (I) to provide a gel precursor, a hydrophilic gel and a catheter comprising or coated with the hydrophilic gel of the invention.

A variety of biomedical devices are provided which include thiol-ene or thiol-yne shape memory polymers. The biomedical devices of the invention are capable of exhibiting shape memory behavior at physiological temperatures and may be used in surgical procedures. Methods of making the devices of the invention are also provided.

The invention pertains to an oligomer or polymer substituted by one or more bisacylphosphine oxide moieties, characterized in that said bisacylphosphine oxide moiety is linked via the phosphorous atom, optionally via a spacer group, to the oligomer or polymer backbone; as well as to specifically functionalized bisacylphosphine oxides, suitable to prepare said polymers or oligomers.

A radiation curable temporary laminating adhesive composition for use in temperature applications at 150° C. or greater, and typically at 200° C. or greater, comprises (A) a hydrogenated polybutadiene diacrylate; (B) a radical photoinitiator; and (C) a diluent.

3-Esters and 3-amides of thioxanthone bearing alkyl chains of appropriate length and can be used as photoinitiators or sensitizers in photopolymerizable systems, in particular for the preparation of coatings compatible with the food use.

The present invention relates to methods for making wear and oxidation resistant polymeric materials by high temperature melting. The invention also provides methods of making medical implants containing cross-linked antioxidant-containing tough and ductile polymers and materials used therewith also are provided.

A bus interconnect interfaces a host system to a radio frequency (RF) generator that is coupled to a plasma chamber. The bus interconnect includes a first set of host ports, which are used to provide a power component setting and a frequency component setting to the RF generator. The ports of the first set of host ports are used to receive distinct variables that change over time. The bus interconnect further includes a second set of generator ports used to send a power read back value and a frequency read back value to the host system. The bus interconnect includes a sampler circuit integrated with the host system. The sampler circuit is configured to sample signals at the ports of the first set at selected clock edges to capture operating state data of the plasma chamber and the RF generator.

A method, apparatus, and system for switching from an existing target end device to a next target end device in a multi-expander storage topology by using Fast Context Switching. The method enhances Fast Context Switching by allowing Fast Context Switching to reuse or extend part of an existing connection path to an end device directly attached to a remote expander. The method can include reusing or extending at least a partial path of an established connection between an initiator and the existing target end device for a connection between the initiator and the next target end device, whereby the existing target end device and the next target end device are locally attached to different expanders.

A cloud system may create physical resource tags to store relationships between cloud computing offerings, such as computing service offerings, storage offerings, and network offerings, and the specific physical resources in the cloud computing environment. Cloud computing offerings may be presented to cloud customers, the offerings corresponding to various combinations of computing services, storage, networking, and other hardware or software resources. After a customer selects one or more cloud computing offerings, a cloud resource manager or other component within the cloud infrastructure may retrieve a set of tags and determine a set of physical hardware resources associated with the selected offerings. The physical hardware resources associated with the selected offerings may be subsequently used to provision and create the new virtual machine and its operating environment.

A system, method and computer program product for allocating shared resources. Upon receiving requests for resources, the cost of bundling software in a virtual machine (VM) image is automatically generated. Software is selected by the cost for each bundle according to the time required to install it where required, offset by the time to uninstall it where not required. A number of VM images having the highest software bundle value (i.e., highest cost bundled) is selected and stored, e.g., in a machine image store. With subsequent requests for resources, VMs may be instantiated from one or more stored VM images and, further, stored images may be updated selectively updated with new images.

A server computer system determines that configuring a first virtual machine in a cloud depends on a configuration result of configuring a second virtual machine. The server computer system configures the second virtual machine in the cloud and configures the first virtual machine in the cloud using the configuration result of the second virtual machine.

A system and method for reconfiguring a computing environment comprising a consumption analysis server, a placement server, an infrastructure management client and a data warehouse in communication with a set of data collection agents and a database. The consumption analysis server operates on measured resource utilization data to yield a set of resource consumptions in regularized time blocks, collects host and virtual machine configurations from the computing environment and determines available capacity for a set of target hosts. The placement server assigns a set of target virtual machines to the target set of hosts in a new placement. In one mode of operation the new placement is nearly optimal. In another mode of operation, the new placement is “good enough” to achieve a threshold score based on an objective function of resource capacity headroom. The new placement is implemented in the computing environment.

According to an embodiment, based on task border information, and first-type dependency relationship information containing N number of nodes corresponding to data accesses to one set of data, containing edges representing dependency relationship between the nodes, and having at least one node with an access reliability flag indicating reliability/unreliability of corresponding data access; task border edges, of edges extending over task borders, are identified that have an unreliable access node linked to at least one end, and presentation information containing unreliable access nodes is generated. According to dependency existence information input corresponding to the set of data, conversion information indicating absence of data access to the unreliable access nodes is output. According to the conversion information, the first-type dependency relationship information is converted into second-type dependency relationship information containing M number of nodes (0≦M≦N) corresponding to data accesses to the set of data and containing edges representing inter-node dependency relationship.

Disclosed is an information processing device and a task switching method that can reduce the time required for switching of tasks in a plurality of coprocessors. The information processing device (30) includes a processor core (301); coprocessors (311 to 31n) including operation units (321 to 32n) that perform operation in response to a request from the processor core (301) and operation storage units (331 to 22n) that store the contents of operation of the operation units (321 to 32n), save storage units (351 to 35n) that store the saved contents of operation, a task switching control unit (302) that outputs a save/restore request signal when switching a task on which operation is performed by the coprocessors (311 to 31n), and save/restore units (341 to 34n) that perform at least one of saving of the contents of operation in the operation storage units (331 to 33n) to the save storage units (351 to 35n) and restoration of the contents of operation in the save storage units (351 to 35 n) to the operation storage units (331 to 33n) in response to the save/restore request signal.

A method and apparatus for method of continuously producing 1,1,1,2,3-pentafluoropropane with high yield is provided. The method includes (a) bringing a CoF3-containing cobalt fluoride in a reactor into contact with 3,3,3-trifluoropropene to produce a CoF2-containing cobalt fluoride and 1,1,1,2,3-pentafluoropropane, (b) transferring the CoF2-containing cobalt fluoride in the reactor to a regenerator and bringing the transferred CoF2-containing cobalt fluoride into contact with fluorine gas to regenerate a CoF3-containing cobalt fluoride, and (c) transferring the CoF3-containing cobalt fluoride in the regenerator to the reactor and employing the transferred CoF3-containing cobalt fluoride in Operation (a). Accordingly, the 1,1,1,2,3-pentafluoropropane can be continuously produced with high yield from the 3,3,3-trifluoropropene using a cobalt fluoride (CoF2/CoF3) as a fluid catalyst, thereby improving the reaction stability and readily adjusting the optimum conversion rate and selectivity.

The present invention relates to 1,4-diethynylbenzene derivatives having substituents in the 2,3-position (cf. formula I, Claims), to the use thereof for high-frequency components, to liquid-crystalline media comprising the compounds, and to high-frequency components, in particular antennae, especially for the gigahertz range, comprising these media. The liquid-crystalline media serve, for example, for the phase shifting of microwaves for tuneable ‘phased-array’ antennae.

A solvent that reversibly converts from a hydrophobic liquid form to hydrophilic liquid form upon contact with water and a selected trigger, e.g., contact with CO2, is described. The hydrophilic liquid form is readily converted back to the hydrophobic liquid form and water. The hydrophobic liquid is an amidine or amine. The hydrophilic liquid form comprises an amidinium salt or an ammonium salt.

The invention relates to the use of polymers, containing between 1 and 100 mol % of structural units of the formula (1), wherein R1 means hydrogen or C1-C6 alkyl, A means C2-C4 alkylene groups, and B means C2-C4 alkylene groups, with the stipulation that A is different from B, and x and y mean an integer from 1 to 100 independent of each other, in amounts of 0.01 to 2 wt % relative to the water phase, as gas hydrate inhibitors.

The invention provides for the use of copolymers comprising 1 to 99 mol % of structural units of the formula (1) in which R1 is hydrogen or C1-C6-alkyl, A is C2-C4-alkylene groups and B is C2-C4-alkylene groups, with the proviso that A is different than B, and x, y are each independently an integer of 1-100, and 1 to 99 mol % of structural units of the formula (3) in which R6 is hydrogen or C1-C6-alkyl, D is C2-C4-alkylene groups and z is an integer of 1-50, in amounts of 0.01 to 2% by weight, based on the water phase, as gas hydrate inhibitors.

The present invention relates to a novel method for preparing a new type of catalyst for the oxidation of CO in a reactant gas or air. The method provides the preparation of a catalyst having nano-sized metal particles and a capping agent deposited on a solid support. The size and distribution of the metal particles can be easily controlled by adjusting reaction condition and the capping agent used. The catalyst prepared has high activity at low temperature toward selective oxidation of CO and is stable over an extended period of time. The catalyst can be used in air filter devices, hydrogen purification processes, automotive emission control devices (decomposition of NOx, x is the integer 1 or 2), F-T synthesis, preparation of fuel-cell electrode, photocatalysis and sensors.

The invention relates to polymers that can be obtained by polymerizing the monomers (A), (B), and (D), and optionally (C), where (A) is a monomer of formula (I), wherein A stands for C2 to C4 alkylene, B stands for a C2 to C4 alkylene different from A, R stands for hydrogen or methyl, m stands for a number from 1 to 500, n stands for a number from 1 to 500, (B) is an ethylenically unsaturated monomer that contains at least one carboxylic acid function, (C) is optionally a further ethylenically unsaturated monomer different from (A) and (B), (D) is a monomer of formula (II), wherein D stands for C2 to C4 alkylene, E stands for a C2 to C4 alkylene group different from D, F stands for a C2 to C4 alkylene group different from E, R stands for hydrogen or methyl, o stands for a number from 1 to 500, p stands for a number from 1 to 500, q stands for a number from 1 to 500, and wherein the weight fraction of the monomers is 35 to 99% for the macromonomer (A), 0.5 to 45% for the monomer (B), 0 to 20% for the monomer (C), and 1 to 20% for the monomer (D), and to the use of said polymers as defoamers for inorganic solid suspensions.

A method for synthesizing catalyst beads of bulk transmission metal carbides, nitrides and phosphides is provided. The method includes providing an aqueous suspension of transition metal oxide particles in a gel forming base, dropping the suspension into an aqueous solution to form a gel bead matrix, heating the bead to remove the binder, and carburizing, nitriding or phosphiding the bead to form a transition metal carbide, nitride, or phosphide catalyst bead. The method can be tuned for control of porosity, mechanical strength, and dopant content of the beads. The produced catalyst beads are catalytically active, mechanically robust, and suitable for packed-bed reactor applications. The produced catalyst beads are suitable for biomass conversion, petrochemistry, petroleum refining, electrocatalysis, and other applications.

A computing section is provided with a plurality of computing units and correlatively stores entries of configuration information that describes configurations of the plurality of computing units with physical configuration numbers that represent the entries of configuration information and executes a computation in a configuration corresponding to a designated physical configuration number. A status management section designates a physical configuration number corresponding to a status to which the computing section needs to advance the next time for the computing section and outputs the status to which the computing section needs to advance the next time as a logical status number that uniquely identifies the status to which the computing section needs to advance the next time in an object code. A determination section determines whether or not the computing section has stored an entry of configuration information corresponding to the status to which the computing section needs to advance the next time based on the logical status number that is output from the status management section. A rewriting section correlatively stores the entry of the configuration information and a physical configuration number corresponding to the entry of the configuration information in the computing section when the determination section determines that the computing section has not stored the entry of configuration information corresponding to the status to which the computing section needs to advance the next time.

A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target.

A computing machine is disclosed having a memory system for storing a collection of execution nodes, a head for reading a sequence of symbols in the execution nodes in the memory system, and writing a sequence of symbols in the memory system. The machine is configured to execute a computation with a collection of pairs of execution nodes. Each pair of execution nodes represents a machine instruction. One execution node in the pair represents input of the machine instruction represented by the execution nodes. Another execution node in the pair represents output of the machine instruction represented by the execution nodes. Each execution node has a state of the machine, a sequence of symbols and a number.

A technique for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.

A method for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.

An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.

A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.