A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. Test wrappers may also be configured to test multiple IP blocks comprising a test partition.

A logical operations functional block for an execution unit of a processor includes a first input data link for a first operand and a second input data link for a second operand. The execution unit includes a register connected to an error correction code detection unit. The logical operations functional block includes a look-up table configured to receive an error correction code syndrome from the error correction code detection unit. The logical operations functional block also includes a multiplexer configured to receive an output signal from the look-up table at a first input and the first operand at a second input, wherein an output of the multiplexer is coupled to the first input data link of a logical functional unit.

The present invention discloses a method and apparatus for processing and error correction of a GFP-T superblock, where the 64 bytes of payload data of a first superblock are buffered in the first page of a two-page buffer. The flag byte is buffered in a separate buffer, and a CRC operation is performed in a separate logic element. The result of the CRC operation is checked against a single syndrome table which may indicate single- or multi-bit errors. As the payload data of the first superblock is processed and read out of the first page of the two-page buffer, the payload data of a second superblock is written into the second page of the two-page buffer to be processed and corrected.

An independently functioning or centrally controlled wall light switch is configured to operate in normal mode and a Jewish holiday mode wherein the state of the light is fixed, regardless of the user's physical manipulation of the light switch. The control system automatically activates holiday mode by combining a geographically determined Jewish religious clock executed by software and hardware that utilizes the current time, date and geographical location of the apparatus in accordance with the Jewish definition of time and laws for calculating numerous religiously significant shifting daily points in time. The control system further incorporates several energy saving and preference modes by utilizing a particular day's calculated religious points in time in conjunction with holiday behavior patterns common to most Jewish families to provide the user with a greatly simplified means of programming an automatically adjusting on/off light timer and dimming overlay functionality during holiday mode.

Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.

A system, method and computer-readable media for managing a compute environment are disclosed. The method includes importing identity information from an identity manager into a module performs workload management and scheduling for a compute environment and, unless a conflict exists, modifying the behavior of the workload management and scheduling module to incorporate the imported identity information such that access to and use of the compute environment occurs according to the imported identity information. The compute environment may be a cluster or a grid wherein multiple compute environments communicate with multiple identity managers.

A system and method for reordering storage levels in a virtualized environment includes identifying a virtual machine (VM) to be transitioned and determining a new storage level order for the VM. The new storage level order reduces a VM live state during a transition, and accounts for hierarchical shared storage memory and criteria imposed by an application to reduce recovery operations after dynamic resource allocation actions. The new storage level order recommendation is propagated to VMs. The new storage level order applied in the VMs. A different storage-level order is recommended after the transition.

A usage allocation of a hardware resource to each of a number of workloads over time is determined using a demand model. The usage allocation of the resource includes a current and past actual usage allocation of the resource, a future projected usage allocation of the resource, and current and past actual usage of the resource. A capacity allocation of the resource is determined using a capacity model. The capacity allocation of the resource includes a current and past capacity and a future projected capacity of the resource. Whether a gap exists between the usage allocation and the capacity allocation is determined using a mapping model. Where the gap exists between the usage allocation of the resource and the capacity allocation of the resource, a user is presented with options determined using the mapping model and selectable by the user to implement a remediation strategy to close the gap.

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and predicate predictions. The predictions may be made using one or more prediction control flow graphs which represent predicates in instruction blocks and branches between blocks in a program. The prediction control flow graphs may be structured as trees such that each node in the graphs is associated with a predicate instruction, and each leaf associated with a branch target which jumps to another block. During execution of a block, a prediction generator may take a control point history and generate a prediction. Following the path suggested by the prediction through the tree, both predicate values and branch targets may be predicted. Other embodiments may be described and claimed.

Methods and apparatus for client-allocatable bandwidth pools are disclosed. A system includes a plurality of resources of a provider network and a resource manager. In response to a determination to accept a bandwidth pool creation request from a client for a resource group, where the resource group comprises a plurality of resources allocated to the client, the resource manager stores an indication of a total network traffic rate limit of the resource group. In response to a bandwidth allocation request from the client to allocate a specified portion of the total network traffic rate limit to a particular resource of the resource group, the resource manager initiates one or more configuration changes to allow network transmissions within one or more network links of the provider network accessible from the particular resource at a rate up to the specified portion.

Disclosed is a novel computer implemented system, on demand service, computer program product and a method that leverages combined concrete and symbolic execution and several fault-localization techniques to automatically detects failures and localizes faults in PHP Hypertext Preprocessor (“PHP”) Web applications.

Apparatus for orientating a user in a space wherein the space comprises a plurality of zones of which only certain zones constitute functional zones wherein each functional zone includes a first type device containing information relating to the position of the zone in the space and wherein the first type device is reactive to the presence of a second type device associated with the user to provide the user with the information to determine the orientation of the user in the space. A method of orientating the user within the space and guiding the user toward one or more features in the space is also disclosed.

A method for illustrating an aircraft flight plan comprising at least one waypoint on a flight display of a flight deck of an aircraft, where the method may include displaying on the flight display of the flight deck some type of display indicia that indicates the suitability of locations for future waypoints.

An automated process uses a local positioning system to acquire location (i.e., position and orientation) data for one or more movable target objects. In cases where the target objects have the capability to move under computer control, this automated process can use the measured location data to control the position and orientation of such target objects. The system leverages the measurement and image capture capability of the local positioning system, and integrates controllable marker lights, image processing, and coordinate transformation computation to provide tracking information for vehicle location control. The resulting system enables position and orientation tracking of objects in a reference coordinate system.

An integrated circuit having a programmable clock spreader configured to generate a plurality of controllably skewed clock signals, each applied to a corresponding region within the integrated circuit with circuitry configured to be triggered off the applied clock signal. The programmable clock spreader is designed to enable customization of the current-demand characteristics exhibited by the integrated circuit, e.g., based on the circuit's spectral impedance profile, to cause transient voltage droops in the power-supply network of the integrated circuit to be sufficiently small to ensure proper and reliable operation of the integrated circuit.

An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.

In one embodiment of the invention, an integrated circuit (IC) design tool is provided for synthesizing logic, including one or more software modules to synthesize a gate-level netlist of a squarer functional block. The software modules include a bitvector generator, a bitvector reducer, and a hybrid multibit adder generator. The bitvector generator multiplies bits of a vector together to generate partial products for a plurality of bitvectors and then optimizes a plurality of least significant bitvectors. The bitvector reducer reduces the partial products in the bitvectors of the squarer functional block down to a pair of final vectors. The hybrid multibit adder generator generates a hybrid multibit adder including a first adder and a second adder coupled together by a carry bit with bit widths being responsive to a dividerbit. The hybrid multibit adder adds the pair of final vectors together to generate a final result for the squarer functional block.

A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.

There is described herein a superconducting segment and method of making same comprising one or several layers with very high electrical resistivity, acting as a current flow diverter when the current transfers from the superconductor to the stabilizer. The purpose of this current flow diverter is: i) to increase the contact resistance between the superconductor and the stabilizer, by reducing the contact area, and ii) to force the current to flow along a specific path, so as to increase momentarily the current density in a specific portion of the stabilizer. The consequence of i) and ii) is that heat generated at the extremities of the normal zone is increased and spread over a longer length along the superconducting segment, which increases the NZPV and thus, the uniformity of the quench.

Methods, apparatus, and computer programs for simulating the source of sound are provided. One method includes operations for determining a location in space of the head of a user utilizing face recognition of images of the user. Further, the method includes an operation for determining a sound for two speakers, and an operation for determining an emanating location in space for the sound, each speaker being associated with one ear of the user. The acoustic signals for each speaker are established based on the location in space of the head, the sound, the emanating location in space, and the auditory characteristics of the user. In addition, the acoustic signals are transmitted to the two speakers. When the acoustic signals are played by the two speakers, the acoustic signals simulate that the sound originated at the emanating location in space.

A technique is provided for post selection location of a mouse pointer icon in a display screen of a computing device. A software tool receives input of the post selection location for the mouse pointer icon. The post selection location defines a default location to move the mouse pointer icon in response to a window action taken on a window displayed in the display screen. In response to the window action in which the mouse pointer icon is initially displayed at a selection location corresponding to the window action, the mouse pointer icon is moved to the post selection location such that the mouse pointer icon is displayed at the post selection location in the display screen.

Images are analyzed within a 3D environment that is generated based on spatial relationships of the images and that allows users to experience the images in the 3D environment. Image analysis may include ranking images based on user viewing information, such as the number of users who have viewed an image and how long an image was viewed. Image analysis may further include analyzing the spatial density of images within a 3D environment to determine points of user interest.

A system, method, and computer-readable medium are disclosed for realizing server management functionalities in the absence of a routable Internet Protocol (IP) network address of a remote access controller (RAC). A first device, which is operatively coupled to a link-local network, generates a Multicast Domain Name System (mDNS) IP multicast query message, which it then sends to a second device on the link-local network. In response, the second device, which comprises a RAC, returns its link-local IP address to the first device.

A clock security device to be hung on a wall of a facility such as, for example, a store. The clock face has a convex mirrored surface which provides reflected panoramic view of the facility. The clock security device also includes a mounting bracket which provides for the mounting of the clock security device on the wall with the concave mirrored surface at different positions from parallel to the wall to tilted downwardly at different selected angles to the wall.

A time-locked cigarette case has time-controlled locking mechanism which is manually adjustable by the user and also has a first latch rod which normally retains the case in a closed condition and a second latch rod which moves to retain the case in a closed condition if the first latch rod is jolted to an open position so as to prevent the case from being opened by jolting before the manually set time delay has expired.

A system includes a system time counter associated with a micro controller and a secure clock module having a real time clock and an elapsed time counter. The system synchronizes operation between the secure clock module and the system time counter. The synchronized time entered into the system time counter is utilized in the operation of the system. The real time clock time can be caused to be entered into the elapsed time counter at certain point in the operation of the system. The relationship of the time provide enhanced systems security.

A combined table lamp and clock assembly includes a lamp unit and a clock unit. The lamp unit includes a lamp stand base, a lamp stand, and a lamp bulb holder. The lamp stand base has a top side formed with a cavity, and a bottom side adapted to be placed on a table top. The lamp stand extends uprightly from the lamp stand base, and has an upper end portion and a lower end portion that is mounted on the top side of the lamp stand base. The lamp bulb holder is mounted on the upper end portion of the lamp stand, and is adapted for mounting a lamp bulb thereon. The clock unit includes a clock base, an upright clock panel, and a clock mechanism. The clock base is received in the cavity in the top side of the lamp stand base, and is formed with an insert slot therethrough. The upright clock panel has a lower end formed with an insert portion that is inserted removably into the insert slot. The clock mechanism is mounted on the clock panel.

A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.

A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.

A controller receives a request to perform a release space operation. A determination is made that a new discard scan has to be performed on a cache, in response to the received request to perform the release space operation. A determination is made as to how many task control blocks are to be allocated to the perform the new discard scan, based on how many task control blocks have already been allocated for performing one or more discard scans that are already in progress.

Techniques for handling version information using a copy engine. In one embodiment, an apparatus comprises a copy engine configured to perform one or more operations associated with a block memory operation in response to a command. Examples of block memory operations may include copy, clear, move, and/or compress operations. In one embodiment, the copy engine is configured to handle version information associated with the block memory operation based on the command. The one or more operations may include operating on data in a cache and/or modifying entries in a memory. In one embodiment, the copy engine is configured to compare version information in the command with stored version information. The copy engine may overwrite or preserve version information based on the command. The copy engine may be a coprocessing element. The copy engine may be configured to maintain coherency with other copy engines and/or processing elements.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

A mechanism is provided in a storage device for performing a write operation. The mechanism configures a write buffer memory with a plurality of write buffer portions. Each write buffer portion is dedicated to a predetermined block size category within a plurality of block size categories. For each write operation from an initiator, the mechanism determines a block size category of the write operation. The mechanism performs each write operation by writing to a write buffer portion within the plurality of write buffer portions corresponding to the block size category of the write operation.

A data processing entity that includes a mass memory with a plurality of memory locations for storing memory blocks. Each of a plurality of software images includes a plurality of memory blocks with corresponding image addresses within the software image. The memory blocks of software images stored in boot locations of a current software image are relocated. The boot blocks of the current software image are stored into the corresponding boot locations. The data processing entity is booted from the boot blocks of the current software image in the corresponding boot locations, thereby loading the access function. Each request to access a selected memory block of the current software image is served by the access function, with the access function accessing the selected memory block in the associated memory location provided by the control structure.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

MRI compatible localization and/or guidance systems for facilitating placement of an interventional therapy and/or device in vivo include: (a) a mount adapted for fixation to a patient; (b) a targeting cannula with a lumen configured to attach to the mount so as to be able to controllably translate in at least three dimensions; and (c) an elongate probe configured to snugly slidably advance and retract in the targeting cannula lumen, the elongate probe comprising at least one of a stimulation or recording electrode. In operation, the targeting cannula can be aligned with a first trajectory and positionally adjusted to provide a desired internal access path to a target location with a corresponding trajectory for the elongate probe. Automated systems for determining an MR scan plane associated with a trajectory and for determining mount adjustments are also described.

Velocity of MR-imaged fluid flows is measured. Data representing a measure of distance traveled by flowing fluid appearing in at least two MR images of a subject's tissue taken at different respective imaging times is generated. Data representing at least one fluid velocity measurement of the flowing fluid is generated by calculating at least one instance of distance traveled by the fluid divided by elapsed time during travel based on different respective imaging times. Data representing at least one fluid velocity measurement is then output to at least one of: (a) a display screen, (b) a non-transitory data storage medium, and (c) a remotely located site.

An apparatus and method for indicating locus of an ultrasonic probe configured to transmit and receive ultrasonic waves toward a part of a subject wherein a position or movement of the ultrasonic probe is detected, and a locus of the ultrasonic probe on an image of the part of the subject is indicated according to the detected position or movement.

Apparatus and methods are described including acquiring a first set of extraluminal images of a lumen, using an extraluminal imaging device. At least one of the first set of images is designated as a roadmap image. While an endoluminal device is being moved through the lumen, a second set of extraluminal images is acquired. A plurality of features that are visible within images belonging to the second set of extraluminal images are identified. In response to the identified features in the images belonging to the second set of extraluminal images, a plurality of local calibration factors associated with respective portions of the roadmap image are determined. Other applications are also described.

A process to prepared bridged bis(indenyl)ligands, comprising the step of reacting a 2-indenylpinacolyl borane compound with a bromosubstituted compound in the presence of a Pd catalyst and a base to form the corresponding bridged bis(indenyl) ligand. The process may further comprise the step of reacting a 2-bromo indene compound with pinacolborane in the presence of a Pd catalyst and a base to form the corresponding 2-indenylpinacolylborane compound. These bridged bis(indenyl)ligands may suitably be used in the preparation of metallocene complexes, such as 2,2'-bis(2-indenyl)biphenyl ZrCl2 and 1,2-bis(2-indenyl)benzene ZrCl2. These metallocene complexes may be used for the polymerization, optionally in the presence of a cocatalyst, of one or more α-olefins, preferably for the polymerization of ethylene.

The present invention provides methods of making stereo-enriched ansa-metallocene compounds using an unchelated amine compound. Generally, these methods result in a rac:meso isomer selectivity of the stereo-enriched ansa-metallocene compound of greater than 4:1.

The present weed reducing material reduces the necessary weed control work by making joint filling sand a hostile substrate for plant and fungus growth by using an environmentally acceptable slow release mineral additive. The additive, having similar grain size distribution, mechanical and rheological properties, forms an integral part of the joint filling sand. The specific gravity of the additive is lower than quartz sand imparting a tendency for the additive to migrate towards the top part of the joint. The additive leads to pore waters rich in sodium and at high pH, both qualities being maintained over long periods. The mixture of additive and sand is handled and applied using conventional laying techniques and equipment, observing usual precautions for mortar or cement mixes with sand. In the environment, reaction with CO2 in the air or in the soil porosity inactivates the causticity, yielding harmless carbonate salts.

The present invention discloses a method of inhibiting an ethylene response in a plant, comprising step of applying to at least one portion of the plant an effective ethylene response-inhibiting amount of a H1-cyclopropene-1-propanoic acid salt (CPAS). A method of prolonging the life of a cut flower, comprising applying to the cut flower an effective life-prolonging amount of CPAS and a method for the production a CPAS, comprising steps of (i) preparing 4-bromo-4-pentenoic acid or derivatives thereof; (ii) producing 1-cyclopropene-1-propanoic acid; and (iii), converting this acid into its water soluble salt, especially its sodium salt are presented. Additionally, a new family of water soluble CPAS inhibitors for ethylene response in a plant is disclosed.

A locking system for axially securing a rotor onto a rotatably mounted shaft. The arrangement includes a plurality of locking levers which are each pivotably mounted about axes extending perpendicularly to the shaft between a locking position and an unlocking position in planes containing the axes. The locking levers can each be automatically transferred between an unlocking position and a locking position depending on rotational speed. The locking levers are mounted on the rotor and an annular groove is provided on the shaft and engages with the locking levers in the locking position, wherein the locking levers are prestressed in the unlocking position. Advantageously, the rotor can be both installed and removed without tools by merely placing the rotor onto or removing the rotor from the shaft, in each case depending on rotational speed.

Vacuum deposited thin films of material are described to create an interface that non-preferentially interacts with different domains of an underlying block copolymer film. The non-preferential interface prevents formation of a wetting layer and influences the orientation of domains in the block copolymer. The purpose of the deposited polymer is to produce nanostructured features in a block copolymer film that can serve as lithographic patterns.

A method for localizing a needle to a nerve, the method comprising: using the needle to electrically stimulate the nerve, with a known current intensity, so as to evoke a nerve response;detecting the nerve response;analyzing the detected nerve response so as to identify at least one attribute of the same; andconfirming that the needle is in the immediate proximity of the nerve based upon known current intensity and at least one identified attribute of the detected nerve response.

Provided is a method of producing an electrophotographic photosensitive member having improved sensitivity and capable of outputting an image having less image defects due to a ghost phenomenon not only under a normal-temperature, normal-humidity environment but also under a low-temperature, low-humidity environment as a particularly severe condition. The method of producing a gallium phthalocyanine crystal includes subjecting a gallium phthalocyanine and a specific amine compound, which are added to a solvent, to a milling treatment to perform crystal transformation of the gallium phthalocyanine. In addition, the gallium phthalocyanine crystal is used in the photosensitive layer of the electrophotographic photosensitive member.