A digital pulse width modulation controller includes a pulse width modulation controller, a selection unit having at least one selector, a comparison unit having at least one comparator, and a signal conversion unit having at least one digital-to-analog converter. The digital-to-analog converter generates a reference current and/or voltage. The comparator receives the reference current and/or voltage, and performs a comparison operation to generate a comparison signal based on a feedback signal. The selector selects one selection signal to input into the pulse width modulation controller, which receives other parameters set by a user or the system at the same time so as to control characteristics of the digital pulse width modulation signals, thereby improving the electric properties of a loading circuit.

Techniques and mechanisms for configuring logic to implement a signal modulation. In an embodiment, the logic includes a finite impulse response (FIR) module comprising circuitry. The selection circuitry may be operable to concurrently receive signals from latch circuitry of the FIR module and, based on the signals, to select an input group of the selection circuitry and to output a voltage identifier. In another embodiment, configuration logic is operable to set an operational mode which determines a total number of concurrent input signals, received by the FIR module, which the FIR module will use to select an input group for generating an output representing a voltage level.

A circuit includes a switched modulator stage combining an information signal with a square wave carrier to produce a first modulated signal; and a second modulation stage forming additional steps in the first modulated signal to produce a second modulated signal.

A rail-to-rail comparator including a first comparison unit connected to a first terminal and configured to compare differential input signals to differential reference voltages; a second comparison unit connected to a second terminal and configured to compare the differential input signals to the differential reference voltages; and an output unit configured to be driven in response to a clock signal and to generate a complementary output signal according to comparison results of the first and second comparison units.

An example PWM includes a driver and a two-way oscillator. The oscillator includes, a first frequency adjust current source, a second frequency adjust current source, a capacitor, a switching reference and a comparator. The capacitor integrates a frequency adjust current by charging with the first frequency adjust current source. The capacitor subsequently integrates a second frequency adjust current by discharging with the second frequency adjust current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to an oscillator signal. The comparator compares the output of the switching reference with a voltage on the capacitor. The first and second frequency adjust current sources vary the first and second frequency adjust currents to vary the frequency of the PWM signal to spread energy of switching harmonics over a frequency band and to reduce EMI.

A time-varying formant is generated at a formant frequency by generating first and second harmonic phase signals having first and second harmonic numbers, respectively, in relation to a modulation frequency. The first and second harmonic phase signals are generated in proportion to a master phase signal, which varies at the modulation frequency, modulo a factor corresponding to their harmonic numbers. First and second sound signals, based on the first and second harmonic phase signals, are frequency modulated to create an arbitrarily rich harmonic spectrum, depending on an FM index. The time-varying formant is generated by generating a time-varying combination of the first and second harmonic sound signals, weighting the first and second harmonic sound signals in accordance with their spectral proximities to the formant frequency. One or more of the harmonic numbers are updated when the time-varying formant frequency passes the frequency of either sound signal.

A communications transmitter includes a baseband processor configured to generate amplitude, angle, in-phase and quadrature baseband signals and a combination modulator that is configurable to modulate in the polar domain and, alternatively, in the quadrature domain. The combination modulator includes a quadrature modulator and a separate and distinct angle modulator that is configured to serve as a local oscillator for the quadrature modulator. In one embodiment of the invention the combination modulator is configured to modulate in the quadrature domain when the transmitter is operating according to a first communications condition (e.g., first transmit power level or first modulation scheme) and is configured to modulate in the polar domain when the transmitter is operating according to a second communications condition (e.g., second transmit power level or second modulation scheme).

A device for mixing multiple (N) pulse density modulated (PDM) bit streams of a bit rate, the device comprises an input logic, an error accumulation circuit, an error correction circuit and an adder of more than N bits; wherein the device is arranged to output an output PDM bit stream that represents a mixture of the multiple input PDM bit streams; wherein the output PDM bit stream comprises a plurality of output PDM bits, wherein a certain output PDM bit of a plurality of output PDM bits that form the output PDM bit stream is generated during a certain clock cycle; wherein the input logic is arranged to select, during each fraction of the certain clock cycle, a current bit of a selected PDM bit stream, wherein different PDM bit streams are selected during different fragments of the certain clock cycle; wherein the error accumulation circuit is arranged to store intermediate values during a first fraction till a penultimate fraction of the certain clock signal and to store a last value during a last fraction of the certain clock signal.

The present invention relates to a switched-mode power supply apparatus and a corresponding method. For an effective compensation of non-linearities caused by dead-time and voltage drops in the switching power amplifier of the apparatus, an apparatus is proposed comprising a switching power amplifier (14) for amplifying a signal supplied by an external signal source (11) and for supplying a load voltage and/or load current to a load (15), and a control unit (12; 12b) for controlling the switching of said switching power amplifier based on a timing setting, said control unit being adapted for simulating the behavior of the switching power amplifier by predicting the average load voltage and/or load current for at least two, in particular a plurality of, timing settings for a desired load voltage and/or load current based on state information about the present state of the switching power amplifier.

A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result.

A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

Embodiments of digital high-speed bi-phase modulator and method for bi-phase modulation are generally described herein. In some embodiments, the digital high-speed bi-phase modulator comprises a high-speed digital divider, a high-speed digital multiplexer, and matched signal paths provided between the divider and the multiplexer. The high-speed digital divider is configured to receive a carrier signal and generate complementary output signals. The high-speed digital multiplexer is configured to switch between the complementary output signals and generate a bi-phase modulated output at a carrier frequency (fc) modulated with a bi-phase code. The bi-phase code may be provided to control inputs of the multiplexer.

A radio frequency generator includes a power control module, a frequency control module and a pulse generating module. The power control module is configured to generate a power signal indicating power levels for target states of a power amplifier. The frequency control module is configured to generate a frequency signal indicating frequencies for the target states of the power amplifier. The pulse generating module is configured to (i) supply an output signal to the power amplifier, (ii) recall at least one of a latest power level or a latest frequency for one of the target states of the power amplifier, and (iii) adjust a current power level and a current frequency of the output signal from a first state to a second state based on the power signal, the frequency signal, and at least one of the latest power level and the latest frequency of the power amplifier.

Provided is a method of generating a driving signal for driving a dual mode supply modulator for a power amplifier. The method includes obtaining an envelope of a complex baseband signal to be transmitted, comparing the envelope of the complex signal with a preset threshold value, when a current envelope of the complex signal is the preset threshold value or greater or when there is a result having the preset threshold value or greater in previous N comparisons, outputting a digital board output signal configured with a first logic level through a digital-to-analog converter; and when the current envelope of the complex signal is smaller than the preset threshold value and when there is no result having the preset threshold value or greater in the previous N comparisons, outputting a digital board output signal configured with a second logic level through the digital-to-analog converter.

In an embodiment, a method of producing a multi-level RF signal includes producing plurality of pulse-width modulated signals based on an input signal. The method further includes driving a corresponding plurality of parallel amplifiers with the plurality of pulse-width modulated signals by setting a parallel amplifier to have a first output impedance when a corresponding pulse-width modulated signal is in an active state and setting the parallel amplifier to have a second output impedance when the corresponding pulse-width is in an inactive state. The method also includes phase shifting the outputs of the plurality of parallel amplifiers, wherein phase shifting transforms the second output impedance into a third impedance that is higher than the second output impedance, and combining the phase shifted outputs.

A modulation apparatus for a class D switching amplifier is capable of reducing power consumption of an Electro-Migration Interface (EMI) of an output end and a gate driver end in a zero input signal. The modulation apparatus for a class D switching amplifier includes a control unit for detecting and outputting a control signal which is a common signal component of a first modulation signal modulated by using a first input signal and a second modulation signal modulated by using a second input signal; and is characterized by feedback of a first output signal, a second output signal and a common output signal outputted by using the first modulation signal, the second modulation signal and the control signal through an input of the modulation apparatus.

A communications system includes a target receiver having a passband and configured to receive an intended signal within the passband. The communications system also includes a jammer configured to jam the target receiver from receiving the intended signal. The jammer has at least one antenna, a jammer receiver coupled to the at least one antenna, a jammer transmitter coupled to the at least one antenna, and a controller configured to cooperate with the jammer receiver. The controller is configured to detect the intended signal and to generate an interfering signal comprising a continuous phase modulation (CPM) waveform having a constant envelope so that the interfering signal at least partially overlaps the passband of the target receiver.

In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.

A modulation method is provided. The modulation method includes the steps of receiving multiple sinusoidal signals, obtaining the maximum value of the sinusoidal signals, obtaining the median value of the sinusoidal signals, and obtaining the minimum value of the sinusoidal signals within a period to generate a difference between the maximum value and the minimum value, generating a difference according to an upper limit and a lower limit of a predetermined comparison value, and comparing the two differences to generate an optimized modulation signal.

An ultra-wide band frequency modulator is disclosed. The frequency modulator includes a direct modulation phase lock loop that receives a small component. The frequency modulator also includes a delay module that produces a plurality of delay lines. The frequency modulator further includes an edge selector that receives a large component and the plurality of delay lines.

The present invention relates to a digital modulation method and a corresponding modulator. The modulator comprises a transcoder (110) followed by a FIFO register (120) and a 2-PSK modulator (130). The transcoder codes a binary word of fixed size into a code word of variable size using a transcoding table. The transcoding table codes at least one first binary word, leading to a first number of phase transitions at the output of the modulator, into a second word of size greater than that of the first word, leading to, at the output of the modulator, a second number of phase transitions less than the first number of phase transitions.

The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.

A memristor-based emulator including a memristor circuit for use in digital modulation that includes a first current feedback operational amplifier (CFOA) having multiple terminals in communication with a capacitor Cd and in further communication with a resistor Ri. A second CFOA having multiple terminals is in communication with the first CFOA and is adapted to be in further communication with a voltage vM to provide an input current iM for integration by a capacitor Ci. A nonlinear resistor is in communication with the second CFOA. A third CFOA having multiple terminals is in communication with the nonlinear resistor and is in further communication with the first CFOA and a resistor Rd. The third CFOA and the resistor Rd act as an inverting amplifier associated with the nonlinear resistor to increase a current gain to increase a difference between ON and OFF values of a resistance of a realized memristor.

A method for phase modulation of a carrier signal from a transmitter to a contactless transponder in which data is coded as consecutive symbols, each corresponding to a predefined number of carrier cycles, and in which a symbol time is at least two cycles of the carrier signal includes, at the transmitter, spreading a phase jump of a symbol in relation to a preceding symbol over a first part of the symbol time. The establishment of the phase jump is completed in the first part of the symbol time. The periods of the cycles are constant during a second part of the symbol time.

A modulator which has a first terminal to receive a carrier signal, a second terminal to receive a first control signal to control a frequency band of the carrier signal and a third terminal to receive a second control signal to control a modulation depth of the carrier signal.

The present invention relates to a packing box for accommodation of plate bodies, which comprises a backplane, and a side plate vertically arranged at the periphery of the backplane, the plate body including a main body, and a PCB plate connected through a flexible sheet to the edge of the main body, a positioning member being further arranged in the space enclosed by the backplane and the side plate for preventing the PCB plate from moving relative to the main body. The positioning member of the present invention can prevent the PCB plate from moving relative to the main body of the plate body, playing a role in protecting the circuit on the flexible sheet and having low costs.

A wireless communication node (10) dynamically estimates passive intermodulation (PIM) interference coupled into the node's receive path from the transmission of a composite signal through the node's transmit path. The node (10) then cancels the estimated PIM interference in the receive path. In some embodiments, the node dynamically estimates the PIM interference as a function of the composite signal that models PIM interference generation and coupling in the node (10) according to one or more coefficients (30). The coefficients (30) may be determined by transmitting a test signal (34) during a test stage, when the node (10) is not scheduled to receive any signal. Later, when the composite signal (18) is transmitted, the node (10) uses the coefficients (10) to dynamically estimate and cancel the resulting PIM interference.

A radio frequency channel amplification module for communication satellite, comprises an input configured to convey an input radio frequency signal, an output configured to restore a pre-amplified output radio frequency signal intended to power a travelling wave tube amplifier that can be equipped with linearization means with predistortion, at least one first upstream gain control module arranged downstream of the input and one second downstream gain control module arranged downstream of the first upstream gain control module and upstream of any linearization means by predistortion. The channel amplification module also comprises an instantaneous power limiter intended to clip the peaks of the input radio frequency signals with a level exceeding a determined threshold value, the instantaneous power limiter being arranged in series between said first upstream gain control module and said second downstream gain control module.

A power converter with positive and negative supply rail outputs for feeding a single ended class D amplifier, the converter comprising a transformer arrangement, a supply pump reduction arrangement connected between the secondary windings and the positive and negative supply rail outputs, and a boost drive mode switching arrangement. A controller is adapted to control the power converter in a negate drive mode and a boost drive mode, wherein the output voltage in the boost mode is increased by means of the transformer and the boost drive mode switching arrangement. The output voltages on the positive and negative rails can be generated at two different output voltage levels without changing the duty cycle or dead time of the control signals.

Differential power amplifier circuitry includes a differential transistor pair, an input transformer, and biasing circuitry. The base contact of each transistor in the differential transistor pair may be coupled to the input transformer through a coupling capacitor. The coupling capacitors may be designed to resonate with the input transformer about a desired frequency range, thereby passing desirable signals to the differential transistor pair while blocking undesirable signals. The biasing circuitry may include a pair of emitter follower transistors, each coupled at the emitter to the base contact of each one of the transistors in the differential transistor pair and adapted to bias the differential transistor pair to maximize efficiency and stability.

A method of operating a switched-mode power supply (SMPS) for supplying power to a load circuit, which draws a supply current that varies with an input signal to the load circuit is disclosed. The method comprises monitoring the input signal and controlling the amount of accumulated energy transferred for consumption by the load circuit, in use, in accordance with the input signal.

One or more embodiments of the present invention pertain to an all solid-state microwave power module. The module includes a plurality of solid-state amplifiers configured to amplify a signal using a low power stage, a medium power stage, and a high power stage. The module also includes a power conditioner configured to activate a voltage sequencer (e.g., bias controller) when power is received from a power source. The voltage sequencer is configured to sequentially apply voltage to a gate of each amplifier and sequentially apply voltage to a drain of each amplifier.

A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×1016 cm−3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.

Systems and methods are provided for generating an amplitude modulation signal to a switchmode power amplifier. A DC to DC switch is configured to receive a DC input voltage and to provide a DC output voltage. A low dropout regulator is configured to provide the amplitude modulation signal according to a modulation control signal received by the low dropout regulator. A control circuit is configured to establish a nominal operating power level for the power amplifier via the amplitude modulation signal and to maintain a minimum voltage difference between the DC output voltage and the low dropout regulator output. A modulator control circuit is configured to provide the modulation control signal to the low dropout regulator. The modulator control circuit provides the transition from a high amplitude to a low amplitude and a transition from the low amplitude to the high amplitude at configurable first and second slopes, respectively.

A model railroad car coupler assembly comprises a coupler with an upper shank having a coupler knuckle at a distal portion and a flat proximal portion, a lower shank having a coupler thumb at a distal portion and a flat proximal portion, and a coil spring terminating in first and second end portions, with a first turn of the coupler spring interlocked with the upper shank and a second turn interlocked with the lower shank. A mounting box has a circular mounting post that accepts circular openings in the shanks permitting them to rotate relative to each other between a closed coupled position and an open uncoupling position. The spring end portions engage the mounting box to bias the shanks into their coupled position. The knuckle carries a ferrous actuating pin that cooperates with a magnetic pad along a track to rotate the upper shank into its open position.

Embodiments related to a self-contained coupler for model railroad rolling stock are provided. In one example, a self-contained coupler comprises a coupler assembly including a knuckle and an uncoupling assembly configured to operate the coupler assembly. The example uncoupling assembly includes a signal input for receiving a signal and a motivator coupled to the coupler assembly via a movable link, the motivator operative to adjust the knuckle from a first position to a second position responsive to the signal. The example uncoupling assembly also includes a housing including the motivator and a rolling stock mounting location for mounting the uncoupling assembly to an item of the model railroad rolling stock.

Processes for preparation of macroporous membranes having unusually high equilibrium protein binding capacities are described. Membranes include a self-supporting porous membrane substrate and a grafted polymeric film on the pore surfaces of the substrate. A polymeric film may be grafted to the porous membrane substrate using surface-initiated polymerization. The grafted polymer chains within the polymeric film can act as molecular ‘brushes’ or ‘tentacles’ in solution and can contain one or more capture chemistries for biomolecules. Membranes can be used in the separation and purification of biomolecules such as proteins, nucleic acids, virus or virus-like particles, endotoxins, and the like.

Disclosed is a pressurized hollow fiber membrane module that exhibits improved durability without deterioration in packing density and permeation flux. The pressurized hollow fiber membrane module includes a composite hollow fiber membrane comprising a tubular braid woven by yarns and a polymer film on the outer surface of the tubular braid. At least one of the yarns comprises a small-fineness filament and a medium-fineness filament. The small-fineness filament comprises first monofilaments having a fineness of 0.01 to 0.4 denier, the medium-fineness filament comprises second monofilaments having a fineness higher than 0.4 and lower than 3, and a ratio of thickness of the tubular braid to outer diameter thereof is 15 to 35%.

A patient wearable, continuously operating extracorporeal pump apparatus which accesses the patient's arterial venous pressure differential by applying external pressure to a subcutaneous graft that has been cannualized to modulate blood flow through an extracorporeal circuit and to drive the pump for delivering a medicament, such as an anticoagulant, to the site of an intravenous cannula to prevent clogging thereof and also to move a dialysate through a circuit, including a dialyzer and a dialysate rejuvenating cartridge, whereby kidney failure can be treated without recourse to prior art hemodialysis machines found in most treatment facilities. With slight modification, the present invention can be used to remove excess fluids from CHF patients, to remove toxins from the blood in those suffering from liver failure and to facilitate administration of insulin to diabetics and/or glucose to those having hypoglycemia.

There is provided in one aspect a nozzle boot arrangement for supporting a nozzle of a fuel dispensing unit, the nozzle including a spout and a base portion including a grip. The arrangement includes a nozzle boot including means for supporting the nozzle at the base portion thereof, and a section for receiving at least a portion of the spout. The arrangement also includes a stopper provided at said receiving section and formed separately from said nozzle boot. The stopper is arranged to cooperate with the spout to prevent the nozzle from falling about from the nozzle boot arrangement by rotation of the nozzle about said supporting means. According to further aspects, there is provided a fuel dispensing unit, a nozzle boot module and method of manufacturing a nozzle boot arrangement.

Efficiency of a switch mode power supply (SMPS) is optimized by operating the SMPS in an asynchronous mode when current being supplied therefrom is less than a certain current value and operating the SMPS in a synchronous mode when the current being supplied therefrom is equal to or greater than the certain current value. When the SMPS is operating in the synchronous mode high-side and low-side power transistors alternately turn on and off. When the SMPS is operating in the asynchronous mode only the high-side power transistor turns on and off and the low-side power transistor remains off. When charging a battery with the SMPS discharge of the battery is eliminated when operating in the asynchronous mode at a low current output.

Circuits and processes for detecting a peak value of an input signal are disclosed. In one example, a peak detector circuit may sample a line sense signal, determine the peak value of the line sense signal during a search window, and output a peak detection signal representative of the determined peak value. In a first mode, the peak detector circuit may cause the peak detection signal to be representative of the determined peak value from an immediately preceding search window. In a second mode, the peak detector circuit may cause the peak detection signal to follow the sampled line sense signal. The peak detector circuit may operate in the second mode in response to the sample of the line sense signal being greater than a peak value of the line sense signal from an immediately preceding search window by more than a threshold amount.

A method for controlling voltage crossing a power switch of a switched-mode power converter includes the steps of: controlling a switch frequency of the power switch of the switched-mode power converter to a first frequency as activating the switched-mode power converter; and then changing the switch frequency of the power switch to a second frequency after the switched-mode power converter is activated for a predetermined time; wherein the first frequency is lower than the second frequency.

In one implementation, a modular power converter having a reduced switching loss includes a package, a field-effect transistor (FET) including a gate terminal, a drain terminal, and a source terminal, and fabricated on a semiconductor die situated inside the package, and a driver circuit inside the package. The driver circuit is configured to drive the gate terminal of the FET. The driver circuit is further configured to sample a drain-to-source voltage (VDS) of the FET directly from the drain terminal and the source terminal, thereby enabling the reduced switching loss.

This disclosure relates to radio frequency (RF) power converters and methods of operating the same. In one embodiment, an RF power converter includes an RF switching converter, a low-drop out (LDO) regulation circuit, and an RF filter. The RF filter is coupled to receive a pulsed output voltage from the RF switching converter and a supply voltage from the LDO regulation circuit. The RF filter is operable to alternate between a first RF filter topology and a second RF filter topology. In the first RF filter topology, the RF filter is configured to convert the pulsed output voltage from a switching circuit into the supply voltage. The RF filter in the second RF filter topology is configured to filter the supply voltage from the LDO regulation circuit to reduce a ripple variation in a supply voltage level of the supply voltage. As such, the RF filter provides greater versatility.

A constant on-time switching converter includes a switching circuit, an on-time control circuit, a comparing circuit and a logic circuit. The switching circuit has a first switch and is configured to provide an output voltage to a load. The on-time control circuit generates an on-time control signal to control the on-time of the first switch. The comparing circuit compares the output voltage of the switching circuit with a reference signal and generates a comparison signal. The logic circuit generates a control signal to control the first switch based on the on-time control signal and the comparison signal. When the switching frequency of the switching circuit approaches an audible range, the switching converter enters into a sleep mode, the on-time control signal is reduced to increase the switching frequency of the switching circuit.

In various embodiments a controller for controlling the operation of a switched mode power supply is provided, the controller comprising: a first signal source configured to provide a first set of signals including a set signal and a clear signal, wherein the first set of signals may correspond to a first mode of operation of the switched mode power supply; a second signal source configured to provide a second set of signals including a set signal and a clear signal, wherein the second set of signals may correspond to a second mode of operation of the switched mode power supply; a selecting circuit coupled to the first signal source and to the second signal source, the selecting circuit being configured to select either the first set of signals or the second set of signals; a switching signal generating circuit coupled to the selecting circuit and configured to provide a switching signal to the switched mode power supply based on the set of signals received from the selecting circuit.

Systems and methods that provide control circuits having multiple sub-control inputs that control operation of a power electronics device (e.g., a power converter). Each of the multiple sub-control inputs are output from a separate sub-control circuit that includes a feedback circuit having an input tied to a common control node. The common control node is coupled to an input of a controller (e.g., a PWM controller). Outputs of each of the sub-control circuits are coupled to the common control node by a respective switch (e.g., diode, transistor, etc.) so that each of the sub-control circuits may be selectively coupled to the common control node to provide a control signal to a controller. Since components of each of the feedback compensations circuits are biased at a regulation voltage instead of a higher power supply voltage, the control circuit may switch between control modes with minimal delay.

A switched mode power supply provides a reduction of switching losses and increased efficiency. The switched mode power supply includes a first switch coupled to an input terminal configured to receive an input voltage, a second switch, an inductor and an output capacitor. The first switch and the second switch are coupled together at a node, the inductor is coupled between the node and an output terminal, and the output capacitor is coupled to the output terminal. The switched mode power supply further includes a transformer coupled between a control input of the first switch and the node and a pulse generator connected to a control input of the second switch. Further, the transformer includes at most two windings, in particular a primary winding and a secondary winding which are not directly connected to each other.

A device for accommodating objects, in particular for use in an airplane, comprises at least one panel. The panel has at least one outer edge which is provided with a rim in order to form a shock-absorbing edge. The rim comprises plastic that is integrally molded onto the outer edge of the panel. The device can be an airplane trolley, folding trolley, container or galley.