In this paper we study removable singularities for regular $(1,1/2)$-Lipschitz solutions of the heat equation in time varying domains. We introduce an associated Lipschitz caloric capacity and we study its metric and geometric properties and the connection with the $L^2$ boundedness of the singular integral whose kernel is given by the gradient of the fundamental solution of the heat equation.

This paper addresses the problem of efficiently achieving visual predictive control tasks. To this end, a memory of motion, containing a set of trajectories built off-line, is used for leveraging precomputation and dealing with difficult visual tasks. Standard regression techniques, such as k-nearest neighbors and Gaussian process regression, are used to query the memory and provide on-line a warm-start and a way point to the control optimization process. The proposed technique allows the control scheme to achieve high performance and, at the same time, keep the computational time limited. Simulation and experimental results, carried out with a 7-axis manipulator, show the effectiveness of the approach.

For decades, two-player (antagonistic) games on graphs have been a framework of choice for many important problems in theoretical computer science. A notorious one is controller synthesis, which can be rephrased through the game-theoretic metaphor as the quest for a winning strategy of the system in a game against its antagonistic environment. Depending on the specification, optimal strategies might be simple or quite complex, for example having to use (possibly infinite) memory. Hence, research strives to understand which settings allow for simple strategies.

In 2005, Gimbert and Zielonka provided a complete characterization of preference relations (a formal framework to model specifications and game objectives) that admit memoryless optimal strategies for both players. In the last fifteen years however, practical applications have driven the community toward games with complex or multiple objectives, where memory -- finite or infinite -- is almost always required. Despite much effort, the exact frontiers of the class of preference relations that admit finite-memory optimal strategies still elude us.

In this work, we establish a complete characterization of preference relations that admit optimal strategies using arena-independent finite memory, generalizing the work of Gimbert and Zielonka to the finite-memory case. We also prove an equivalent to their celebrated corollary of great practical interest: if both players have optimal (arena-independent-)finite-memory strategies in all one-player games, then it is also the case in all two-player games. Finally, we pinpoint the boundaries of our results with regard to the literature: our work completely covers the case of arena-independent memory (e.g., multiple parity objectives, lower- and upper-bounded energy objectives), and paves the way to the arena-dependent case (e.g., multiple lower-bounded energy objectives).

High-resolution remote sensing images (HRRSIs) contain substantial ground object information, such as texture, shape, and spatial location. Semantic segmentation, which is an important task for element extraction, has been widely used in processing mass HRRSIs. However, HRRSIs often exhibit large intraclass variance and small interclass variance due to the diversity and complexity of ground objects, thereby bringing great challenges to a semantic segmentation task. In this paper, we propose a new end-to-end semantic segmentation network, which integrates lightweight spatial and channel attention modules that can refine features adaptively. We compare our method with several classic methods on the ISPRS Vaihingen and Potsdam datasets. Experimental results show that our method can achieve better semantic segmentation results. The source codes are available at https://github.com/lehaifeng/SCAttNet.

Hypertension is a potentially unsafe health ailment, which can be indicated directly from the Blood pressure (BP). Hypertension always leads to other health complications. Continuous monitoring of BP is very important; however, cuff-based BP measurements are discrete and uncomfortable to the user. To address this need, a cuff-less, continuous and a non-invasive BP measurement system is proposed using Photoplethysmogram (PPG) signal and demographic features using machine learning (ML) algorithms. PPG signals were acquired from 219 subjects, which undergo pre-processing and feature extraction steps. Time, frequency and time-frequency domain features were extracted from the PPG and their derivative signals. Feature selection techniques were used to reduce the computational complexity and to decrease the chance of over-fitting the ML algorithms. The features were then used to train and evaluate ML algorithms. The best regression models were selected for Systolic BP (SBP) and Diastolic BP (DBP) estimation individually. Gaussian Process Regression (GPR) along with ReliefF feature selection algorithm outperforms other algorithms in estimating SBP and DBP with a root-mean-square error (RMSE) of 6.74 and 3.59 respectively. This ML model can be implemented in hardware systems to continuously monitor BP and avoid any critical health conditions due to sudden changes.

In the future we can expect that artificial intelligent agents, once deployed, will be required to learn continually from their experience during their operational lifetime. Such agents will also need to communicate with humans and other agents regarding the content of their experience, in the context of passing along their learnings, for the purpose of explaining their actions in specific circumstances or simply to relate more naturally to humans concerning experiences the agent acquires that are not necessarily related to their assigned tasks. We argue that to support these goals, an agent would benefit from an episodic memory; that is, a memory that encodes the agent's experience in such a way that the agent can relive the experience, communicate about it and use its past experience, inclusive of the agents own past actions, to learn more effective models and policies. In this short paper, we propose one potential approach to provide an AI agent with such capabilities. We draw upon the ever-growing body of work examining the function and operation of the Medial Temporal Lobe (MTL) in mammals to guide us in adding an episodic memory capability to an AI agent composed of artificial neural networks (ANNs). Based on that, we highlight important aspects to be considered in the memory organization and we propose an architecture combining ANNs and standard Computer Science techniques for supporting storage and retrieval of episodic memories. Despite being initial work, we hope this short paper can spark discussions around the creation of intelligent agents with memory or, at least, provide a different point of view on the subject.

This paper reviews the Challenge on Image Demoireing that was part of the New Trends in Image Restoration and Enhancement (NTIRE) workshop, held in conjunction with CVPR 2020. Demoireing is a difficult task of removing moire patterns from an image to reveal an underlying clean image. The challenge was divided into two tracks. Track 1 targeted the single image demoireing problem, which seeks to remove moire patterns from a single image. Track 2 focused on the burst demoireing problem, where a set of degraded moire images of the same scene were provided as input, with the goal of producing a single demoired image as output. The methods were ranked in terms of their fidelity, measured using the peak signal-to-noise ratio (PSNR) between the ground truth clean images and the restored images produced by the participants' methods. The tracks had 142 and 99 registered participants, respectively, with a total of 14 and 6 submissions in the final testing stage. The entries span the current state-of-the-art in image and burst image demoireing problems.

Homomorphic encryption (HE) allows direct computations on encrypted data. Despite numerous research efforts, the practicality of HE schemes remains to be demonstrated. In this regard, the enormous size of ciphertexts involved in HE computations degrades computational efficiency. Near-memory Processing (NMP) and Computing-in-memory (CiM) - paradigms where computation is done within the memory boundaries - represent architectural solutions for reducing latency and energy associated with data transfers in data-intensive applications such as HE. This paper introduces CiM-HE, a Computing-in-memory (CiM) architecture that can support operations for the B/FV scheme, a somewhat homomorphic encryption scheme for general computation. CiM-HE hardware consists of customized peripherals such as sense amplifiers, adders, bit-shifters, and sequencing circuits. The peripherals are based on CMOS technology, and could support computations with memory cells of different technologies. Circuit-level simulations are used to evaluate our CiM-HE framework assuming a 6T-SRAM memory. We compare our CiM-HE implementation against (i) two optimized CPU HE implementations, and (ii) an FPGA-based HE accelerator implementation. When compared to a CPU solution, CiM-HE obtains speedups between 4.6x and 9.1x, and energy savings between 266.4x and 532.8x for homomorphic multiplications (the most expensive HE operation). Also, a set of four end-to-end tasks, i.e., mean, variance, linear regression, and inference are up to 1.1x, 7.7x, 7.1x, and 7.5x faster (and 301.1x, 404.6x, 532.3x, and 532.8x more energy efficient). Compared to CPU-based HE in a previous work, CiM-HE obtain 14.3x speed-up and >2600x energy savings. Finally, our design offers 2.2x speed-up with 88.1x energy savings compared to a state-of-the-art FPGA-based accelerator.

“In computing, memoization or memoisation is an optimization technique used primarily to speed up computer programs by storing the results of expensive function calls and returning the cached result when the same inputs occur again” — Wikipedia article on memoization. 

I've written a two part article in Memoization in JavaScript. The first part explains the concept with basic implementation in JavaScript code. It details a way to apply the technique on function calls. It is generic to handle most JavaScript functions.

While not every musician has taken to the internet to perform live shows during the (almost) nationwide lockdown, it sure seems that way. At least, it does according to my social media feeds, which lean heavily on bands and solo artists.…

Forty years ago, Mount St. Helens in southwestern Washington was just days away from a devastating eruption. When the mountain finally did blow, after weeks of frequent quakes and ash belching, on the morning of May 18, 1980, it caused the deadliest and most economically destructive volcanic event in U.S. history.…

Virtually every musician starts out trying to copy their heroes.…

The chafing.…

A spiking neuron-based working memory device is provided. The spiking neuron-based working memory device includes an input interface configured to convert input spike signals into respective burst signals having predetermined forms, and output a sequence of the burst signals, the burst signals corresponding to the input spike signals in a burst structure, and two or more memory elements (MEs) configured to sequentially store features respectively corresponding to the outputted sequence of the burst signals, each of the MEs continuously outputting spike signals respectively corresponding to the stored features.

The present invention relates to a method for removing phosphorus-containing compounds from triglyceride-containing compositions.

Provided herein are processes of preparing sulfonated estolide compounds, and the removal of sulfonate residues from those compounds to provide desulfonated estolide base oils. Exemplary sulfonated estolide compounds include those selected from the formula: wherein z is an integer selected from 0 to 15; q is an integer selected from 0 to 15; x is, independently for each occurrence, an integer selected from 0 to 20; y is, independently for each occurrence, an integer selected 0 to 20; n is equal to or greater than 0; R6 is selected from —OH, optionally substituted alkyl, and optionally substituted aryl; and R2 is selected from hydrogen and optionally substituted alkyl that is saturated or unsaturated, and branched or unbranched, wherein each fatty acid chain residue of said compounds is independently optionally substituted.

The present application describes modulators of MCP-1 or CCR-2 of formula or stereoisomers or prodrugs or pharmaceutically acceptable salts thereof, wherein m, n, W, X, R1 and R6, are defined herein. In addition, methods of treating and preventing inflammatory diseases such as asthma and allergic diseases, as well as autoimmune pathologies such as rheumatoid arthritis and transplant rejection using modulators of formula (I) are disclosed.

Methods for removing parasites and in particular ectoparasites of vertebrates, in particular of mammals, and compositions for the implementation of this method.Methods for removing parasites of vertebrates, and in particular arthropods, mainly insects and Arachnida, wherein an effectively parasiticidal amount of a compound of formula (I) ##STR1## in particular of fipronil, is administered to the animal via an administration route which makes possible systemic distribution and good absorption.

Disclosed are a ferrocene-containing conductive polymer, an organic memory device using the conductive polymer and a method for fabricating the organic memory device. The conductive polymer may include a fluorenyl repeating unit, a thienyl repeating unit and a diarylferrocenyl repeating unit. The organic memory device may possess the advantages of rapid switching time, decreased operating voltage, decreased fabrication costs and increased reliability. Based on these advantages, the organic memory device may be used as a highly integrated, large-capacity memory device.

Shape memory and pseudoelastic martensitic behavior is enabled by a structure in which there is provided a crystalline ceramic material that is capable of undergoing a reversible martensitic transformation and forming martensitic domains, during such martensitic transformation, that have an elongated domain length. The ceramic material is configured as a ceramic material structure including a structural feature that is smaller than the elongated domain length of the ceramic material.

The present invention provides a process for removing oxygenate from an olefin stream comprising oxygenate, comprising providing to an oxygenate recovery zone the olefin stream comprising oxygenate and a solvent comprising ethanol, treating the olefin stream comprising oxygenate with the solvent, and retrieving from the oxygenate recovery zone at least one oxygenate-depleted olefinic product stream comprising olefin and a spent solvent comprising at least part of the oxygenate.

Disclosed is a method for removing weakly basic nitrogen compounds from a hydrocarbon feed stream by contacting the hydrocarbon feed stream with a basic catalyst to convert a portion of the weakly basic nitrogen compounds to basic nitrogen compounds. The method also includes contacting the hydrocarbon feed stream with an acidic adsorbent to adsorb the basic nitrogen compounds from the stream. The hydrocarbon feed stream comprises an aromatic compound and a weakly basic nitrogen compound.

Disclosed is a method for removing weakly basic nitrogen compounds from a hydrocarbon feed stream by contacting the hydrocarbon feed stream with acidic clay to produce a hydrocarbon effluent stream having a lower weakly basic nitrogen compound content relative to the hydrocarbon feed stream. The hydrocarbon feed stream comprises an aromatic compound and a weakly basic nitrogen compound.

A perpendicular spin-transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.

A nano-ionic memory device is provided. The memory device includes a substrate, a chemically inactive lower electrode provided on the substrate, a solid electrolyte layer provided on the lower electrode and including a silver (Ag)-doped telluride (Te)-based nano-material, and an oxidizable upper electrode provided on the electrolyte layer.

A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.

Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process.

An approach for introspection of a software component and generation of a conditional memory dump, a computing device executing an introspection program with respect to the software component is provided. An introspection system comprises one or more conditions for generating the conditional memory dump based on operations of the software component. In one aspect, a computing device detects, through an introspection program, whether the one or more conditions are satisfied by the software component based on information in an introspection analyzer of the introspection program. In addition, the computing device indicates, through the introspection program, if the one or more conditions are satisfied by the software component. In another aspect, responsive to the indication, the computing device generates the conditional memory dump through the introspection program.

Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.

A double data rate memory physical interface having self checking loopback logic on-chip is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of generating a set of test data values that comprise at least two data bits. Also disposed on the chip is a second linear feedback shift register. The second linear feedback shift register is capable of generating a set of expected data values that match the test data values. Further, an internal loopback error check element is disposed on the chip. The internal loopback error check element is used to compare the set of expected data values with the set of test data values.

An apparatus is equipped with a storage device including an error correction circuit. The apparatus performs a test of the storage device according to a predetermined testing procedure, and records a time-point at which error correction of the storage device has been performed by the error correction circuit during performance of the test. The apparatus determines, with predetermined accuracy, a first position within the storage device on which the error correction has been performed, based on a test speed at which the test is performed, a time-period from the time-point to current time, and a second position within the storage device on which the test is being performed at the current time. Then, the apparatus performs the test predetermined times on a range included in the storage device and including the first position, according to a testing procedure that has been used at the time-point.

Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory.

A method of operating a memory controller to control a memory device includes reading a read vector from the memory device and correcting one or more errors in the read vector, where a power consumed at the correcting is varied according to the number of errors in the read vector.

A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory that includes a three-dimensional (3D) memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event.

A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.

Example embodiments relate to a bad area managing method of a nonvolatile memory device. The nonvolatile memory device may include a plurality of memory blocks and each block may contain memory layers stacked on a substrate. According to example embodiments, a method includes accessing one of the memory blocks, judging whether the accessed memory block includes at least one memory layer containing a bad memory cell. If a bad memory cell is detected, the method may further include configuring the memory device to treat the at least one memory layer of the accessed memory block as a bad area.

The present invention intends to provide a method for removing radioactive cesium, or radioactive iodine and radioactive cesium that is simple and low-cost, further does not require an energy source such as electricity, moreover can take in and stably immobilize the removed radioactive substances within a solid, and can reduce the volume of radioactive waste as necessary, and to provide a hydrophilic resin composition using for the method for removing radioactive cesium, or radioactive iodine and radioactive cesium, and the object of the present invention is achieved by using a hydrophilic resin composition containing: at least one hydrophilic resin selected from the group consisting of a hydrophilic polyurethane resin, a hydrophilic polyurea resin, and a hydrophilic polyurethane-polyurea resin each having at least a hydrophilic segment; and a zeolite dispersed therein in a ratio of at least 1 to 200 mass parts relative to 100 mass parts of the hydrophilic resin.

A method and apparatus for the stabilization and safe removal of buried waste that is tested and classified as being transuranic or not transuranic waste and disposed accordingly. The buried waste (usually in vertical pipe units) is enclosed in a casing and ground and mixed with the surrounding soil. This process allows for chemical reactions to occur that stabilizes the mixture. The entire process is contained within the casing to avoid contamination. In situ or external testing is done for radio isotopes to classify the waste. If it is classified as transuranic the waste is removed in a controlled way into a retrieval enclosure and disposed off in drums. If the waste is not transuranic then grout is introduced into the mixture, allowed to set and the resulting monolith is removed and buried in trenches.

A treatment system and a method for removal of at least one halogenated compound, such as PCBs, found in contaminated systems are provided. The treatment system includes a polymer blanket for receiving at least one non-polar solvent. The halogenated compound permeates into or through a wall of the polymer blanket where it is solubilized with at least one non-polar solvent received by said polymer blanket forming a halogenated solvent mixture. This treatment system and method provides for the in situ removal of halogenated compounds from the contaminated system. In one embodiment, the halogenated solvent mixture is subjected to subsequent processes which destroy and/or degrade the halogenated compound.

A data collection unit obtains physiological data from a subject interface on a subject. The subject interface can be connected to the data collection unit. When the subject interface is connected to the data collection unit, subject interface contacts on the subject interface make contact with data collection unit contacts on the data collection unit. Some of the data collection unit contacts are for communicating physiological data from the subject interface to the data collection unit. Some of the contacts are for powering the data collection unit upon the subject interface being connected to the data collection unit and for powering down the data collection unit upon the subject interface being disconnected from the data collection unit.

Memory system operations are extended for a data processor by DMA, cache, or memory controller to include a DMA descriptor, including a set of operations and parameters for the operations, which provides for data compression and decompression during or in conjunction with processes for moving data between memory elements of the memory system. The set of operations can be configured to use the parameters and perform the operations of the DMA, cache, or memory controller. The DMA, cache, or memory controller can support moves between memory having a first access latency, such as memory integrated on the same chip as a processor core, and memory having a second access latency that is longer than the first access latency, such as memory on a different integrated circuit than the processor core.

The disclosure is related systems and methods for using operation durations of a data storage medium to generate random numbers. In one embodiment, a device may comprise a random number generator circuit configured to store a value representing a duration of an operation on the data storage medium, and generate a random number based on the value. Another embodiment may be a method comprising recording durations of access operations to a data storage medium, and generating a random number based on the durations.

A system (200) and a method (100) of operating a computing device to perform memoization are disclosed. The method includes determining whether a result of a function is stored in a cache and, if so, retrieving the result from the cache and, if not, calculating the result and storing it in the cache. The method (100) includes transforming (104) by the computing device at least one selected from the input parameters and the output parameters of the function, the transforming being based on an analysis of the function and its input arguments to establish whether or not there is a possible relationship reflecting redundancy among the input parameters and output parameters of the function. The transforming may include at least one of: use of symmetry, scaling, linear shift, interchanging of variables, inversion, polynomial and/or trigonometric transformations, spectral or logical transformations, fuzzy transformations, and systematic arrangement of parameters.

A variety of biomedical devices are provided which include thiol-ene or thiol-yne shape memory polymers. The biomedical devices of the invention are capable of exhibiting shape memory behavior at physiological temperatures and may be used in surgical procedures. Methods of making the devices of the invention are also provided.

In one exemplary embodiment, a computer-implemented method includes receiving, at a remote direct memory access (RDMA) device, a plurality of RDMA requests referencing a plurality of virtual pages. Data transfers are scheduled for the plurality of virtual pages, wherein the scheduling occurs at the RDMA device. The number of the virtual pages that are currently pinned is limited for the RDMA requests based on a predetermined pinned page limit.

A dispersed storage network memory includes a pool of storage nodes, where the pool of storage nodes stores a multitude of encoded data files. A storage node obtains and analyzes data access response performance data for each of the storage nodes to produce a modified data access response plan that includes identity of an undesired performing storage node and an alternative data access response for the undesired performing storage node. The storage nodes receive corresponding portions of a data access request for at least a portion of one of the multitude of encoded data files. The undesired performing storage node or another storage node processes one of the corresponding portions of the data access request in accordance with the alternative data access response.

A semiconductor memory device includes a selection signal generation unit configured to generate a plurality of selection signals that are sequentially activated, a path selection unit configured to select a transmission path of sequentially input information data in response to the plurality of selection signals, a plurality of first storage units, each configured to have a first storage completion time and store an output signal of the path selection unit, and a plurality of second storage units, each configured to have a second storage completion time, which is longer than the first storage completion time, and store a respective output signal of the plurality of first storage units.

A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.