A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. Firstly, a selected memory cell of the memory array is determined, wherein one of the plural bit lines connected with the selected memory cell is a selected bit line and the other bit lines are unselected bit lines. Then, the unselected bit lines are precharged to a precharge voltage. Then, the selected bit line is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to at least one result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.

To provide a magnetic element capable of performing skyrmion transfer, a skyrmion memory to which this magnetic element is applied, and a shift register, for example, a magnetic element capable of performing skyrmion transfer is provided, the magnetic element providing a transverse transfer arrangement in which the skyrmion is transferred substantially perpendicular to a current between an upstream electrode and a downstream electrode, and including a plurality of stable positions in which the skyrmion exists more stably than in other regions of a magnet, and a skyrmion sensor that detects a position of the skyrmion.

To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having a β-Mn type crystal structure. Also, to provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having an Au4Al type crystal structure.

A magnetic element capable of generating and erasing a skyrmion, including a magnet shaped as a thin layer and including a structure surrounded by a nonmagnetic material; a current path provided surrounding an end region including an end portion of the magnet, on one surface of the magnet; and a skyrmion sensor that detects the generation and erasing of the skyrmion. With Wm being width of the magnet and hm being height of the magnet, a size of the magnet, with the skyrmion of a diameter λ being generated, is such that 2λ>Wm>λ/2 and 2λ>hm>λ/2. With W being width of the end region in a direction parallel to the end portion of the magnet and h being height of the end region in a direction perpendicular to the end portion of the magnet, the end region is such that λ≧W>λ/4 and 2λ>h>λ/2.

A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.

An SRAM includes an SRAM array comprising a plurality of SRAM cells arranged in a matrix. Each of the SRAM cells includes six vertical field effect transistors. The SRAM array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region arranged in this order in the row direction, and the first to fourth conductive regions are separated by insulating regions from each other. The first, second and third conductive regions are coupled to sources of first conductive type VFETs, and the fourth conductive region is coupled to sources of second conductive type VFETs. The plurality of groups are arranged in the row direction such that the fourth conductive region of one group of conductive regions is adjacent to the first conductive region of adjacent one group of conductive regions.

A compact CMOS anti-fuse memory cell. In one aspect, an apparatus includes an N− well and an anti-fuse cell formed on the N− well. The anti-fuse cell includes a lightly doped drain (LDD) region deposited in the N− well, an oxide layer deposited on the N− well and having an overlapping region that overlaps the LDD region, and a control gate deposited on the oxide layer, wherein a bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the LDD region exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the LDD region, and wherein the leakage path is confined to occur in the overlapping region.

The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising:first and second conduction electrodes (201, 202);a channel zone (203) arranged between the first and second conduction electrodes;a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222);an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.

Provided is a magnetic element capable of generating one skyrmion and erasing the one skyrmion. The magnetic element includes a magnet shaped like a substantially rectangular flat plate, an upstream electrode connected to the magnet in a width Wm direction of the magnet and made of a non-magnetic metal, a downstream electrode connected to the magnet in the width Wm direction to oppose the upstream electrode and made of a non-magnetic metal, and a skyrmion sensor configured to detect the skyrmion. Here, a width Wm of the substantially rectangular magnet is such that 3·λ>Wm≧λ, where λ denotes a diameter of the skyrmion, a length Hm of the substantially rectangular magnet is such that 2·λ>Hm≧λ, and the magnet has a notch structure at the edge between the upstream electrode and the downstream electrode.

A magnetic memory of an embodiment includes: a first to third terminals; a magnetoresistive element including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second nonmagnetic layer including a first to third portions, the first portion being located between the second and the third portions, the second and third portions being electrically connected to the second and third terminals respectively, the first magnetic layer being disposed between the first portion and the first nonmagnetic layer; and a third nonmagnetic layer including a fourth to sixth portions, the fourth portion being located between the first portion and the first magnetic layer, the fifth portion including a first region extending from the magnetoresistive element to the second terminal, the sixth portion including a second region extending from the magnetoresistive element to the third terminal.

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.

A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.

A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

According to one embodiment, a semiconductor storage apparatus includes a memory cell array and a read circuit. The memory cell array includes a memory cell which is connected to a word line. A threshold voltage of the memory cell corresponds to a data value of multiple bits. The read circuit receives designation of one bit among the multiple bits, applies a first reading voltage and a second reading voltage corresponding to the designated bit to the word line, senses ON or OFF of the memory cell for each reading voltage, and outputs a first sensed value and a second sensed value after performing the sensing for each reading voltage. The first sensed value is a sensing result in a case where the first reading voltage is applied. The second sensed value is a sensing result in a case where the second reading voltage is applied.

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.

A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line.

A method of operating a nonvolatile memory device includes: first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first threshold voltage distribution after the first programming, and wherein the cell string includes a plurality of transistors; and second programming the target transistor of the cell string, wherein the first transistor has a second threshold voltage distribution after the second programming, wherein a width of the second threshold voltage distribution is less than a width of the first threshold voltage distribution.

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

According to one embodiment, a semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

A memory system may include a memory device including 0th to N-1th memory blocks, wherein N is a positive integer; and a controller having a first list and a second list, wherein the first list includes 0th to N-1th erase count values respectively for the 0th to N-1th memory blocks, wherein the second list includes 0th to N-1th difference values respectively for the 0th to N-1th memory blocks, wherein each of the 0th to N-1th difference values is a difference between an average value of the 0th to N-1th erase count values and each of the 0th to N-1th erase count values, wherein the controller selects a source block and a target block among the 0th to N-1th memory blocks depending on the 0th to N-th erase count values included in the first list and the 0th to N-1th difference values included in the second list to perform a wear leveling between the source block and the target block.

A array of electrically programmable fuse (eFuse) units includes at least one connecting switch connecting two adjacent eFuse units. Each eFuse unit includes an eFuse, a write switch for passing through a first portion of a write current, a read/write switch for passing through a second portion of the write current or a read current, and a common node. The eFuse, the write switch, the read/write switch, and the at least one connecting switch are connected to each other at the common node. By turning on and off the at least one connecting switch, the current is split among the eFuse units, so that the size of the write switch can be reduced, thus reducing the total area of the array.

Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The input/output (I/O) drive controller generates drive control signals and an input control signal for driving first and second global I/O lines in a first test mode or a second test mode. The data I/O unit drives the first global I/O line in response to an input data when a write operation is executed in the first test mode and to drive the first and second global I/O lines in response to the drive control signals when the write operation is executed in the second test mode. The data transmitter transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line in a memory cell array portion when the write operation is executed in the first test mode. The data transmitter also transfers the data on the first and second global I/O lines onto the first and second local I/O lines to store the data on the first and second global I/O lines in the memory cell array portion when the write operation is executed in the second test mode. Related methods are also provided.

An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.

In a communications system which complies with LTE including a base station which transmits data by using an OFDM (Orthogonal Frequency Division Multiplexing) method as a downlink access method, and a mobile terminal, in a case in which an uplink scheduling request signal is transmitted by using an S-RACH when an Ack/Nack signal is being transmitted by using an Ack/Nack exclusive channel, the transmission of the Ack/Nack signal is stopped while the uplink scheduling request signal is transmitted.

This disclosure describes methods, devices, and systems related to an OFDMA Distributed Channel Access. Devices are disclosed comprising: at least one processor; and at least one memory that stores computer-executable instructions, wherein the at least one processor is configured to access the at least one memory and execute the computer-executable instructions to identify a trigger frame received on the communication channel from the computing device. The at least one processor may determine an uplink frame to be sent to a computing device on a communication channel. The at least one processor may identify one or more random access resource allocations, wherein the one or more random access resource allocations are associated with the trigger frame. The at least one processor may assign a respective numerical value to each of the one or more random access resource allocations. The at least one processor may also select a numerical value based at least in part on a probability distribution. The at least one processor may also determine a particular resource allocation of the one or more random access resource allocations that corresponds to the numerical value. The at least one processor may also cause the uplink frame to be sent to the computing device using the particular resource allocation.

Embodiments of the present invention disclose a wireless access point, including: a first radio frequency module, a second radio frequency module, and a processor. A frequency band of the first radio frequency module is the same as that of the second radio frequency module; the first radio frequency module and the second radio frequency module work on different channels; a first transmit power upper limit of the first radio frequency module is greater than a second transmit power upper limit of the second radio frequency module; and the processor is configured to schedule a terminal whose signal strength is greater than a threshold to associate with the wireless access point by using the second radio frequency module. The complexity of hardware design for integrating two radio frequency modules of a same frequency band into one AP may be reduced.

A remote maintenance system includes a maintenance management apparatus connected to a user apparatus and a communication relay apparatus connected to a remote-controlled apparatus. The maintenance management apparatus transmits, to the communication relay apparatus, message data whose destination is unique identification information of a mobile communication network assigned in advance to the communication relay apparatus. The communication relay apparatus notifies the maintenance management apparatus of an IP address that is dynamically assigned to itself upon reception of the message data. The maintenance management apparatus transmits, to the communication relay apparatus, information on remote operation received from the user apparatus whose destination is the notified IP address. The communication relay apparatus relays, to the remote-controlled apparatus, the information on the remote control received from the maintenance management apparatus.

The stealthiness of a camouflage fabric product is enhanced by rendering the camouflage pattern in three dimensional relief. In one implementation, a treatment such as an anti-pill treatment is applied to selected portions of the pattern prior to a finishing process. In the case of a circular web fabric, the finishing process may involve fleecing the fabric. In this manner, a cost effective process is provided for constructing a three-dimensional relief camouflage fabric product.

A query statement, issued to a local database server, is re-written. The query references at least one of a first or a second object. The first object is remote with respect to the local database server, for accessing a first materialized view that is local or remote with respect to the local database server. The second object is local with respect to the local database server, to access a second materialized view that is remote with respect to the local database server. Rewriting the query can include dynamically tracking a staleness state associated with one or more of the materialized views.

A portable apparatus is removably and communicatively connectable to a network device to communicate authentication or authorization credentials of a user in connection with the user logging into or entering into a transaction with a network site. The apparatus includes a communications port to connect and disconnect the apparatus to and from the network device and to establish a communication link with the network device when connected thereto. A processor receives a secure message from the network security server via the port. The message has a PIN for authenticating the user to the network site, and is readable only by the apparatus. The processor either transfers, via the port, the received PIN to an application associated with the network site that is executing on the network device or causes the apparatus to display the received PIN for manual transfer to the application associated with the network site.

A moisture metering calibration method and system for, e.g., determining the moisture lumber within a lumber drying kiln is disclosed. Calibration of moisture indicative electrical signals obtained from, e.g., moisture sensing capacitive plates spaced apart within a stack of drying lumber is performed, wherein long lengths (e.g., up to 1000 linear feet or more) of coaxial cable can be used for transmitting the signals, and effectively removing signal anomalies induced in such cabling so that accurate lumber moisture measurements result. Such extended cable lengths provides flexibility with respect to placement of electronic moisture metering equipment. This flexibility allows such equipment to be placed in an environmentally-controlled enclosure, rather than on the weather exposed exterior of a kiln whose lumber is being monitored.

A locating beam and a robot linear motion unit having the same, wherein the locating beam comprises a first support beam and a second support beam which are parallel to each other, a crossbeam connected between the first support beam and the second support beam and is vertical to the beams, and a joints between the crossbeam and the beams is provided with a right-angle connecting piece. The robot linear motion unit includes a motion track and a transmission mechanism arranged along the extension direction of the motion track, and the motion track is arranged on a surface of the locating beam. Arranging the crossbeam and right-angle connecting pieces between the first support beam and the second support beam in the locating beam, improves the mechanical structure strength, reduces deflection deformation and twist deformation of the locating beam, and improves the impact resistance of the robot linear motion unit.

A motor drive assembly can prevent a two-way roller clutch of the current speed ratio and a two-way roller clutch of the next speed ratio from engaging simultaneously, and includes a first-speed friction plate formed with engaging protrusions on the first-speed side, and a shift ring formed with engaging recesses. While the shift ring is in a first-speed shift position SP1f, the engaging protrusions are adapted to be engaged in the engaging recesses, thereby preventing rotation of the shift ring relative to the first-speed friction plate. The shift ring is provided with projections on its inner periphery. The drive assembly further includes an annular protrusion formed with cutouts. When the projections are axially and circumferentially displaced from the respective cutouts, the projections are adapted to interfere with the annular protrusion, thereby preventing axial movement of the shift ring between the first-speed shift position SP1f and a second-speed shift position SP2f.

An injection-molded resin face gear that can suppress deterioration of gear accuracy caused by shrinkage of resin material after injection molding and allow accurate and smooth rotation transmission is provided. An injection-molded resin face gear 1 includes a boss 3, a disk-shaped web 4, and a teeth section 5. The boss 3 has an axis hole 2. The web 4 is formed on an outer circumferential side of the boss in an outward radial direction. The teeth section 5 is formed on an outer circumferential edge of the web 4. The teeth section 5 includes a cylindrical section 13, a disk-shaped section 14, and a plurality of teeth 15. The cylindrical section 13 is connected to the outer circumferential edge of the web 4. The disk-shaped section 14 is formed on one end side of the cylindrical section 13 in the outward radial direction. The teeth 15 are formed evenly spaced on an outer circumferential side of the cylindrical section 13 such that one side surface of the disk-shaped section 14 is a bottom land 16. The web 4, the cylindrical section 13, and the disk-shaped section 14 have almost the same thicknesses. The outer circumferential edge of the web 4 is connected between an end surface 19 and an end surface 22 of the cylindrical section 13, in almost the center in a direction along a rotational center axis CL.

An arrangement for adjusting the position of handlebars on a vehicle including a first mechanism for effecting rotation of the handlebars about a first axis in response to a first control signal; a second mechanism for effecting translation of the handlebars along a longitudinal axis in response to a second control signal; and a control system for providing the first and second control signals. In the illustrative embodiment, the inventive system includes a first support secured to the vehicle; a second support operationally coupled to the first support and adapted for rotational movement about a first axis; a first actuator for rotating the second support over an angular extent about the first axis; a third support coupled to the second support for translational movement along a second axis, the second axis being coaxial with a longitudinal axis of the third support and transverse to the first axis; a second actuator for effecting movement of the third support relative to the second support; and a control system for driving the first and second actuators.

A build up edge monitoring method is provided for performing online real-time detection and suppression of abnormal build up edges of cutters occurred in a CNC manufacturing process. Signal variation analysis and fast Fourier transform are used for analyzing signals and establishing an algorithm of diagnosing build up edges to improve the efficiency and reliability of the cutting abnormality diagnostics. A vibration acceleration signal is captured and filtered to a frequency exceeding 1.1 times of a blade passing frequency, and an occurrence of accumulated chips is determined according to a sudden increase of the vibration acceleration and whether the main vibration frequency of the current vibration signal determined by a fast Fourier transform analysis matches with the frequency of the build up edge characteristic, and a shutdown instruction is issued to a CNC controller to shut down a cutting machine.

A portable articulated arm coordinate measurement machine can include a base, a manually positionable articulated arm portion having opposed first and second ends, the arm portion including a plurality of connected arm segments, an electronic circuit that receives the position signals from the transducers, a first inclinometer coupled to the base, wherein the inclinometer is configured to produce a first electrical signal responsive to an angle of tilt of the base and an electrical system configured to record a first reading of the first inclinometer and a second reading of the first inclinometer, wherein the first reading is in response to at least one of a first force applied to the base and a third force applied to the mounting structure, wherein the second reading is in response to at least one of a second force applied to the base and a fourth force applied to the mounting structure.

A data comparison apparatus 1 includes: an image acquisition unit 42 that acquires data of a plurality of motions; an interval identification unit 45 that identifies a predetermined interval that is common in data of the plurality of motions; a time period comparison unit 47 that compares the plurality of motions in the identified predetermined interval; and a notification unit 50 that notifies information corresponding to a comparison result of the time period comparison unit 47.

The invention relates to an autonomous system for determining items of information representative of the movement of an articulated chain (CA—1, CA—2, CA—3) comprising at least two solid elements (ES1—1, ES2—1, ES1—2, ES2—2, ES3—2, ES1—3, ES2—3, ES3—3, ES4—3) and at least one articulation (ART1—1, ART1—2, ART2—2, ART1—3, ART2—3, ART3—3) connecting said two elements. The system comprises at least two devices (DISP1—1, DISP2—1, DISP1—2, DISP2—2, DISP3—2, DISP1—3, DISP2—3, DISP3—3, DISP4—3) for measuring inter-device distances, mounted fixedly on two distinct elements of said articulated chain and suitable for transmitting the measurements made. Moreover, the system comprises means for determining at least one distance separating two measuring devices based on at least one measurement supplied by a measuring device, and calculation means (CALC), mounted on said articulated chain, suitable for calculating items of information representative of the movement of said articulated chain based on the measurements transmitted by said devices for measuring inter-device distances.

An instrument and method for determining the location of the anatomical epicondylar axis between the condyles of a femur is provided. The instrument includes first and second gauges each for measuring a radius of a femoral condyle and a frame. At least one of the gauges is movably connected to the frame. The method includes positioning the measuring end of each gauge against a separate condyle of a femur, actuating a pivoting member of each gauge to determine the radius of each condyle, measuring the distance between the condyles, and determining the location of the anatomical epicondylar axis of the femur. A measurement can be taken from a measuring scale provided on the gauge and from another scale provided on the frame. Determining the location of the axis can further include performing a calculation utilizing the radii of the condyles and the distance between the condyles.

A method of operating a coordinate positioning apparatus comprising an articulated head having at least one rotational axis. The method comprises, in any suitable order, loading at least one interchangeable task module onto the articulated head; and loading at least one interchangeable task module counterweight on the articulated head. The at least one interchangeable task module counterweight at least partially counterbalances the weight of the at least one task module on the articulated head about the at least one axis.