A computer system, comprising at least one controlled execution space hosting an operating system and an application program; a vulnerability monitoring agent coupled to the controlled execution space; one or more vulnerability profiles coupled to the vulnerability monitoring agent, wherein each of the vulnerability profiles comprises an application program identifier, an operating system identifier, a vulnerability specification describing a vulnerability of an application program that the application program identifier indicates when executed with an operating system that the operating system identifier indicates, and a remedial action which when executed will remediate the vulnerability; wherein the vulnerability monitoring agent is configured to monitor execution of the operating system and the application program in the controlled execution space, to detect an anomaly associated with the vulnerability, to determine the remedial action for the operating system and application program based on one of the vulnerability profiles, and to cause the remedial action.

A machine for producing circular products such as bottoms and lids of casks comprising a machine base, a blank feeding station, a blank sawing station, a blank chamfering station and a blank positioning station provided on said base in a circumferentially spaced relationship, a vertical main drive shaft rotatably mounted in said base, blank support means fixedly mounted on said drive shaft and having a plurality of spaced blank support discs, blank holding-down means fixedly mounted on said drive shaft and having a plurality of arms each having a downwardly extending shaft on which a blank holding-down member is journalled in opposition to the associated one of said support discs to hold a blank therebetween.

A phase-locked loop circuit and method for providing for compensation for an offset. A phase-locked loop circuit comprises a phase detector, a compensation circuit, a loop filter, and a VCO. The phase detector is coupled to receive a first input signal and a second input signal. The phase detector is configured to output one or more of a plurality of output signals indicative of a difference between the first input signal and the second input signal. The compensation circuit is coupled to receive the output signals and to reduce a voltage offset between the output signals. The compensation circuit is further configured to provide a plurality of compensated output signals. The loop filter is coupled to receive the compensated control signals. The loop filter is configured to output a first control signal. The VCO is coupled to receive the first control signal and to output the second input signal based on the first control signal. A method of operating a phase-locked loop circuit comprises receiving and comparing a first input signal and a second input signal and providing output signals indicative of the comparison. The method compensates for a voltage offset between the output signals and provides compensated output signals indicative of the compensation. The method filters the compensated control signals and provides a control signal indicative of the filtration. The method provides the second input signal based on the first control signal. Lower skew between the input and output may be achieved.

An XY all-directional precision alignment platform is provided and includes an XY-axes moving platform including X-axis moving platform and Y-axis moving platform, the X-axis and Y-axis moving platforms being stacked together, and a θ-angle rotating platform, the θ-angle rotating platform stacked onto the carrier surface thereof; wherein the θ-angle rotating platform is driven to perform precise θ-angle rotation achieving 360° and is of a four-layered thickness only, achieving the goal of having a light and thin product.

A tractor includes a prime mover, a driven implement selectively engaged with the prime mover, and a switch for selectively engaging and disengaging the driven implement with the prime mover. The switch has three positions including a disengaged position, a momentary position, and an engaged position located between the disengaged position and the momentary position. The prime mover can be started with the switch in the disengaged position. The prime mover can be started with the switch in the engaged position when the switch was previously moved to the momentary position before being moved to the engaged position, such that after operation of the prime mover is stopped, the prime mover can be restarted without changing the position of the switch.

An electromechanical actuator for a movable flight control surface of an aircraft, the actuator comprising an electric motor having an outlet shaft with first and second directions of rotation, a movement transmission arranged to connect the outlet shaft of the motor to the movable flight control surface, and a control unit for controlling the motor. The transmission incorporates a pawl device arranged to oppose the transmission of movement in the first direction of rotation, and the control unit is connected to a pawl declutching member for declutching the pawl and enabling movement to be transmitted in the first direction of rotation.

A machining tool assembly for manufacturing a firearm lower receiver includes a first and second side jig which are configured to be disposed on opposite sides of the firearm lower receiver and configured to removably attach to one another securing the firearm lower receiver therebetween. A drill block jig is removably attachable to the first and second side jigs disposed above the top surface of the firearm lower receiver, wherein the drill block jig comprises a plurality of through holes. A template spacer jig is removably attachable to the first and second side jigs disposed above the top surface of the firearm lower receiver, wherein the template spacer jig comprises a spacer aperture disposed through a template spacer thickness. A first and second pocket templates are removably attachable and disposed onto the template spacer jig. A router support plate is disposed onto either the first or second pocket templates.

The six direction directing device includes a shaft, a rotation member, a driving source, and a guide member. The shaft extends in an X axis direction. The rotation member is rotatable around an inclined axis inclined at α deg with respect to the shaft. The rotation member has an xyz rectangular coordinate system. The rotation member further includes a spherical surface and an orbit portion formed around an x axis of the spherical surface. The guide member is fixed to an XYZ rectangular coordinate system. The orbit portion has such a shape that the y axis of the rotation member is sequentially directed in + and − directions on the U, V, and W axes that cross one another at intervals of 60 deg around the X axis when the rotation member is rotated in contact with the guide member by the rotation of the shaft.

Systems and methods for providing aircraft heading information are provided. In one embodiment, an attitude heading reference device comprises: at least one interface for receiving heading information from one or more IRUs; at least one set of gyroscopes and accelerometers; a memory device for storing data representing heading information received via the at least one interface; and a heading calculator coupled to the at least one interface, the at least one set of gyroscopes and accelerometers, and the memory device. The heading calculator generating a heading output signal based on heading information when reliable heading information is received over the at least one interface; the heading calculator generating the heading output signal based on data from the memory device regarding previously reliable heading information and an output of the at least one set of gyroscopes and accelerometers when reliable heading information is not received over the at least one interface.

A recreational or outdoor mirrored compass is comprised of a base member, a hinged cover with a mirror and a sighting window for sighting a land mark, and a vial assembly pivotally coupled to said base member. The vial assembly comprises a vial, a magnetized indicator member pivotally journaled in the vial and an azimuth ring. At least parts of the inner sides of the sighting window are tapered in the line of sight.

An archwire for use with a passive self-ligation orthodontic bracket is described and which includes a resilient main body which is received in the archwire slot, and which further has a predetermined width dimension, and a variable thickness dimension, and wherein the variable thickness dimension of the archwire can be varied so as to facilitate an adjustable application of a force to the passive self-ligation orthodontic bracket so as to achieve a clinician selectable and controllable second and third order movement of a patient's tooth.

Casting jigs, methods, and kits that may be used in manufacture of anatomical healing caps. A casting jig may include a body having one or more wells within the body, each well being open at a proximal end thereof and having a negative shape corresponding to an anatomical healing cuff body of a given tooth position. Each respective anatomical healing cuff body negative shape includes an asymmetrical cross-section and an irregular surface so that an anatomical healing cuff body having said shape is configured to provide substantially custom filling of at least an emergence portion of a void where a natural tooth once emerged or should have emerged from the void (e.g., in the case of a congenitally missing tooth). The casting jig may further include a socket at a distal end of each well that is configured to receive therein a dental implant or dental implant analog.

Techniques and methods for utilizing ion implantation to modify dental archwires are provided. An example of a method of ion implanting a wire target includes providing the wire target in an ion implant system, implanting ions into the wire target such that a color of the wire target material after the implanting exhibits a changed appearance from the color of the wire target material before the implanting, and removing the wire target from the ion implant system. An example of a copper-aluminum-nickel (CuAlNi) wire includes an ion implanted atomic species wherein a color of an implanted CuAlNi wire is white, off-white and/or silver and further wherein the implanted CuAlNi wire exhibits mechanical properties of an unimplanted CuAlNi wire.

A hydraulic circuit includes a clutch actuator operatively associated with a clutch that may be disposed in a transmission. A hydraulic fluid source supplies pressurized hydraulic fluid for the clutch actuator. To measure the filling rate of the hydraulic actuator, a reference actuator having a predetermined filling rate is disposed in parallel with the hydraulic actuator and in fluid communication with the hydraulic fluid source. If hydraulic pressure associated with the reference actuator does not correspond to the hydraulic pressure associated with the clutch actuator, a compensation valve can appropriately respond by selectively directing hydraulic fluid to or from the clutch actuator. In a further embodiment, the reference actuator and compensation valve may be replaced with an electrohydraulic valve utilizing feedback from the hydraulic pressure present at the inlet of the clutch actuator.

A hydraulic circuit includes a clutch actuator operatively with a clutch that may be disposed in a transmission. A hydraulic fluid source supplies pressurized hydraulic fluid for the clutch actuator. An on-off valve is disposed in fluid communication between the clutch actuator and the hydraulic fluid source; the on-off valve configured to fill the clutch actuator with hydraulic fluid. An accumulator is disposed in parallel with the on-off valve and in fluid communication with the clutch actuator. The accumulator is adapted to receive hydraulic fluid redirected from the clutch actuator and to provide a counter-pressure for modulating the clutch actuator.

A hair coloring composition comprising: a) dihydroxyacetone or a derivative thereof; b) from 0.2 to 10 wt % of the total composition of a cationic conditioning compound c) a sulphonic compound of formula: H2N—(CHR1}pS(—X)q—Y in which where p is an integer from 1 to 5, R1 is H or an alkyl group, X is O or S q is an integer from 0 or 1. Y is an alkyl group or hydroxyl group.

The invention relates to a self-contained and wireless monitoring device (10) for use in a washing machine (1) to indicate shortage of detergent in said washing machine. The monitoring device comprises a sensor (13) arranged to monitor detergent concentration in washing liquid (5) of said washing machine and to provide an alarm signal (A) when said monitored detergent concentration is below a target value. The monitoring device is capable of floating in said washing liquid and comprises signalling means (11) for indicating said shortage of detergent in response to said alarm signal. The invention further relates to a package containing such a monitoring device and a method for indicating shortage of detergent.

The present invention relates to dyes of the formula (I) in which R1 to R10, D1 and D2 are defined as given in claim 1, a process for preparing them, and their use for dyeing and printing hydroxyl- and/or carboxamido-containing materials.

The present invention provides dye mixtures containing at least one dye of formula (I) and at least one dye of formula (II) where T1, T2, R1 to R9 and n are each as defined in claim 1, processes for their preparation and their use.

The present invention relates to a hair dye composition, and more particularly, to a foam-type hair dye composition comprising: a first agent including a dye and an alkaline agent and a second agent including an oxidant; and a nonionic viscosity increasing agent of a PEG-aliphatic acid ester or a PPG-aliphatic acid ester in one or both of the first agent and the second agent, thereby largely improving dyeing properties without dripping after the composition is coated on hair.

A charge pump circuit includes a capacitor, a first switch between the capacitor and a power supply terminal, a second switch between the capacitor and an output terminal, a third switch between the output terminal and the capacitor, a fourth switch between the capacitor and a ground terminal, and a control unit configured to generate control signals for the switches. The control signals include first signals generated during a first period that cause first and third switches to be in an ON state and second and fourth switches to be in an OFF state, second signals generated during a second period that cause first and third switches to be in an OFF state and second and fourth switches to be in an ON state, and third signals generated between the first and second periods, that cause the ON/OFF state of each of the switches to be switched at different times.

A control switch is connected to a power supply voltage and turns on based on a control signal to output a current. A clamp circuit is connected to a load and performs clamp control of the output voltage of the control switch. A current control element conducts or shuts off a current based on the output voltage to be clamp-controlled. A selector switch group includes switches, and performs switching based on a voltage varying with the current control by the current control element, thereby switching between paths for generating an internal power supply. The switch circuit connects or disconnects the coupling between the clamp circuit and the selector switch group.

An active filter device and a circuit arrangement comprising an active filter device are disclosed. In an embodiment the active filter device includes sensor terminals for applying a sensor signal depending on a sensed noise signal, an output terminal for providing a correction signal that is suitable for reducing the noise signal, a signal source adapted for generating a correction signal and a high-pass filter coupled between the sensor terminals and the signal source, wherein the correction signal is generated with a dependence on a high-pass filtered sensor signal.

An SR latch circuit with single gate delay is provided. The circuit has an an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage.

A semiconductor device includes a first transistor and a clamping circuit. The first transistor is arranged to generate an output signal according to a control signal. The clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level.

A system includes a voltage-controlled oscillator (VCO) to generate an output signal based on an input voltage and a multi-stage delay network to receive the output signal from the VCO. Each stage of the delay network produces a phase-shifted output signal. The system includes a multi-stage digital-to-analog converter (DAC) network, where each stage of the DAC network is associated with a corresponding stage of the delay network. Each stage of the DAC network receives the phase-shifted output signal from its corresponding stage of the delay network and generates a weighted output signal based on the received phase-shifted output signal. The DAC network combines the weighted output signal of each stage. A weighting factor for each stage of the DAC network is selected to reduce harmonic content of the combination of weighted output signals.

The present disclosure relates to a delay control circuit arranged for adding delay to a signal. The delay control circuit includes a driver circuit arranged to receive a first signal and to output a second signal. The driver circuit includes a variable load arranged for outputting the second signal by adding delay to the first signal. The delay control circuit also includes a control circuit arranged to receive the first signal and to control the variable load of the driver circuit based on a current state of the first signal and on a control signal indicative of an amount of delay to be added to the first signal in the current state.

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

A load-driving circuit for receiving a supply of power from a power source and driving a load, wherein the load-driving circuit is provided with: a high-side switching element; a low-side switching element; a high-side current detection circuit connected in parallel to the high-side switching element, the high-side current detection circuit detecting a high-side driving current; and a fault detection circuit for detecting the fault state of the load-driving circuit from the output result of the high-side current detection circuit. The high-side current detection circuit is provided with a high-side sense switching circuit operating in response to a gate signal that is different from the high-side switching element, the high-side sense switching circuit comprising a device of the same type as the high-side switching element. The output result of the high-side current detection circuit, the gate signal of the high-side switching element, and the gate signal of the high-side sense switching element are input and the fault states are detected apart from each other when the connection terminal between the load-driving circuit and the load is in a state of short circuit with the positive electrode side of the power source or in a state of short circuit with the negative electrode side of the power source.

A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.

A transmission circuit includes: a first transistor, a first current source, a third transistor. The first transistor has a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit. The first current source is coupled between a gate terminal of the first transistor and a second reference voltage terminal of the transmission circuit. The third transistor has a drain terminal coupled to the first output terminal of the transmission circuit, a source terminal coupled to the second reference voltage terminal of the transmission circuit, and a gate terminal for receiving a first input signal. The first transistor is of a first conducting type, and the second transistor is of a second conducting type different from the first conducting type.

An integrated circuit includes a drive circuit with a first inverter circuit with a first transistor of a first conductivity type and a second transistor of a second conductivity type. The drains of the first and second transistors are connected. An output circuit is provided having a third transistor of the second conductivity with a gate connected to the drains of the first and second transistors. A capacitor is connected between the gate and a drain of the third transistor and has a capacitance greater than 0.5 pF and less than or equal to 3.0 pF. A gate width of the first transistor when divided by a gate width of the third transistor has a value of less than 1/100. The output circuit is configured to output a transmission signal from the drain of the third transistor.

A signal transfer circuit may include a pass gate coupled between first and second nodes; and a control unit suitable for controlling the pass gate to prevent a current flowing from the second node to the first node during turn-on of the pass gate.

A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.

A duty cycle correction circuit may include: a phase mixing section capable of mixing a first integrated signal generated by integrating a positive clock signal, with a first compensation signal generated by differentiating and integrating the positive clock signal and a negative clock signal, respectively, to generate a first phase-mixed signal, and mixing a second integrated signal generated by integrating the negative clock signal, with a second compensation signal generated by integrating and differentiating the positive clock signal and the negative clock signal, respectively, to generate a second phase-mixed signal; and a noise removal section capable of receiving and removing a common mode noise between the first phase-mixed signal and the second phase-mixed signal by adjusting a cross-point therebetween, and outputting first and second duty-corrected clock signals.

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

An apparatus includes an integrated circuit (IC). The IC includes a power controller, which includes a regulator and a controller. The regulator receives a plurality of input voltages and provides a regulated output voltage. The controller controls the regulator to generate the regulated output voltage from the plurality of input voltages. The power controller provides power to a load integrated in the IC from a set of arbitrary input voltages. The set of arbitrary input voltages includes the plurality of input voltages.

An example circuit includes: a slew rate driver configured to provide an output voltage; a first voltage provider configured to provide a first input voltage to the slew rate driver in response to the output voltage being within a first range; and a second voltage provider configured to provide a second input voltage to the slew rate driver in response to the output voltage being within a second range. The slew rate driver is further configured to change the output voltage based at least in part on the first input voltage or the second input voltage.

A circuit suitable for data backup of a logic circuit is provided. The circuit includes first to fourth nodes, a capacitor, first to third transistors, and first and second circuits. Data can be loaded and stored between the circuit and the logic circuit. The first node is electrically connected to a data output terminal of the logic circuit. The second node is electrically connected to a data input terminal of the logic circuit. The capacitor is electrically connected to the third node. The first transistor controls electrical continuity between the first node and the third node. The second transistor controls electrical continuity between the second node and the third node. The third transistor controls electrical continuity between the second node and the fourth node. The first and second circuits have functions of raising gate voltage of the first transistor and raising gate voltage of the second transistor, respectively.

To provide a clock selection circuit capable of reducing clock omission generated when switching from a state of being synchronized with a first clock to a second clock. The clock selection circuit is equipped with a clock detection circuit which detects a first clock to output a detected signal, a switch which outputs the first clock when the detected signal is at a first level and outputs a second clock when the detected signal is at a second level different from the first level, and a one-shot circuit which outputs a one-shot pulse in response to switching of the detected signal from the first level to the second level. The output of the switch and the output of the one-shot circuit are added to be outputted as an output clock.

A clock-signal generator circuit, for generating an output clock signal starting from an input clock signal, includes: a monostable stage having a clock input configured to receive the input clock signal, a control input configured to receive a control signal, and an output configured to supply the output clock signal having a duty cycle variable as a function of the control signal; and a feedback loop, operatively coupled to the monostable stage for generating the control signal as a function of a detected value, and of a desired value, of the duty cycle of the output clock signal.

A device (442) for producing a dynamic reference signal (UREF) for a control circuit for a power semiconductor switch comprises a reference signal generator (442) for providing a dynamic reference signal (UREF), which has a stationary signal level after elapse of a predefined time following a switching process of the power semiconductor switch, a passive charging circuit (450) which is configured to increase a signal level of the dynamic reference signal in reaction to a switching of a control signal of the power semiconductor switch from an OFF state to ON state for at least one part of the predefined time above the stationary signal level, in order to produce the dynamic reference signal and an output (A) for tapping the dynamic reference signal (UREF).

A half-bridge circuit comprises a high supply contact and a low supply contact. A half-bridge output contact is connectable to drive a load and has a high-side between the high supply contact and the half-bridge output contact and a low-side between the half-bridge output contact and the low supply contact. A high-side bidirectional vertical power transistor at the high-side has a source connected to the high supply contact, and a low-side bidirectional vertical power transistor at the low-side, transistor has a source connected to the low supply contact. The high-side bidirectional vertical power transistor and low-side bidirectional vertical power transistor are connected in cascode and share a common drain connected to the half-bridge output contact, and are controllable to alternatingly allow a current flow from the high supply contact to the half-bridge output contact or from the half-bridge output contact to the low supply contact.

A device for controlling a first control gate transistor, including: a second transistor and a third transistor series-connected between a first and a second terminals of application of a power supply voltage, the junction point of these transistors being connected to the gate of the first transistor; a terminal of application of a digital control signal; a circuit for generating an analog signal according to variations of the power supply voltage; and for each of the second and third transistors, a circuit of selection of a control signal of the first transistor representative of said digital signal or of said analog signal.

A driving circuit includes a first switching element operating in a turned-on state or a turned-off state depending on a control voltage; a second switching element operating complementarily to the first switching element depending on the control voltage; a constant voltage circuit unit turning on depending on a source-gate voltage of the first switching element to maintain a constant voltage; a current adjusting circuit operating in a turned-on state or a turned-off state depending on the control voltage, and adjusting an operating current flowing to a ground depending on a current control signal in the turned-on state of the current adjusting circuit; a current control circuit controlling the operating current by providing the current control signal to the current adjusting circuit in a turned-on state of the constant voltage circuit unit; and a signal transfer circuit providing the control voltage to a gate of the second switching element.

A radio-frequency (RF) switch includes a field-effect transistor (FET) disposed between a first node and a second node, the FET having a source, a drain, a gate, and a body. The RF switch further includes a coupling circuit including a first path and a second path, the first path being connected between the gate and one of the source or the drain via a first resistor in series with a first capacitor, the second path being connected between the body and the one of the source or the drain via a second resistor in series with a second capacitor, the coupling circuit configured to allow discharge of interface charge from either or both of the gate and body.

Circular comb for a combing machine for combing textile fibers, comprising a base body with a center longitudinal axis, a peripheral surface and two end faces, a plurality of bar tacks, which are arranged on the peripheral surface of the base body and define a combing region of the circular comb, a plurality of fastening devices attached to the base body for the non-positive connection of one of the bar tacks in each case to the base body and unlocking units to release the non-positive connections, each unlocking unit having an unlocking device and an unlocking means to actuate the unlocking device, wherein the unlocking units are accessible from outside the combing region, in particular from at least one of the end faces, and an additional positive securing connection to secure the bar tacks is provided on the base body.

The present invention refers to a process of making a fibrous structure, wherein roughly graded material is provided to rotating, apertured drums. The drums have at least one needle roll in their inside. The roughly graded material is agitated inside the drums, whereby fibers or small fiber clusters are separated from each other. These fibers and small fiber clusters are flung through the apertures to the outside of the drum, where they are directed onto a foraminous carrier to form a fibrous structure. The fibrous structures are especially useful in absorbent articles.

The present invention provides cellulose-based fibers including cellulose and at least one polymer selected from the group consisting of a polysiloxane, a polyacrylic acid, a polyacrylamide, an m-aramid, and a polyvinylalcohol/polystyrene copolymer, and a tire cord including the same. Furthermore, the cellulose-based fibers of the present invention have an advantage in superior elongation and tenacity of the prior cellulose fibers by blending at least one polymer having a functional group that is capable of a hydrogen bond with a hydroxyl group of a cellulose molecule.