Cadence Protium prototyping platforms rapidly bring up an SoC or system prototype and provide a pre-silicon platform for early software development, SoC verification, system validation, and hardware regressions. In this Training W ebinar, we will explore debugging using Save/Restart on Protium X2 . This feature saves execution time and lets you focus on actual debugging. The system state can be saved before the bug appears and restartS directly from there without spending time in initial execution. We’ll cover key concepts and applications, explore Save/Restart performance metrics, and provide examples to help you understand the concepts. Agenda: The key concepts of debugging using save/restart Capabilities, limitations, and performance metrics Some examples to enable and use save/restart on the Protium X2 system Date and Time Thursday, November 7, 2024 07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Munich / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing REGISTER To register for this webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System*. Then select Enrol to register for the session. Once registered, you’ll receive a confirmation email containing all login details. A quick reminder: If you haven’t received a registration confirmation within 1 hour of registering, please check your spam folder and ensure your pop-up blockers are off and cookies are enabled. For issues with registration or other inquiries, reach out to eur_training_webinars@cadence.com . Want to See More Webinars? You can find recordings of all past webinars here Like This Topic? Take this opportunity and register for the free online course related to this webinar topic: Protium Introduction Training The course includes slides with audio and downloadable lab exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training. Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe . Hungry for Training? Choose the Cadence Training Menu that’s right for you. To view our complete training offerings, visit the Cadence Training website . Related Courses Protium Introduction Training Course | Cadence Palladium Introduction Training Course | Cadence Related Blogs Training Insights – A New Free Online Course on the Protium System for Beginner and Advanced Users Training Insights – Palladium Emulation Course for Beginner and Advanced Users Related Training Bytes Protium Flow Steps for Running Design on Protium System ICE and IXCOM mode comparison ICE compile flow IXCOM compile flow PATH settings for using Protium System Please see the course learning maps for a visual representation of courses and course relationships. Regional course catalogs may be viewed here

hi,

     I save the waveform file of the oscilloscope as CSV file format.

     Now, I need to use this waveform file as the source of the low-pass filter .

     I searched and read the PSPICE help documents, and did not find any  methods. 

     How to realize it?

     Are there any reference documents or examples?

     Thanks!

When the Arduino Mega2560 is added to the first serial port, the dynamic memory is 2000 bytes, and when the second serial serial is added, the dynamic memory is 4000 bytes. Now I need to add the third Serial serial port. The dynamic memory is 6000 bytes. Due to the many variables in the program itself, the dynamic memory is not enough. Please help me how to save the dynamic memory?

Hello,

I am new in formal verification and I have a concept question about how to verify an I2C Slave block.

I think the response should be valid for any serial interface which needs to receive information for several clocks before making an action.

The the protocol description is the following: 

I have a serial clock (SCL), Serial Data Input (SDI) and Serial Data Output (SDO), all are ports of the I2C Slave block.

The protocol looks like this:

The first byte which is received by the slave consists in 7bits of sensor address and the 8th bit is the command 0/1 Write/Read.

After the first 8 bits, the slave sends an ACK (SDO = 1 for 1 clock) if the sensor address is correct.

Lets consider only this case, where I want to verify that the slave responds with an ACK if the sensor address is correct.

The only solution I found so far was to use the internal buffer from the block which saves the received bits during 8 clocks. The signal is called shift_s.

I also needed to use internal chip state (state_s) and an internal counter (shift_count_s).

Instead of doing an direct check of the SDO(sdo_o) depending on SDI (sdi_d_i), I used the internal shift_s register.

My question is if my approach is the correct one or there is a possibility to write the verification at a blackbox level.

Below you have the 2 properties: first checks connection from SDI to internal buffer, the second checks the connection between internal buffer and output.

property prop_i2c_sdi_store;
  @(posedge sclk_n_i)
  $past(i2c_bl.state_s == `STATE_RECEIVE_I2C_ADDR)
    |-> i2c_bl.shift_s == byte'({ $past(i2c_bl.shift_s), $past(sdi_d_i)});
endproperty
APF_I2C_CHECK_SDI_STORE: assert property(prop_i2c_sdi_store);

property prop_i2c_sensor_addr(sens_addr_sel, sens_addr);
@(posedge sclk_n_i) (i2c_bl.state_s == `STATE_RECEIVE_I2C_ADDR) && (i2c_addr_i == sens_addr_sel) && (i2c_bl.shift_count_s == 7)
  ##1 (i2c_bl.shift_s inside {sens_addr, sens_addr+1}) |-> sdo_o;
endproperty
APF_I2C_CHECK_SENSOR_ADDR0: assert property(prop_i2c_sensor_addr(0, `I2C_SENSOR_ADDRESS_A0));
APF_I2C_CHECK_SENSOR_ADDR1: assert property(prop_i2c_sensor_addr(1, `I2C_SENSOR_ADDRESS_A1));
APF_I2C_CHECK_SENSOR_ADDR2: assert property(prop_i2c_sensor_addr(2, `I2C_SENSOR_ADDRESS_A2));
APF_I2C_CHECK_SENSOR_ADDR3: assert property(prop_i2c_sensor_addr(3, `I2C_SENSOR_ADDRESS_A3));

PS: i2c_addr_i is address selection for the slave (there are 4 configurable sensor addresses, but this is not important for the case).

Thank you!

This is the 24th installment of The Rationalist, my column for the Times of India.

Back in the last decade, I was a cricket journalist for a few years. Then, around 12 years ago, I quit. I was jaded as hell. Every game seemed like déjà vu, nothing new, just another round on the treadmill. Although I would remember her fondly, I thought me and cricket were done.

And then I fell in love again. Cricket has changed in the last few years in glorious ways. There have been new ways of thinking about the game. There have been new ways of playing the game. Every season, new kinds of drama form, new nuances spring up into sight. This is true even of what had once seemed the dullest form of the game, one-day cricket. We are entering into a brave new world, and the team leading us there is England. No matter what happens in the World Cup final today – a single game involves a huge amount of luck – this England side are extraordinary. They are the bridge between eras, leading us into a Golden Age of Cricket.

I know that sounds hyperbolic, so let me stun you further by saying that I give the IPL credit for this. And now, having woken up you up with such a jolt on this lovely Sunday morning, let me explain.

Twenty20 cricket changed the game in two fundamental ways. Both ended up changing one-day cricket. The first was strategy.

When the first T20 games took place, teams applied an ODI template to innings-building: pinch-hit, build, slog. But this was not an optimal approach. In ODIs, teams have 11 players over 50 overs. In T20s, they have 11 players over 20 overs. The equation between resources and constraints is different. This means that the cost of a wicket goes down, and the cost of a dot ball goes up. Critically, it means that the value of aggression rises. A team need not follow the ODI template. In some instances, attacking for all 20 overs – or as I call it, ‘frontloading’ – may be optimal.

West Indies won the T20 World Cup in 2016 by doing just this, and England played similarly. And some sides began to realise was that they had been underestimating the value of aggression in one-day cricket as well.

The second fundamental way in which T20 cricket changed cricket was in terms of skills. The IPL and other leagues brought big money into the game. This changed incentives for budding cricketers. Relatively few people break into Test or ODI cricket, and play for their countries. A much wider pool can aspire to play T20 cricket – which also provides much more money. So it makes sense to spend the hundreds of hours you are in the nets honing T20 skills rather than Test match skills. Go to any nets practice, and you will find many more kids practising innovative aggressive strokes than playing the forward defensive.

As a result, batsmen today have a wider array of attacking strokes than earlier generations. Because every run counts more in T20 cricket, the standard of fielding has also shot up. And bowlers have also reacted to this by expanding their arsenal of tricks. Everyone has had to lift their game.

In one-day cricket, thus, two things have happened. One, there is better strategic understanding about the value of aggression. Two, batsmen are better equipped to act on the aggressive imperative. The game has continued to evolve.

Bowlers have reacted to this with greater aggression on their part, and this ongoing dialogue has been fascinating. The cricket writer Gideon Haigh once told me on my podcast that the 2015 World Cup featured a battle between T20 batting and Test match bowling.

This England team is the high watermark so far. Their aggression does not come from slogging. They bat with a combination of intent and skills that allows them to coast at 6-an-over, without needing to take too many risks. In normal conditions, thus, they can coast to 300 – any hitting they do beyond that is the bonus that takes them to 350 or 400. It’s a whole new level, illustrated by the fact that at one point a few days ago, they had seven consecutive scores of 300 to their name. Look at their scores over the last few years, in fact, and it is clear that this is the greatest batting side in the history of one-day cricket – by a margin.

There have been stumbles in this World Cup, but in the bigger picture, those are outliers. If England have a bad day in the final and New Zealand play their A-game, England might even lose today. But if Captain Morgan’s men play their A-game, they will coast to victory. New Zealand does not have those gears. No other team in the world does – for now.

But one day, they will all have to learn to play like this.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

Hello Everybody

Recently, I want to design a high output Power Amplifier at 2.4GHz using TSMC 1P6M CMOS Bulk Process. I use its nmos_rf_25_6t transistor model to determine the approximate mosfet size

I use the most common Common-Source Differential Amplifier topology with neutralizing capacitor to improve its stability and power gain performance

Because I want to output large power, the size of mosfet is very large, the gate width is about 2mm, when I perform harmonic balance analysis, everything is alright, the OP1dB is about 28dBm (0.63Watt)

But When I perform Transient simulation, the magnitude of voltage and current waveform at the saturation point is too small, for voltgae, Vpeaking is about 50mV, for current, Ipeaking is about 5mA

I assume some reasons: the bsim4 model is not complete/ the virtuoso version is wrong (My virtuoso version is IC6.1.7-64b.500.21)/the spectre version is wrong (spectre version is 15.1.0 32bit)/the MMSIM version is wrong/Transient Simulation setting is wrong (the algorithm is select gear2only, but when I select other, like: trap, the results have no difference), the maxstep I set 5ps, minstep I set 2ps to improve simulation speed, I think this step is much smaller than the fundamental period (1/2.4e9≈416ps)

I have no idea how to solve this problem, please help me! Thank you very very much!

Hi,

Do anyone know if it's possible in simvision waveform viewer to see a timestamp of where uvm_errors/$errors occurred in a simulation via post-processing? 

Cheers,

Antonio

I'm trying to use Jasper for checking parameter propagation in a large design. I have a list of top-level parameters, each with a HDL path of a module parameter somewhere lower in the hierarchy that's supposed to receive its value from the top-level module. The FPV app seems like an excellent tool for this, but elaborating the entire design in it is extremely time-consuming and memory-intensive. So, I'm trying to black-box everything but the interesting HDL paths. I thought using `elaborate -top dut_module_name -bbox_i * -no_bbox_i inst_foo -no_bbox_i inst_bar (...)` would work, but it doesn't. Jasper just starts flooding the log with warnings from modules that are definitely not on the whitebox list, and eventually dies due to insufficient memory. When I use -bbox_m * it correctly elaborates the top-level module with all of its sub-modules black-boxed. But then the -no_bbox_i switches have no effect. Could anyone suggest a working solution for this use case?

Hello,

I am aware of command script .svcf file that saves signals and loads them in while opening Simvision.

I am wondering, if there is a way for saving signals while we are in an interactive session and loading them next time when we open Simvision interactively.

Any ideas on how to do this?

Thank you in advance.

Swetha. C

I'm working on the code coverage. Doing a metrics analysis by default we see overall average grade and overall covered. But when i do a block analysis on an instance i see overall covered grade, code covered grade, block covered grade, statement covered grade, expression covered grade, toggle covered grade.

As I dont know the difference I started to read the IMC user guide and came to know there are 3 things we come across while doing a code coverage local, covered, average

From my understanding

local - child instances metrics doesnt reach the parent level. For example, we have an instance Q and its sub instances like Q.a, Q.b. Block Local grade of Q can be 100% even when its instances Q.a and Q.b a block local grades isnt at 100%.

In the attached image there is formula 

The key difference between average and covered is the weights.

Average : Mathematically taking the above scenario where Q.a, and Q.b has 10 blocks each. Q.a has covered 8 blocks and q.b has covered 2 blocks. Now if we take the normal average it should be total covered/ totatl number = 8+2/10+10 yielding 50%. But when we add weights saying Q.a is 70% and Q.b is 30% the new number would be (8*0.7+2*0.3) / (10*0.7+10*0.3) resulting 62%. Because of the weights we see 12% bump.

Covered: there is no role of weights.

Among these 3 metrics i've changed my default view to this in the image to get more realistic picture when i do analyze metrics. Do you guys agree with the approach?

Hello,

First, I had something working that broke in the past few versions that I've been meaning to get working again. There was some setting I recall in the GUI that allowed me to have inputs be placed in the waveform viewer with yellow traces, and output signals with orange traces to match the name colors. How can I set this to happen in the .simvisionrc file?

Second, I would like to add something to my .simvisionrc file to go through foreach signal and depending on key locations based on the signal's Path.Name (mainly the model and design areas) such that if the path contains "mon", then to auto-set the trace and name colors to something such as cyan. I'd like to have loops for various key areas of the design to color-code the signals.

Third, I am interested if there is a possibility of coloring names/traces foregound colors to based on which position they are in the waveform viewer to make banding, ideally such that every three (or whatever) are one color (or a color mutation, adding some gray to signals colorized by the auto-coloring mentioned already, etc) that allows for the signal names/traces to be colorized along with the built-in optional black/gray background banding.

Thanks in advance

Hello Everybody

Recently, I want to design a high output Power Amplifier at 2.4GHz using TSMC 1P6M CMOS Bulk Process. I use its nmos_rf_25_6t transistor model to determine the approximate mosfet size

I use the most common Common-Source Differential Amplifier topology with neutralizing capacitor to improve its stability and power gain performance

Because I want to output large power, the size of mosfet is very large, the gate width is about 2mm, when I perform harmonic balance analysis, everything is alright, the OP1dB is about 28dBm (0.63Watt)

But When I perform Transient simulation, the magnitude of voltage and current waveform at the saturation point is too small, for voltgae, Vpeaking is about 50mV, for current, Ipeaking is about 5mA

I assume some reasons: the bsim4 model is not complete/ the virtuoso version is wrong (My virtuoso version is IC6.1.7-64b.500.21)/the spectre version is wrong (spectre version is 15.1.0 32bit)/the MMSIM version is wrong/Transient Simulation setting is wrong (the algorithm is select gear2only, but when I select other, like: trap, the results have no difference), the maxstep I set 5ps, minstep I set 2ps to improve simulation speed, I think this step is much smaller than the fundamental period (1/2.4e9≈416ps)

I have no idea how to solve this problem, please help me! Thank you very very much!

Poor infrastructure and political instability deter tourism, but small and manageable steps to avoid chaos and promote hospitality can work wonders.

The chief executive of Ras Al Khaimah Economic Zone (RAKEZ), shares his views over the perks of free zones in emerging markets. 

We're already deeply into the discovery phase of the 2025 model year. With it, as usual, have come a stellar crop of new vehicles—everything from the high and mighty Chevy Corvette ZR1 to the cheeky, efficient Honda Civic Hybrid. But on the sadder end of the spectrum, we're tallying the list of vehicles that didn't make the cut—the...

Want a pickup truck but don’t want the hangups of a full-size truck? Ford has you covered with two compelling pickup options. The Ford Ranger midsize pickup truck has a crew cab and 5-foot bed like the F-150, and it also has a Raptor off-road model. With a 7,500-pound towing capacity, it can’t tow or haul as much as an F-150, but...

Through AI-powered photo restoration, NVIDIA's RTX technology ensures that historic photos are preserved for future generations.

As of Nov. 12, Apple’s 2024 MacBook Air with the new M3 chip is $200 off at Amazon, priced at $899.

Save 57% on a pair of refurbished Dyson Corrale straighteners at Walmart.

The Shark Pet Pro cordless stick vacuum is just $144 at Walmart, down from the normal price of $249.99. That's a 42% discount.

Govee lights are up to 24% off during Walmart's Black Friday sale

The best Black Friday VPN deal is on Proton VPN. Save 70% on a two-year plan.

Austrade is seeking feedback on options to improve the Export Market Development Grants (EMDG) program.

Lee Seung-woong didn’t have an auspicious start when he first came to Shanghai from South Korea in 2005 and worked in an Italian restaurant.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Tehran, Iran — A militant attack near the Pakistani border with Iran left five Iranian forces dead, the state-run IRNA news agency reported Sunday. The report said the dead were ethnic Baluch members of the paramilitary Revolutionary Guard's volunteer Basij force and were killed in Saravan city in Sistan and Baluchistan province. Saravan is some 1,400 km (870 miles) southeast of the capital Tehran. No group immediately claimed responsibility for the attack. Earlier in the day, state TV reported that Revolutionary Guard forces killed three terrorists and arrested nine others in a military operation. The report did not specify which group the suspects belonged to. Last month, unknown gunmen killed four people, including the chief of the Revolutionary Guard in the province. In September, gunmen killed four border guards in Sistan and Baluchistan province in two separate attacks. The militant group Jaish al-Adl, which seeks greater rights for the ethnic Baluch minority, claimed responsibility for one attack in which one officer and two soldiers were killed. The province, which borders Afghanistan and Pakistan, has been the site of occasional deadly clashes involving militant groups, armed drug smugglers and Iranian security forces. It is one of the least developed parts of Iran. Relations between the predominantly Sunni Muslim residents of the region and Iran's Shiite theocracy have long been strained.

La enseñanza bíblica en profundidad de John MacArthur lleva la verdad transformadora de la Palabra de Dios a millones de personas cada día.