Disclosed is an epoxy resin composition used for encapsulation of a semiconductor containing an epoxy resin (A), a curing agent (B), an inorganic filler (C) and a mold releasing agent, in which the mold releasing agent contains a compound (D) having a copolymer of an α-olefin having 28 to 60 carbon atoms and a maleic anhydride esterified with a long chain aliphatic alcohol having 10 to 25 carbon atoms.

An approach for introspection of a software component and generation of a conditional memory dump, a computing device executing an introspection program with respect to the software component is provided. An introspection system comprises one or more conditions for generating the conditional memory dump based on operations of the software component. In one aspect, a computing device detects, through an introspection program, whether the one or more conditions are satisfied by the software component based on information in an introspection analyzer of the introspection program. In addition, the computing device indicates, through the introspection program, if the one or more conditions are satisfied by the software component. In another aspect, responsive to the indication, the computing device generates the conditional memory dump through the introspection program.

Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.

A double data rate memory physical interface having self checking loopback logic on-chip is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of generating a set of test data values that comprise at least two data bits. Also disposed on the chip is a second linear feedback shift register. The second linear feedback shift register is capable of generating a set of expected data values that match the test data values. Further, an internal loopback error check element is disposed on the chip. The internal loopback error check element is used to compare the set of expected data values with the set of test data values.

An apparatus is equipped with a storage device including an error correction circuit. The apparatus performs a test of the storage device according to a predetermined testing procedure, and records a time-point at which error correction of the storage device has been performed by the error correction circuit during performance of the test. The apparatus determines, with predetermined accuracy, a first position within the storage device on which the error correction has been performed, based on a test speed at which the test is performed, a time-period from the time-point to current time, and a second position within the storage device on which the test is being performed at the current time. Then, the apparatus performs the test predetermined times on a range included in the storage device and including the first position, according to a testing procedure that has been used at the time-point.

Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory.

A method of operating a memory controller to control a memory device includes reading a read vector from the memory device and correcting one or more errors in the read vector, where a power consumed at the correcting is varied according to the number of errors in the read vector.

A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory that includes a three-dimensional (3D) memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event.

A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.

Example embodiments relate to a bad area managing method of a nonvolatile memory device. The nonvolatile memory device may include a plurality of memory blocks and each block may contain memory layers stacked on a substrate. According to example embodiments, a method includes accessing one of the memory blocks, judging whether the accessed memory block includes at least one memory layer containing a bad memory cell. If a bad memory cell is detected, the method may further include configuring the memory device to treat the at least one memory layer of the accessed memory block as a bad area.

The present invention intends to provide a method for removing radioactive cesium, or radioactive iodine and radioactive cesium that is simple and low-cost, further does not require an energy source such as electricity, moreover can take in and stably immobilize the removed radioactive substances within a solid, and can reduce the volume of radioactive waste as necessary, and to provide a hydrophilic resin composition using for the method for removing radioactive cesium, or radioactive iodine and radioactive cesium, and the object of the present invention is achieved by using a hydrophilic resin composition containing: at least one hydrophilic resin selected from the group consisting of a hydrophilic polyurethane resin, a hydrophilic polyurea resin, and a hydrophilic polyurethane-polyurea resin each having at least a hydrophilic segment; and a zeolite dispersed therein in a ratio of at least 1 to 200 mass parts relative to 100 mass parts of the hydrophilic resin.

A method and apparatus for the stabilization and safe removal of buried waste that is tested and classified as being transuranic or not transuranic waste and disposed accordingly. The buried waste (usually in vertical pipe units) is enclosed in a casing and ground and mixed with the surrounding soil. This process allows for chemical reactions to occur that stabilizes the mixture. The entire process is contained within the casing to avoid contamination. In situ or external testing is done for radio isotopes to classify the waste. If it is classified as transuranic the waste is removed in a controlled way into a retrieval enclosure and disposed off in drums. If the waste is not transuranic then grout is introduced into the mixture, allowed to set and the resulting monolith is removed and buried in trenches.

Methods of capturing and immobilizing radioactive nuclei with metal fluorite-based inorganic materials are described. For example, a method of capturing and immobilizing radioactive nuclei includes flowing a gas stream through an exhaust apparatus. The exhaust apparatus includes a metal fluorite-based inorganic material. The gas stream includes a radioactive species. The radioactive species is removed from the gas stream by adsorbing the radioactive species to the metal fluorite-based inorganic material of the exhaust apparatus.

A treatment system and a method for removal of at least one halogenated compound, such as PCBs, found in contaminated systems are provided. The treatment system includes a polymer blanket for receiving at least one non-polar solvent. The halogenated compound permeates into or through a wall of the polymer blanket where it is solubilized with at least one non-polar solvent received by said polymer blanket forming a halogenated solvent mixture. This treatment system and method provides for the in situ removal of halogenated compounds from the contaminated system. In one embodiment, the halogenated solvent mixture is subjected to subsequent processes which destroy and/or degrade the halogenated compound.

Degradation of phosphate esters, particularly neurotoxins and pesticides, is performed using high oxidative state molybdenum complexes, more particularly molybdenum(VI) complexes. A molybdenum(VI) complex is dissolved in water and then reacted with a phosphate ester. The phosphate esters can include, but are not limited to, VX, VE, VG, VM, GB, GD, GA, GF, parathion, paraoxon, triazophos, oxydemeton-methyl, chlorpyrifos, fenitrothion and pirimiphos-methyl, representing both chemical warfare agents as well as pesticides and insecticides.

A data collection unit obtains physiological data from a subject interface on a subject. The subject interface can be connected to the data collection unit. When the subject interface is connected to the data collection unit, subject interface contacts on the subject interface make contact with data collection unit contacts on the data collection unit. Some of the data collection unit contacts are for communicating physiological data from the subject interface to the data collection unit. Some of the contacts are for powering the data collection unit upon the subject interface being connected to the data collection unit and for powering down the data collection unit upon the subject interface being disconnected from the data collection unit.

An independently functioning or centrally controlled wall light switch is configured to operate in normal mode and a Jewish holiday mode wherein the state of the light is fixed, regardless of the user's physical manipulation of the light switch. The control system automatically activates holiday mode by combining a geographically determined Jewish religious clock executed by software and hardware that utilizes the current time, date and geographical location of the apparatus in accordance with the Jewish definition of time and laws for calculating numerous religiously significant shifting daily points in time. The control system further incorporates several energy saving and preference modes by utilizing a particular day's calculated religious points in time in conjunction with holiday behavior patterns common to most Jewish families to provide the user with a greatly simplified means of programming an automatically adjusting on/off light timer and dimming overlay functionality during holiday mode.

Memory system operations are extended for a data processor by DMA, cache, or memory controller to include a DMA descriptor, including a set of operations and parameters for the operations, which provides for data compression and decompression during or in conjunction with processes for moving data between memory elements of the memory system. The set of operations can be configured to use the parameters and perform the operations of the DMA, cache, or memory controller. The DMA, cache, or memory controller can support moves between memory having a first access latency, such as memory integrated on the same chip as a processor core, and memory having a second access latency that is longer than the first access latency, such as memory on a different integrated circuit than the processor core.

A method includes receiving a dividend and a divisor for performing a division operation. Numbers p and n are found, for which the divisor equals 2n(1+2p). An interim result, which is equal to a reciprocal of 1+2p multiplied by the dividend, is calculated. The interim result is divided by 2n to produce a result of the division operation.

The disclosure is related systems and methods for using operation durations of a data storage medium to generate random numbers. In one embodiment, a device may comprise a random number generator circuit configured to store a value representing a duration of an operation on the data storage medium, and generate a random number based on the value. Another embodiment may be a method comprising recording durations of access operations to a data storage medium, and generating a random number based on the durations.

A system (200) and a method (100) of operating a computing device to perform memoization are disclosed. The method includes determining whether a result of a function is stored in a cache and, if so, retrieving the result from the cache and, if not, calculating the result and storing it in the cache. The method (100) includes transforming (104) by the computing device at least one selected from the input parameters and the output parameters of the function, the transforming being based on an analysis of the function and its input arguments to establish whether or not there is a possible relationship reflecting redundancy among the input parameters and output parameters of the function. The transforming may include at least one of: use of symmetry, scaling, linear shift, interchanging of variables, inversion, polynomial and/or trigonometric transformations, spectral or logical transformations, fuzzy transformations, and systematic arrangement of parameters.

Devices, systems, methods, and other embodiments associated with generating a moving average are described. In one embodiment, a method includes inputting a new data value, wherein the new data value is a most recent data value in a series of M prior sequential data values that are input to an accumulator for the purpose of calculating a moving average having a window size of M. The method also includes detecting an error in the new data value and correcting the moving average, based at least in part, on the error.

A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal.

A variety of biomedical devices are provided which include thiol-ene or thiol-yne shape memory polymers. The biomedical devices of the invention are capable of exhibiting shape memory behavior at physiological temperatures and may be used in surgical procedures. Methods of making the devices of the invention are also provided.

The present invention relates to methods for making oxidation resistant homogenized polymeric materials and medical implants that comprise polymeric materials, for example, ultra-high molecular weight polyethylene (UHMWPE). The invention also provides methods of making antioxidant-doped medical implants, for example, doping of medical devices containing cross-linked UHMWPE with vitamin E by diffusion and annealing the anti-oxidant doped UHMWPE in a super critical fluid, and materials used therein.

A process for the preparation of modified polymers by a photo-initiated polymerization includes preparing a polymerization medium comprising at least one photoinitiator comprising at least one phosphorous oxide (P═O) group or at least one phosphorous sulfide (P═S) group, and at least one polymerizable monomer. The at least one polymerizable monomer is polymerized by irradiating the polymerization medium with electromagnetic radiation so as to induce a generation of radicals so as to obtain a polymer. The polymer is modified by irradiating the polymer with electromagnetic radiation so as to induce a generation of radicals from the polymer in a presence of at least one modifying agent.

A UV curable silicone rubber composition is provided. The composition does not undergo curing failure, foaming, and other undesirable conditions even if a water-containing inorganic filler such as zeolite were added. A UV curable silicone rubber composition comprising (A) 100 parts by weight of an organopolysiloxane having at least 2 alkenyl groups per molecule represented by the average compositional formula (I): R1aSiO(4-a)/2 (I) (wherein R1 is independently a substituted or unsubstituted monovalent hydrocarbon group, and a is a positive number of 1.95 to 2.05); (B) 1 to 300 parts by weight of an inorganic filler having a water content of at least 0.5% by weight; (C) 0.1 to 50 parts by weight of an organohydrogenpolysiloxane having at least 2 silicon-bonded hydrogen atoms per molecule; and (D) a catalytic amount of a photoactive platinum complex curing catalyst.

The present invention aims to provide a surface modification method for a rubber vulcanizate or a thermoplastic elastomer, which can impart excellent sliding properties and excellent durability against repeated sliding motion and can allow the surface to maintain the sealing properties, without using expensive self-lubricating plastics. The present invention relates to a surface modification method for modifying a rubber vulcanizate or a thermoplastic elastomer as an object to be modified, the method including: step 1 of forming polymerization initiation points on the object to be modified; step 2 of radically polymerizing a monomer, starting from the polymerization initiation points, by irradiation with LED light at 300 nm to 400 nm to grow polymer chains on a surface of the object to be modified; and step 3 of esterifying, transesterifying or amidating side chains of the polymer chains.

In one exemplary embodiment, a computer-implemented method includes receiving, at a remote direct memory access (RDMA) device, a plurality of RDMA requests referencing a plurality of virtual pages. Data transfers are scheduled for the plurality of virtual pages, wherein the scheduling occurs at the RDMA device. The number of the virtual pages that are currently pinned is limited for the RDMA requests based on a predetermined pinned page limit.

A dispersed storage network memory includes a pool of storage nodes, where the pool of storage nodes stores a multitude of encoded data files. A storage node obtains and analyzes data access response performance data for each of the storage nodes to produce a modified data access response plan that includes identity of an undesired performing storage node and an alternative data access response for the undesired performing storage node. The storage nodes receive corresponding portions of a data access request for at least a portion of one of the multitude of encoded data files. The undesired performing storage node or another storage node processes one of the corresponding portions of the data access request in accordance with the alternative data access response.

Machines, systems and methods for I/O monitoring in a plurality of compute nodes and a plurality of service nodes utilizing a Peripheral Component Interconnect express (PCIe) are provided. In one embodiment, the method comprises assigning at least one virtual function to a services node and a plurality of compute nodes by the PCIe interconnect and a multi-root I/O virtualization (MR-IOV) adapter. The MR-IOV adapter enables bridging of a plurality of compute node virtual functions with corresponding services node virtual functions. A front-end driver on the compute node requests the services node virtual function to send data and the data is transferred to the services node virtual function by the MR-IOV adapter. A back-end driver running in the services node receives and passes the data to a software service to modify/monitor the data. The back-end driver sends the data to another virtual function or an external entity.

A semiconductor memory device includes a selection signal generation unit configured to generate a plurality of selection signals that are sequentially activated, a path selection unit configured to select a transmission path of sequentially input information data in response to the plurality of selection signals, a plurality of first storage units, each configured to have a first storage completion time and store an output signal of the path selection unit, and a plurality of second storage units, each configured to have a second storage completion time, which is longer than the first storage completion time, and store a respective output signal of the plurality of first storage units.

A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.

A method, apparatus, and system for switching from an existing target end device to a next target end device in a multi-expander storage topology by using Fast Context Switching. The method enhances Fast Context Switching by allowing Fast Context Switching to reuse or extend part of an existing connection path to an end device directly attached to a remote expander. The method can include reusing or extending at least a partial path of an established connection between an initiator and the existing target end device for a connection between the initiator and the next target end device, whereby the existing target end device and the next target end device are locally attached to different expanders.

A system, method and computer-readable media for managing a compute environment are disclosed. The method includes importing identity information from an identity manager into a module performs workload management and scheduling for a compute environment and, unless a conflict exists, modifying the behavior of the workload management and scheduling module to incorporate the imported identity information such that access to and use of the compute environment occurs according to the imported identity information. The compute environment may be a cluster or a grid wherein multiple compute environments communicate with multiple identity managers.

A method for efficient dispatch/completion of a work element within a multi-node data processing system. The method comprises: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ.

A system and method for detecting, filtering, prioritizing and reporting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises initialization information for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a potential conflict by identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. First information associated with a first access and second information associated with the second access to the location is determined. Filter criteria is applied to the first and second information to determine whether the instruction causes a reportable hazard. The instruction is reported when it causes the reportable hazard.

Embodiments of the invention are directed to a system, method, or computer program product for providing an information technology build service for building a platform in response to a service request. The invention receives a service request for the platform build from a requester, receives a plurality of platform parameters from the requester, determines whether the service request requires one or more physical machines or one or more virtual machines, and if the service request requires one or more virtual machines, initiates build of the one or more virtual machines. The invention also provisions physical and virtual storage based on received parameters, provisions physical and virtual processing power based on received parameters, and manages power of resources during the build, the managing comprising managing power ups, power downs, standbys, idles and reboots of one or more physical components being used for the build.

A system for protecting an electronic device against malware includes a memory, an operating system configured to execute on the electronic device, and a below-operating-system security agent. The below-operating-system security agent is configured to trap an attempted access of a resource of the electronic device, access one or more security rules to determine whether the attempted access is indicative of malware, and operate at a level below all of the operating systems of the electronic device accessing the memory. The attempted access includes attempting to write instructions to the memory and attempting to execute the instructions.

The systems and methods described herein may be used to implement a shared dynamic-sized data structure using hardware transactional memory to simplify and/or improve memory management of the data structure. An application (or thread thereof) may indicate (or register) the intended use of an element of the data structure and may initialize the value of the data structure element. Thereafter, another thread or application may use hardware transactions to access the data structure element while confirming that the data structure element is still part of the dynamic data structure and/or that memory allocated to the data structure element has not been freed. Various indicators may be used determine whether memory allocated to the element can be freed.

Methods and systems for managing a removal of a passthrough device from a guest managed by a hypervisor in virtualized computing environment. A hypervisor receives a request from the guest for access to a passthrough device. The hypervisor sets, in a memory, a last accessed state associated with a virtual machine executing the guest. The hypervisor forwards the request to the passthrough device and configures the host CPU to send a subsequent access request directly to the passthrough device. In response to a virtual machine reset, the hypervisor clears the last accessed state and instructs the host CPU to send a post-reset access request to the hypervisor.

An optically active bisbenzyl compound or a racemic bisbenzyl compound represented by formula (2) that has axial chirality: where: R1 represents a halogen, or an optionally substituted: linear, branched, or cyclic C1-8 alkyl, C2-8 alkenyl, C2-8 alkynyl, C6-14 aryl, C3-8 heteroaryl, linear, branched, or cyclic C1-8 alkoxy, or C7-16 aralkyl;R21 each independently represents hydrogen, halogen, nitro, or an optionally substituted: linear, branched, or cyclic C1-8 alkyl, C2-8 alkenyl, C2-8 alkynyl, C6-14 aryl, linear, branched, or cyclic C1-8 alkoxy, or a C7-16 aralkyl;R3 represents hydrogen, or an optionally substituted: C6-14 aryl, a C3-8 heteroaryl, or a C7-16 aralkyl; andY2 represents a halogen, or an optionally substituted: C1-8 alkylsulfonyloxy, C6-14 arylsulfonyloxy, or C7-16 aralkylsulfonyloxy.

Disclosed and claimed herein are hybrid silica aerogels containing non-polymeric, functional organic materials covalently bonded at one or both ends to the silica network of the aerogels through a C—Si bond between a carbon atom of the organic material and a silicon atom of the aerogel network. Methods of their preparation are also disclosed.

The invention is drawn to fluid concentrate formulations of fatty acid monoethanolamides comprising (a) about 71-76% by weight of one or more C8-C22 fatty acid monoethanolamides, (b) about 15-17% by weight of water, and (c) about 10-12% by weight of one or more hydrotropes, based on the fluid formulation, wherein the fluid formulation is homogeneous, pumpable and color stable at a temperature of less than 55° C. A preferred embodiment is drawn to fluid concentrate formulations of cocamide monoethanolamide (CMEA) consisting of (a) about 71-76% by weight of CMEA, (b) about 15-17% by weight of water, and (c) about 10-12% by weight of glycerol, based on the fluid formulation. Methods of preparing the fluid concentrate formulations mulations are also disclosed. The fluid concentrate formulations of fatty acid monoethanolamides are useful in the preparation of cosmetic and pharmaceutical compositions.

A process for preparing bi-modal water emulsions is disclosed comprising: I) forming a mixture comprising; A) 100 parts by weight of a hydrophobic oil, B) 1 to 1000 part by weight of a water continuous emulsion having at least one surfactant, II) admixing additional quantities of the water continuous emulsion and/or water to the mixture from step I) to form a bi-modal emulsion.

Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.

A method of extending advanced process control (APC) models includes constructing an APC model table including APC model parameters of a plurality of products and a plurality of work stations. The APC model table includes empty cells and cells filled with existing APC model parameters. Average APC model parameters of the existing APC model parameters are calculated, and filled into the empty cells as initial values. An iterative calculation is performed to update the empty cells with updated values.

A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.