Polysubstituted cyclopentadiene compound wherein at least two different substituents are present from the group consisting of linear, branched and cyclic alkyls, aralkyls and alkenyls, and a process for the preparation of a cyclopentadiene compound substituted with at least two different groups chosen from the group consisting of linear, branched, cyclic and aromatic alkyls and alkenyls, characterized in that it comprises the reacting of a halide of a first substituting group in a mixture of the cyclopentadiene compound and an aqueous solution of a base, in which the quantity of the base relative to the cyclopentadiene compound is between 5 and 30 mol/mol, in the presence of a phase transfer catalyst, followed by the addition of a halide of a second or optionally a third substituting group to the reaction mixture.

Embodiments are directed to glass frits containing phosphors that can be used in LED lighting devices and for methods associated therewith for making the phosphor containing glass frit and their use in glass articles, for example, LED devices.

Provided is an oxide sintered body suitably used for the production of an oxide semiconductor film for a display device, wherein the oxide sintered body has both high conductivity and relative density, and is capable of depositing an oxide semiconductor film having high carrier mobility. This oxide sintered body is obtained by mixing and sintering powders of zinc oxide, tin oxide and indium oxide, and when an EPMA in-plane compositional mapping is performed on the oxide sintered body the percentage of the area in which Sn concentration is 10 to 50 mass % in the measurement area is 70 area percent or more.

Provided are an oxide sintered body and a sputtering target that are ideal for the production of an oxide semiconductor film for a display device. The oxide sintered body and sputtering target that are provided have both high conductivity and high relative density, are capable of forming an oxide semiconductor film having a high carrier mobility, and in particular, have excellent direct-current discharge stability in that long-term, stable discharge is possible, even when used by the direct-current sputtering method. The oxide sintered body of the invention is an oxide sintered body obtained by mixing and sintering zinc oxide, tin oxide, and an oxide of at least one metal (M metal) selected from the group consisting of Al, Hf, Ni, Si, Ga, In, and Ta. When the in-plane specific resistance and the specific resistance in the direction of depth are approximated by Gaussian distribution, the distribution coefficient σ of the specific resistance is 0.02 or less.

A process for oligomerizing isobutene comprises contacting a feedstock comprising isobutene with a catalyst comprising a MCM-22 family molecular sieve under conditions effective to oligomerize the isobutene, wherein said conditions including a temperature from about 45° C. to less than 140° C. The isobutene may be a component of a hydrocarbon feedstock containing at least one additional C4 alkene. In certain aspects, isobutene oligomers are separated from a first effluent of the oligomerization to produce a second effluent comprising at least one n-butene. The second effluent can be contacted with an alkylation catalyst to produce sec-butylbenzene.

A process for the double-bond isomerization of olefins is disclosed. The process may include contacting a fluid stream comprising olefins with a fixed bed comprising an activated basic metal oxide isomerization catalyst to convert at least a portion of the olefin to its isomer. The isomerization catalysts disclosed herein may have a reduced cycle to cycle deactivation as compared to conventional catalysts, thus maintaining higher activity over the complete catalyst life cycle.

There may be provided a process for producing a polyimide siloxane solution composition having a further improved long-term viscosity stability; and a polyimide siloxane solution composition. In the process for producing the polyimide siloxane solution composition by polymerizing/imidizing a tetracarboxylic acid component and a diamine component consisting of (a) a diaminopolysiloxane, (b) a diamine having a polar group and (c) a diamine other than (a) and (b) in a solvent, the tetracarboxylic acid component and the diamine component excluding (b) the diamine having a polar group are polymerized/imidized to provide a reaction mixture solution, and then (b) the diamine having a polar group is added to the reaction mixture solution last, and the mixture is polymerized/imidized.

The invention relates to a method of neutralizing paints, that includes adding at least one associative neutralizing agent to a formulation such as a pigment concentrate, a white paint base or paint. The associative neutralizing agent includes at least one neutralizing group N and at least one nitrogenous associative group A bonded together by at least one “spacer” group Sp. The invention also relates to pigment concentrates and to paints containing at least one such associative neutralizing agent.

Bis-Phenol A (BPA) can now be replaced in industrial processes by BPA substitutes. The BPA substitutes can have structures that are derivatives of BPA. The BPA substitutes can be used in preparing epoxy composition, polycarbonate compositions, and polysulfonate compositions or for other uses in place of BPA.

A method for preparing poly(butylene terephthalate-co-adipate) copolymer by polymerizing 1,4-butane diol, an adipic acid component and an aromatic dicarboxy compound derived from polyethylene terephthalate, and a polyester component residue in the presence of a catalyst under conditions effective to form poly(butylene terephthalate-co-adipate) oligomers; adding a quencher; and reacting the quenched poly(butylene terephthalate-co-adipate) oligomers with a chain extender.

Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from multiple blocks and buffered in a buffer. The buffer's output is operatively coupled to one or more high-speed serial I/O interfaces via muxing logic during debug test operations. The buffered data is encoded as serialized data and sent over the one or more high-speed serial I/O interfaces to a logic device that receives serialized data and de-serializes it to generate parallel debug data that is provided to a debugger. The buffer may be configured as a bandwidth-adapting buffer that facilitates transfer of debug data that is received at a variable combined data rate outbound via the one or more high-speed serial I/O interfaces at a data rate corresponding to the bandwidth of the serial I/O interfaces.

A system, method and computer program product for avoiding a processing flaw in a computer processor triggered by a predetermined sequence of hardware events. The system may include a detecting unit and a power-on reset unit. The detecting unit detects that the predetermined sequence of hardware events is going to occur at the computer processor. The power-on reset unit initializes the computer processor to a state stored in computer memory in response to detecting the sequence of hardware events.

A method to prevent failure on a server computer due to internally and/or externally induced shock and/or vibration. The method includes acquiring, by at least one sensor, analog acceleration data of components in a server computer. The data is then converted to digital format and stored within a motor drive assembly processor memory unit. The processor analyzes the stored data for existence of machine degradation. In response to detecting the existence of machine degradation, the motor drive assembly processor initiates remediation procedures. The remediation procedures include controlling rotating speed of moving devices or performing a complete system shut down.

Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts; the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices; and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.

A method for decoding and checking a tail-biting convolutional code is provided. The method fully utilizes structural features of the tail-biting convolutional code to re-sort Log-Likelihood Ratio (LLR) values input into a decoder, and by reconstructing a derivative generator polynomial of a convolutional code, allows the decoder to output in serial according to a normal ordering of information bits during backtracking, that is, a first bit of an information sequence is first decoded successfully. Thus, CRC checking may be activated as soon as possible, so that part of the backtracking process and the CRC checking may be performed in parallel, thereby achieving the objective of reducing a processing time delay in decoding and checking the tail-biting convolutional code.

It is provided a computer comprising a nonvolatile memory for storing data, a control processor for controlling the saving of data into the nonvolatile memory, and a battery for supplying power to the computer in case of a failure of an external power supply, wherein the control processor checks a charge amount stored in the battery, calculates an amount of data which can be saved in the nonvolatile memory by the battery in case of a failure of the external power supply based on the checked charge amount, and saves data excluding the amount of data that can be saved, out of data which should be saved into the nonvolatile memory, into the nonvolatile memory in advance.

The present application is directed to a novel composition which acts as a barrier to noxious agents while adding self-detoxifying catalytic treatments to neutralize the noxious and harmful warfare agents when applied for example on a fabric, or other solid support.

The present invention relates to a method for the degradation of pollutants in water and/or soil. More specific, the present invention relates to a method for the on-site decontamination or re-mediation of water and/or soil which are contaminated with organic compounds. Moreover, the invention relates to a method for forming a barrier against the spreading of a contamination with pollutants within the water and/or soil, especially within groundwater (aquifer). Further, the invention relates to means for use in these methods, and to the production of such means.

An environmentally beneficial process for utilizing waste drill cuttings from oil and gas exploration. The waste drill cuttings (20) are used as a filler and combined with plastic to provide a plastic based product (26) in the plastics industry. In an embodiment the cuttings are thermally treated and formed into pellets. In a further embodiment the cuttings are treated and mixed with recycled plastic to be formed into pellets. The pellets are then used in the manufacture of rigid plastic products such as bollards, planters, benches and decking.

An exemplary system for treatment and disposal of pharmaceutical waste comprises a sealable pail, a stirring device, a sealable bag, a container, an acidic substance, and a denaturant. The sealable pail receives the pharmaceutical waste and the acidic substance. The acidic substance dissolves the pharmaceutical waste, and the stirring device stirs the acidic substance to ensure that the pharmaceutical waste is completely dissolved. The denaturant is added to the dissolved pharmaceutical waste and renders the dissolved pharmaceutical waste safe for transport. The treated pharmaceutical waste is sealed within the sealable pail, and the sealable bag receives the sealed pail and is sealed. The sealed bag is then placed in the container for transport to a disposal facility.

Containers and methods for disposing unused pharmaceutical product are disclosed. Each container (100, 200, 300) may include a container body (104, 204, 304) with an internal chamber (116, 216, 316) for storing pharmaceutical product, along with a cover (124, 224, 324) for selectively limiting access to the chamber (116, 216, 316). An encapsulation component (128, 228, 328) may be selectively disposable within the chamber (116, 216, 316), and may be operable to encapsulate the pharmaceutical product within the container (100, 200, 300). For instance, the encapsulation component (128, 228, 328) may melt and/or flow into contact with the pharmaceutical product and thereafter solidify to encapsulate the pharmaceutical product. The encapsulation component (128, 228, 328) may melt and thereafter solidify between the cover (124, 224, 324) and shell (104, 204, 304) to limit removal of the cover (124, 224, 324) from the shell (104, 204, 304).

A treatment process of persistent organic pollutants contained in particles is provided. Said process includes reacting persistent organic pollutant in particles under hydrothermal conditions in the presence of Fe2+ and Fe3+. Several beneficial effects can be achieved, including 1) no other additive is needed during the reaction process; 2) Fe2+ and Fe3+ are safe, cheap and extensive sources; 3) because Fe2+ and Fe3+ are dissolved, they can fully disperse into particles, and fully contact can be achieved, thus obtaining a decomposition rate no less than 70% of the persistent organic pollutants is under subcritical conditions.

A method and apparatus for distributing objects. In one embodiment, the method comprises computing a modulus operand based on a number of objects to be distributed and a number of objects pertaining to a first category; computing a modulus operation based on a number of distributed objects and the modulus operand; and distributing a first object or a second object based on a result of computing the modulus operation.

Apparatus comprising an input connected to receive an input signal, a lookup table comprising a plurality of input entries and first and second output entries for each input entry. The look up table receives the input signal and returns a lower input entry, an upper input entry, the second output entry for the lower input entry, and the first output entry for the upper input entry. A first subtractor subtracts the lower input entry from the input signal to produce a first difference. A second subtractor subtracts the input signal from the upper input entry to produce a second difference. First and second multipliers multiply the first and second differences by the first output entry for the upper input entry and the second output entry for the lower input entry, respectively, to produce first and second products. An adder adds the first and second products to produce an output signal.

A method for computer-implemented unit-conversion method, the method comprising identifying a first numerical value in a first system of units displayed on a computing device, converting the first numerical value in the first system of units into a second numerical value, and displaying the second numerical value and the second system of units on the computing device.

A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be selectively output to the execution unit for use as an operand during the execution of instructions by the execution unit. A PRNG may be coupled to an input of an operand multiplexer that outputs to an operand input of an execution unit so that operands provided by instructions supplied to the execution unit are selectively overridden with pseudorandom numbers generated by the PRNG. Furthermore, overridden operands provided by instructions supplied to the execution unit may be used as seed values for the PRNG.

Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Distributed processing system and method for discrete logarithm calculation. The speed and resource efficiency of discrete logarithm calculation may be improved by allowing a plurality of operation agents to distributively process an operation of generating a modulo multiplication auxiliary table, an operation of generating a pre-calculation table, and an operation of searching for an answer by applying an iterated function for discrete logarithm calculation in a discrete logarithm calculation operation using the pre-calculation table.

A system (200) and a method (100) of operating a computing device to perform memoization are disclosed. The method includes determining whether a result of a function is stored in a cache and, if so, retrieving the result from the cache and, if not, calculating the result and storing it in the cache. The method (100) includes transforming (104) by the computing device at least one selected from the input parameters and the output parameters of the function, the transforming being based on an analysis of the function and its input arguments to establish whether or not there is a possible relationship reflecting redundancy among the input parameters and output parameters of the function. The transforming may include at least one of: use of symmetry, scaling, linear shift, interchanging of variables, inversion, polynomial and/or trigonometric transformations, spectral or logical transformations, fuzzy transformations, and systematic arrangement of parameters.

A method includes configuring a processing circuit to perform: receiving a control word for an I/O operation, forwarding a transport command control block (TCCB) from the channel subsystem to a control unit, gathering data associated with the I/O operation, and transmitting the gathered data to the control unit in the I/O processing system. Gathering the data includes accessing entries of a list of storage addresses that collectively specifying the data. Based on an entry of the list comprising a not-set first flag and a corresponding first storage address, gathering data from a corresponding storage location, and based on an entry of the list comprising a set first flag and a corresponding second storage address, obtaining a next entry of the list from a second storage location.

In one exemplary embodiment, a computer-implemented method includes receiving, at a remote direct memory access (RDMA) device, a plurality of RDMA requests referencing a plurality of virtual pages. Data transfers are scheduled for the plurality of virtual pages, wherein the scheduling occurs at the RDMA device. The number of the virtual pages that are currently pinned is limited for the RDMA requests based on a predetermined pinned page limit.

Machines, systems and methods for I/O monitoring in a plurality of compute nodes and a plurality of service nodes utilizing a Peripheral Component Interconnect express (PCIe) are provided. In one embodiment, the method comprises assigning at least one virtual function to a services node and a plurality of compute nodes by the PCIe interconnect and a multi-root I/O virtualization (MR-IOV) adapter. The MR-IOV adapter enables bridging of a plurality of compute node virtual functions with corresponding services node virtual functions. A front-end driver on the compute node requests the services node virtual function to send data and the data is transferred to the services node virtual function by the MR-IOV adapter. A back-end driver running in the services node receives and passes the data to a software service to modify/monitor the data. The back-end driver sends the data to another virtual function or an external entity.

A portable or mobile computing device, such as a smart phone or portable media player, can be used to control one or more electronic devices over an appropriate wireless channel. In one example, a user can utilize a smart phone as a mouse for a notebook computer or Internet-capable television. The user can move the portable device on a surface and press appropriate selectable elements on the portable device, as if the user is using a wireless mouse. The portable device can send the commands over the wireless channel to the electronic device, which can provide inputs and/or control signals to the electronic device. In some embodiments, the user can take advantage of the processing capability of the portable device to work directly with elements such as a wireless keyboard and wireless monitor, without the need for a notebook or other such computing element therebetween.

Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

A system, method and computer-readable media for managing a compute environment are disclosed. The method includes importing identity information from an identity manager into a module performs workload management and scheduling for a compute environment and, unless a conflict exists, modifying the behavior of the workload management and scheduling module to incorporate the imported identity information such that access to and use of the compute environment occurs according to the imported identity information. The compute environment may be a cluster or a grid wherein multiple compute environments communicate with multiple identity managers.

A method for efficient dispatch/completion of a work element within a multi-node data processing system. The method comprises: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ.

In one embodiment, the invention provides a method of managing a computing job based on a job priority and a submitter quota.

A cloud system may create physical resource tags to store relationships between cloud computing offerings, such as computing service offerings, storage offerings, and network offerings, and the specific physical resources in the cloud computing environment. Cloud computing offerings may be presented to cloud customers, the offerings corresponding to various combinations of computing services, storage, networking, and other hardware or software resources. After a customer selects one or more cloud computing offerings, a cloud resource manager or other component within the cloud infrastructure may retrieve a set of tags and determine a set of physical hardware resources associated with the selected offerings. The physical hardware resources associated with the selected offerings may be subsequently used to provision and create the new virtual machine and its operating environment.

Systems, methods and computer program products may provide managing utilization of one or more physical processors in a shared processor pool. A method of managing utilization of one or more physical processors in a shared processor pool may include determining a current amount of utilization of the one or more physical processors and generating an instruction message. The instruction message may be at least partially determined by the current amount of utilization. The method may further include sending the instruction message to a guest operating system, the guest operating system having a number of enabled virtual processors.

In mainframe computer system, workload tasks are accomplished using a logically partitioned data processing system, where the partitioned data processing system is divided into multiple logical partitions. In a system and method managing such a computer system, each running workload tasks that can be classified based on time criticality, and groups of logical partitions can be freely defined. Processing capacity limits for the logical partitions in a group of logical partitions based upon defined processing capacity thresholds and upon an iterative determination of how much capacity is needed for time critical workload tasks. Workload can be balanced between logical partitions within a group, to prevent surplus processing capacity being used to run not time critical workload on one logical partition when another logical partition running only time critical workload tasks faces processing deficit.

A system and method for reconfiguring a computing environment comprising a consumption analysis server, a placement server, an infrastructure management client and a data warehouse in communication with a set of data collection agents and a database. The consumption analysis server operates on measured resource utilization data to yield a set of resource consumptions in regularized time blocks, collects host and virtual machine configurations from the computing environment and determines available capacity for a set of target hosts. The placement server assigns a set of target virtual machines to the target set of hosts in a new placement. In one mode of operation the new placement is nearly optimal. In another mode of operation, the new placement is “good enough” to achieve a threshold score based on an objective function of resource capacity headroom. The new placement is implemented in the computing environment.

By employing a two-tier load balancing scheme, embodiments of the present invention may reduce the overhead of shared resource management, while increasing the potential aggregate throughput of a thread pool. As a result, the techniques presented herein may lead to increased performance in many computing environments, such as graphics intensive gaming.

There is provided a parallel computer system for performing barrier synchronization using a master node and a plurality of worker nodes based on the time to allow for an adaptive setting of the synchronization time. When a task process in a certain worker node has not been completed by a worker determination time, the particular worker node performs a communication to indicate that the process has not been completed, to a master node. When the communication has been received by a master determination time, the master node performs a communication to indicate that the process time is extended by a correction process time, in order to adjust and extend the synchronization time. In this way, it is possible to reduce the synchronization overhead associated with the execution of an application with a relatively large variation in the process time from a synchronization point to the next synchronization point.

A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

Aqueous emulsions of epoxy- and organo-substituted, branched organopolysiloxanes are prepared by emulsifying the latter in water with the aid of a dispersing agent. The emulsions are storage stable and are useful in multi-component coating, adhesive, and binder systems.

Antibacterial sol-gel coating solutions are used to form articles. The antibacterial sol-gel coating solution includes at least one Ti or Si-containing compound that is capable of hydrolyzing to form a base film; a regulating agent capable of regulating the hydrolysis rate of the Ti or Si-containing compounds, an organic solvent, water, and at least one soluble compound of an antibacterial metal, such as Ag, Cu, Mg, Zn, Sn, Fe, Co, Ni, or Ce.

A computing section is provided with a plurality of computing units and correlatively stores entries of configuration information that describes configurations of the plurality of computing units with physical configuration numbers that represent the entries of configuration information and executes a computation in a configuration corresponding to a designated physical configuration number. A status management section designates a physical configuration number corresponding to a status to which the computing section needs to advance the next time for the computing section and outputs the status to which the computing section needs to advance the next time as a logical status number that uniquely identifies the status to which the computing section needs to advance the next time in an object code. A determination section determines whether or not the computing section has stored an entry of configuration information corresponding to the status to which the computing section needs to advance the next time based on the logical status number that is output from the status management section. A rewriting section correlatively stores the entry of the configuration information and a physical configuration number corresponding to the entry of the configuration information in the computing section when the determination section determines that the computing section has not stored the entry of configuration information corresponding to the status to which the computing section needs to advance the next time.

Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.