A method of reducing the downward flow of air currents on the leeward side of an emissions emitting structure including the step of using a system that includes components chosen from the group consisting of one or more mechanical air moving devices; physical structures; and combinations thereof to create an increase in the air pressure within a volume of air on the leeward side of an emissions emitting structure having emissions that become airborne. The increased air pressure prevents or lessens downward flow of emissions that would occur without the use of the system and increases the safety by which one can travel a road or other transportation route that might otherwise be visually obscured by the emissions and the safety of the property and those within the area where emissions occur.

A computing section is provided with a plurality of computing units and correlatively stores entries of configuration information that describes configurations of the plurality of computing units with physical configuration numbers that represent the entries of configuration information and executes a computation in a configuration corresponding to a designated physical configuration number. A status management section designates a physical configuration number corresponding to a status to which the computing section needs to advance the next time for the computing section and outputs the status to which the computing section needs to advance the next time as a logical status number that uniquely identifies the status to which the computing section needs to advance the next time in an object code. A determination section determines whether or not the computing section has stored an entry of configuration information corresponding to the status to which the computing section needs to advance the next time based on the logical status number that is output from the status management section. A rewriting section correlatively stores the entry of the configuration information and a physical configuration number corresponding to the entry of the configuration information in the computing section when the determination section determines that the computing section has not stored the entry of configuration information corresponding to the status to which the computing section needs to advance the next time.

A computing machine is disclosed having a memory system for storing a collection of execution nodes, a head for reading a sequence of symbols in the execution nodes in the memory system, and writing a sequence of symbols in the memory system. The machine is configured to execute a computation with a collection of pairs of execution nodes. Each pair of execution nodes represents a machine instruction. One execution node in the pair represents input of the machine instruction represented by the execution nodes. Another execution node in the pair represents output of the machine instruction represented by the execution nodes. Each execution node has a state of the machine, a sequence of symbols and a number.

A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.

A hypervisor and one or more guest operating systems resident in a data processing system and hosted by the hypervisor are configured to selectively enable or disable branch prediction logic through separate hypervisor-mode and guest-mode instructions. By doing so, different branch prediction strategies may be employed for different operating systems and user applications hosted thereby to provide finer grained optimization of the branch prediction logic for different operating scenarios.

In a multiprocessor system, in general, a processor assigned with a larger amount of tasks is apt to perform a larger amount of communication with other processors assigned with tasks, than a processor assigned with a smaller amount of tasks. Thus in order for each processor to be able to perform the routing process efficiently, tasks are assigned such that, when there are a first processor and a second processor, the number of processors each assigned with one or more tasks and directly connected with the second processor being smaller than the number of processors each assigned with one or more tasks and directly connected with the first processor, the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor.

A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.

Graphical programming or modeling environments in which a coding standard can be applied to graphical programs or models are disclosed. The present invention provides mechanisms for applying the coding standard to graphical programs/models in the graphical programming/modeling environments. The mechanisms may detect violations of the coding standard in the graphical model and report such violations to the users. The mechanisms may automatically correct the graphical model to remove the violations from the graphical model. The mechanisms may also automatically avoid the violations in the simulation and/or code generation of the graphical model.

Methods, devices, and systems for management of a cloud computing environment for use by a software application. The cloud computing environment may be an N-tier environment. Multiple cloud providers may be used to provide the cloud computing environment.

A single software project in an integrated development environment (IDE) may be built for multiple target environments in a single build episode. Multiple different output artifacts may be generated by the build process for each of the target environments. The output artifacts are then deployed to the target environments, which may be homogeneous or heterogeneous environments. The same source project may be used to generate multiple output artifacts for the same target environment.

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

A system for blueprint-driven environment template creation in a virtual infrastructure comprises a processor and a memory. The processor is configured to receive a blueprint, receive an environment template configuration, and build an environment template using the blueprint and the environment template configuration. The environment template is for provisioning an environment. The environment is for deploying an application. The memory is coupled to the processor and is configured to provide the processor with instructions.

A firmware update method and apparatus of a set-top box for a digital broadcast system is provided. A firmware update method of a set-top box for a digital broadcast system includes determining whether a newly received Code Version Table (CVT) following a public CVT which has been previously received and stored is the public CVT or a filtering CVT; and updating, when the newly received CVG is the filtering CVT, the firmware of the set-top box with a filtering firmware indicated by the filtering CVT.

The present invention relates to the field of perfumery and more particularly to the field of malodor counteractancy. In particular, it relates to a method for application of malodor counteracting (MOC) compositions capable of neutralizing in an efficient manner, through chemical reactions, malodors of a large variety of origins and which can be encountered in the air, on textiles, bathroom or kitchen surfaces, and the like. The composition may be applied as is or in the form of a perfuming composition or in a consumer product or article containing the compound or perfume composition.

A microcapsule comprising A) a core containing a hydrophobic liquid or wax, B) a polymeric shell comprising a) a polymer formed from a monomer mixture containing: i) 1 to 95% by weight of a hydrophobic mono functional ethylenically unsaturated monomer, ii) 5 to 99% by weight of a polyfunctional ethylenically unsaturated monomer, and iii) 0 to 60% by weight of other mono functional monomer, and b) a further hydrophobic polymer which is insoluble in the hydrophobic liquid or wax. The invention includes a process for the manufacture of particles and the use of particles in articles, such as fabrics, and coating compositions, especially for textiles.

The present invention relates to novel pyrimidine derivatives and their use in perfume compositions. The novel pyrimidine derivatives of the present invention are represented by the following formula: wherein m and n are integers of 0 or 1, with the proviso that when m is 0, n is 1 and when m is 1, n is 0; andwherein the dashed circle represents either single or double bonds.

A para-methoxy protected benzaldehyde useful in preparation of treprostinil, and of formula: (Formula (1)) is prepared by subjecting to Claisen re-arrangement a substituted benzaldehyde of formula (1a): (Formula (Ia)) to form the m-hydroxy-substituted benzaldehyde of formula (1b): (Formula (Ib)) and then reacting compound (1b) with a p-methoxybenzyl (PMB) compound to form a PMB-substituted benzaldehyde of formula (1).

A polyether polyol based on renewable materials is obtained by the in situ production of a polyether from a hydroxyl group-containing vegetable oil, at least one alkylene oxide and a low molecular weight polyol having at least 2 hydroxyl groups. The polyol is produced by introducing the hydroxyl group-containing vegetable oil, a catalyst and an alkylene oxide to a reactor and initiating the alkoxylation reaction. After the alkoxylation reaction has begun but before the reaction has been 20% completed, the low molecular weight polyol having at least 2 hydroxyl groups is continuously introduced into the reactor. After the in situ made polyether polyol product having the desired molecular weight has been formed, the in situ made polyether polyol is removed from the reactor. These polyether polyols are particularly suitable for the production of flexible polyurethane foams.

The invention relates to compressed data transmission in wireless data communication. Disclosed are methods and apparatuses for transporting residue of vehicle position data via a wireless network. A disclosed method for transporting residue of vehicle position data via a wireless network, includes the steps of: receiving data for updating residue encoding schema from a monitoring server; constructing a residue encoding schema based on the data, thereby producing a constructed residue encoding schema; and storing the constructed residue encoding schema such that the constructed residue encoding schema will become the current residue encoding schema; where: the constructed residue encoding schema is constructed such that each residue of the constructed residue encoding schema corresponds to a code; and the constructed residue encoding schema is constructed such that a residue having a relatively high probability of occurrence corresponds to a code of relatively short length.

Vehicle event recorder systems are arranged to be in constant communication with remote servers and administrators via mobile wireless cellular networks. Vehicle event recorders equipped with video cameras capture video and other data records of important events relating to vehicle use. These data are then transmitted over special communications networks having very high coverage space but limited bandwidth. A vehicle may be operated over very large region while maintaining continuous communications connections with a remote fixed server. As such, systems of these inventions may be characterized as including a mobile unit having: a video camera; a microprocessor; memory; an event trigger; and mobile wireless transceivers, and a fixed network portion including: mobile wireless cellular network, a protocol translation gateway, the Internet and an application-specific server.

A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.

This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.

Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times.

An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

A method of creating a datasheet includes obtaining integrated circuit data from at least one data source, creating a data structure including the integrated circuit data obtained from the at least one data source, and creating a datasheet using data contained in the data structure. The datasheet is created in a human-readable format.

A circuit-design support method includes obtaining information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output via the logic circuit; obtaining information concerning a control circuit that has a first flip-flop for scanning and that can control a value of a given signal line by a value set by the first flip-flop; selecting, based on the circuit information, a second flip-flop at an output destination of a signal from the logic circuit, among second flip-flops of the circuit; and generating, based on the control circuit information, information indicating a serial connection of the control circuit between an output source of the signal of the given signal line and the given signal line and a connection of a data input terminal of the first flip-flop and an output terminal of the selected second flip-flop.

A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.

A layout-legalizing system modifies a portion of a circuit layout that is selected by a user to generate a modified portion that satisfies a set of technology constraints and a set of design constraints. The system receives as input the set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes. The system also receives a set of design constraints from the user which restricts how objects in the portion of the circuit layout can be modified to satisfy the set of technology constraints. The system can further receive a selection input from the user which identifies the portion of the circuit layout which is to be legalized. The system then modifies the identified portion of the circuit layout to obtain a modified portion which satisfies the set of design constraints and at least a subset of the set of technology constraints.

Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.

A non-aqueous liquid cleaning composition for applicators used for applying non-aqueous hair removal compositions to the skin. The composition includes a solubilizing oil effective for solubilizing the non-aqueous hair removal composition, e.g., mineral oil, and an effective antibacterial amount of an antibacterial agent, e.g., triclosan. The composition may also include fragrances and additional bacteriocides, e.g., phenoxyethanol. When the applicator is contacted with the heated cleaning composition any hair removal composition and bacteria on the applicator are removed therefrom and the applicator is ready for reuse. It is preferred to use surgical stainless steel applicators. Also provided are methods of using these compositions and kits containing, among other items, such compositions and applicators.

A superconductive electrical direct current cable with at least two conductors insulated relative to each other is indicated, where the cable is placed with at least two conductors insulated relative to each other, where the conductors are arranged in a cryostat suitable for guidance of the cooling agent, wherein the cryostat is composed of at least one metal pipe which is surrounded by a circumferentially closed layer with thermally insulating properties. In the cryostat is arranged a strand-shaped carrier composed of insulating material, where the carrier has at least two diametrically oppositely located outwardly open grooves in each of which is arranged one of the conductors. Each conductor is composed of a plurality of superconductive elements.

An apparatus and method for moving a wire along its own axis against a high resistance to its motion causing a substantial uniaxial compression stress in the wire without allowing it to buckle. The apparatus consists of a wire gripping and moving drive wheel and guide rollers for transporting the moving wire away from the drive wheel. Wire is pressed into a peripheral groove in a relatively large diameter, rotating drive wheel by a set of small diameter rollers arranged along part of the periphery causing the wire to be gripped by the groove.

Disclosed is a splicing method of two second-generation ReBCO high temperature superconductor coated conductors (2G ReBCO HTS CCs), in which, with stabilizing layers removed from the two strands of 2G ReBCO HTS CCs through chemical wet etching or plasma dry etching, surfaces of the two high temperature superconducting layers are brought into direct contact with each other and heated in a splicing furnace in a vacuum for micro-melting portions of the surfaces of the high temperature superconducting layers to permit inter-diffusion of ReBCO atoms such that the surfaces of the two superconducting layers can be spliced to each other and oxygenation annealing for recovery of superconductivity which was lost during splicing.

A tape-shaped superconducting film-forming substrate is disclosed, which includes a film-forming face for forming a laminate including a superconducting layer thereon, a rear face that is a face at a side opposite to the film-forming face, a pair of end faces connected to the film-forming face and the rear face, and a pair of side faces connected to the film-forming face, the rear face, and the pair of end faces, in which each of the pair of side faces includes a spreading face that spreads toward an outer side in an in-plane direction of the film-forming face from an edge part of the film-forming face toward the rear face side. A superconducting wire and a superconducting wire manufacturing method are also disclosed.

A superconducting structure (1) has a plurality of coated conductor tapes (2; 2a-2o), each with a substrate (3) which is one-sided coated with a superconducting film (4), in particular an YBCO film, wherein the superconducting structure (1) provides a superconducting current path along an extension direction (z) of the superconducting structure (1), wherein the coated conductor tapes (2; 2a-2o) provide electrically parallel partial superconducting current paths in the extension direction (z) of the superconducting structure (1), is characterized in that the coated conductor tapes (2; 2a-2o) are superconductively connected among themselves along the extension direction (z) continuously or intermittently. A more stable superconducting structure with which high electric current strengths may be transported is thereby provided.

A device for the high pressure densification of superconducting wire from compacted superconductor material or superconductor precursor powder particles, has four hard metal anvils (5, 6, 7, 8) with a total length (L2) parallel to the superconducting wire, the hard metal anvils borne in external independent pressure blocks (9, 10, 11), which are in turn either fixed or connected to high pressure devices, preferably hydraulic presses. At least one of the hard metal anvils is a free moving anvil (6) having clearances of at least 0.01 mm up to 0.2 mm towards the neighboring hard metal anvils (5, 8), so that no wall friction occurs between the free moving anvil and the neighboring anvils. This allows for high critical current densities Jc at reduced pressure applied to the hard metal anvils.

A superconducting wire includes a linear superconductor and a carbon nanotube structure. The carbon nanotube structure is located on the linear superconductor. The carbon nanotube structure includes a number of carbon nanotubes joined end to end by van der Waals attractive force between and arranged helically along an axial direction of the linear superconductor.

A superconducting wire includes a superconductor layer and a carbon nanotube layer. The superconductor layer and the carbon nanotube layer are stacked on each other and rolled to form the superconducting wire. Thus, the superconductor layer and the carbon nanotube layer are simultaneously rolled and alternately stacked on each other.

A composite barrier-type Nb3Al superconducting multifilament wire material comprises Nb barrier filaments, Ta barrier filaments, Nb bulk dummy filaments, and a Nb or Ta covering. In the composite barrier-type Nb3Al superconducting multifilament wire material, the Nb barrier filaments and Ta barrier filaments are disposed in the wire material so that the Nb barrier filaments are concentrated in a filament region near a core formed from the Nb bulk dummy filaments and only the Ta barrier filaments are disposed or the Nb barrier filaments are dispersed in the Ta barrier filaments in an outer layer portion formed from a region outside the Nb barrier filaments, excluding the Nb or Ta covering.

A speech recognition system, method of recognizing speech and a computer program product therefor. A client device identified with a context for an associated user selectively streams audio to a provider computer, e.g., a cloud computer. Speech recognition receives streaming audio, maps utterances to specific textual candidates and determines a likelihood of a correct match for each mapped textual candidate. A context model selectively winnows candidate to resolve recognition ambiguity according to context whenever multiple textual candidates are recognized as potential matches for the same mapped utterance. Matches are used to update the context model, which may be used for multiple users in the same context.

A file managing software program for managing a list of elements in a specific sequence in a first file of a computer program, including the steps of copying the first file to form a second file having an identical list of elements as the first file. The user is then permitted to rearrange the sequence of the elements of the second file independently of the sequence of the first file. A display of both the first and the second file list elements is provided to the user. Further embodiments allow the user to categorize, prioritize, and order according to users specified rules of how the second file element list is organized and displayed to provide a more convenient and flexible presentation of the file contents.

An information processing apparatus configured to display a user interface on a display unit according to screen information acquired from an outside device changes the screen information according to a display attribute set by a user, and if setting of a display attribute of an object included in the screen information is unchangeable, color conversion processing of a specified object included in the screen information is performed and the screen information obtained by executing conversion processing according to the display attribute set by the user with respect to the screen information including the object which has undergone the color conversion processing is displayed.

An electronic device for text prediction in a virtual keyboard. The device includes a memory including an input determination module for execution by the microprocessor, the input determination module being configured to: receive signals representing input at the virtual keyboard, the virtual keyboard being divided into a plurality of subregions, the plurality of subregions including at least one subregion being associated with two or more characters and/or symbols of the virtual keyboard; identify a subregion on the virtual keyboard corresponding to the input; determine any character or symbol associated with the identified subregion; and if there is at least one determined character or symbol, provide the at least one determined character or symbol to a text prediction algorithm.

Images are analyzed within a 3D environment that is generated based on spatial relationships of the images and that allows users to experience the images in the 3D environment. Image analysis may include ranking images based on user viewing information, such as the number of users who have viewed an image and how long an image was viewed. Image analysis may further include analyzing the spatial density of images within a 3D environment to determine points of user interest.

A phosphazene compound having a vinyl group is manufactured by a reaction between a vinyl compound and a phosphazene compound having a hydroxyl group and added to a resin composition for manufacturing a prepreg or a resin film so as to be applicable to copper-clad laminates and printed circuit boards to thereby achieve satisfactory circuit laminate properties, namely low coefficient of thermal expansion, low dielectric properties, heat resistant, fire resistant, and halogen-free.

Alkyl nitrate ester compounds are provided for the delivery of nitric oxide to targeted muscle tissues, and in particular, to normal and dystrophic muscles. In one aspect, nitrate ester compounds are provided having the following formula: wherein, R1 is ONO2, CH2ONO2, CnH2n+1OH, CnH2n+1OH, or CH2CH2CH3, or H;R2 is ONO2, CH2ONO2, Cn'H2n'+1OH, Cn'H2n'+1OH, CH2CH2CH3 or H; andR3 is ONO2, CH2ONO2, Cn'″H2n″+1OH, Cn″H2n″+1OH, CH2CH2CH3 or H; wherein n is an integer from 0 to 9, n' is an integer from 0 to 9, and n″ is an integer from 0 to 9, and n+n'+n″≦9, and wherein at least one of R1, R2, and R3 is an ester nitrate selected from the group consisting of ONO2, CH2ONO2, and combinations thereof.