This is the 16th installment of The Rationalist, my column for the Times of India.

Steven Pinker, in his book Enlightenment Now, relates an old Russian joke about two peasants named Boris and Igor. They are both poor. Boris has a goat. Igor does not. One day, Igor is granted a wish by a visiting fairy. What will he wish for?

“I wish,” he says, “that Boris’s goat should die.”

The joke ends there, revealing as much about human nature as about economics. Consider the three things that happen if the fairy grants the wish. One, Boris becomes poorer. Two, Igor stays poor. Three, inequality reduces. Is any of them a good outcome?

I feel exasperated when I hear intellectuals and columnists talking about economic inequality. It is my contention that India’s problem is poverty – and that poverty and inequality are two very different things that often do not coincide.

To illustrate this, I sometimes ask this question: In which of the following countries would you rather be poor: USA or Bangladesh? The obvious answer is USA, where the poor are much better off than the poor of Bangladesh. And yet, while Bangladesh has greater poverty, the USA has higher inequality.

Indeed, take a look at the countries of the world measured by the Gini Index, which is that standard metric used to measure inequality, and you will find that USA, Hong Kong, Singapore and the United Kingdom all have greater inequality than Bangladesh, Liberia, Pakistan and Sierra Leone, which are much poorer. And yet, while the poor of Bangladesh would love to migrate to unequal USA, I don’t hear of too many people wishing to go in the opposite direction.

Indeed, people vote with their feet when it comes to choosing between poverty and inequality. All of human history is a story of migration from rural areas to cities – which have greater inequality.

If poverty and inequality are so different, why do people conflate the two? A key reason is that we tend to think of the world in zero-sum ways. For someone to win, someone else must lose. If the rich get richer, the poor must be getting poorer, and the presence of poverty must be proof of inequality.

But that’s not how the world works. The pie is not fixed. Economic growth is a positive-sum game and leads to an expansion of the pie, and everybody benefits. In absolute terms, the rich get richer, and so do the poor, often enough to come out of poverty. And so, in any growing economy, as poverty reduces, inequality tends to increase. (This is counter-intuitive, I know, so used are we to zero-sum thinking.) This is exactly what has happened in India since we liberalised parts of our economy in 1991.

Most people who complain about inequality in India are using the wrong word, and are really worried about poverty. Put a millionaire in a room with a billionaire, and no one will complain about the inequality in that room. But put a starving beggar in there, and the situation is morally objectionable. It is the poverty that makes it a problem, not the inequality.

You might think that this is just semantics, but words matter. Poverty and inequality are different phenomena with opposite solutions. You can solve for inequality by making everyone equally poor. Or you could solve for it by redistributing from the rich to the poor, as if the pie was fixed. The problem with this, as any economist will tell you, is that there is a trade-off between redistribution and growth. All redistribution comes at the cost of growing the pie – and only growth can solve the problem of poverty in a country like ours.

It has been estimated that in India, for every one percent rise in GDP, two million people come out of poverty. That is a stunning statistic. When millions of Indians don’t have enough money to eat properly or sleep with a roof over their heads, it is our moral imperative to help them rise out of poverty. The policies that will make this possible – allowing free markets, incentivising investment and job creation, removing state oppression – are likely to lead to greater inequality. So what? It is more urgent to make sure that every Indian has enough to fulfil his basic needs – what the philosopher Harry Frankfurt, in his fine book On Inequality, called the Doctrine of Sufficiency.

The elite in their airconditioned drawing rooms, and those who live in rich countries, can follow the fashions of the West and talk compassionately about inequality. India does not have that luxury.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
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Hi everyone! I'm working on a small battery powered PCB which will fit inside a small plastic "hockey puck" container. A number of these "pucks" will be sold together with a "charging doc" which will store and charge the pucks when not in use.

I'm trying to work out the best way to charge the battery. I'm thinking of having metal "pads" on the rr.com puck that pass through the puck's plastic shell and then make contact with the PCB on the inside, and having a similar system on the charging dock. I'm thinking of having SMD "contact sprints" mounted to the underside of the PCB and have these mate against metal pins that protrude through the puck, but it's the later of which I'm struggling to find. For a visual, think about "restaurant pagers" and how they charge.

Is it possible to change trace ends from round to square? Allegro PCB Designer 17.2 (basic)

Thanks

I want to write a transition coverage on an enumeration. One of the parts of that transition is a queue of the enum. I construct this queue in my constructor. Considering the example below, how would one go about it.

In my coverage bin I can create a range like this A => [queue1Enum[0]:queue1Enum[$]] => [queue2Enum[0]:queue2Enum[$]]. But I only get first and last element then.

typedef enum { red, d_green, d_blue, e_yellow, e_white, e_black } Colors;
 Colors dColors[$];
 Colors eColors[$];
 Lcolors = Colors.first();
 do begin
  if (Lcolors[0].name=='d') begin
   dColors.push_back(Lcolors);
  end
  if (Lcolors[0].name=='e') begin
   eColors.push_back(Lcolors);
  end
 end while(Lcolors != Lcolors.first())

 covergroup cgTest with function sample(Colors c);
   cpTran : coverpoint c{
      bins t[] = (red => dColors =>eColors);   
   }
 endgroup

Hello,

I have a question I want to create a cover that consists a sparse values, pre-computed (a list or define) for example l = {1; 4; 7; 9; 2048; 700} I'd like to cover that data a (uint(bits:16)) had those values, Any suggestion on how to achieve this, I'd prefer to stay away from macros, and avoid to write a lot of code

struct inst {

  data :uint(bits:16);
  opcode :uint(bits:16);
  !valid_data : list of uint(bits:16) = {0; 12; 10; 700; 890; 293;};
  event data_e;
  event opcode_e;

  cover data_e is {
     item data using radix = HEX, ranges = {
     //I dont want to write all of this
     range([0], "My range1");
     range([10], "My range2");
     //... many values in between
    range([700], "My rangen");
    };

    item opcode;

   cross data, opcode;
};

post_generate() is also {
    emit data_e;
};
};

Hello,

I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.

When I use the settings below to import the modules into a library, it imports it correctly but completely ignores all `define directive; hence when I simulate using any of the modules below the simulator errors out requesting these variables.

My question: Is there a way to make Verilog In consider `define directives in every module cell created? 

Code to be imported by Cadence Verilog In:

--------------------------------------------------------

`timescale 1ns/1ps
`define PROP_DELAY 1.1
`define INVALID_DELAY 1.3

`define PERIOD 1.1
`define WIDTH 1.6
`define SETUP_TIME 2.0
`define HOLD_TIME 0.5
`define RECOVERY_TIME 3.0
`define REMOVAL_TIME 0.5
`define WIDTH_THD 0.0

`celldefine
module MY_FF (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF
`endcelldefine

`timescale 1ns/1ps
`celldefine
module MY_FF2 (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF2
`endcelldefine

--------------------------------------------------------

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9

Hi, 

I want my layout verified by Quantus QRC. But, I can't find the tool bar on the option list ( as show in the picture)

I have tried to install EXT182 and configured it with iscape already, and also make some path settings on .bashrc, .cshrc. But, when I re-source .cshrc and run virtuoso again, I just can't find the toolbar. 

If you have some methods, please let me know.

Thanks a lot!

Appreciated

My virtuoso version is: ICADV12.3

Hi,

I am trying to characterize a D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). This is a positive edge triggered D flip flop based on true-single-phase clocking scheme. After the characterization, the measurements reported for hold constraint arcs seem to deviate significantly from its (spectre) spice simulation.

The constraint and the power settings to the liberate are as follows : 

# -------------------------------------------- Timing Constraints --------------------------------------------------------------------------------
### Input waveform ###
set_var predriver_waveform 2;# 2=use pre-driver waveform
### Capacitance ###
set_var min_capacitance_for_outputs 1;# write min_capacitance attribute for output pins
### Timing ###
set_var force_condition 4
### Constraint ###
set_var constraint_info 2
#set_var constraint_search_time_abstol 1e-12 ;# 1ps resolution for bisection search
set_var nochange_mode 1 ;# enable nochange_* constraint characterization
### min_pulse_width ###
set_var conditional_mpw 0
set_var constraint_combinational 2

#---------------------------------------------- CCS Settings ----------------------------------------------------------------------------------------
set_var ccsn_include_passgate_attr 1
set_var ccsn_model_related_node_attr 1
set_var write_library_is_unbuffered 1

set_var ccsp_min_pts 15 ;# CCSP accuracy
set_var ccsp_rel_tol 0.01 ;# CCSP accuracy
set_var ccsp_table_reduction 0 ;# CCSP accuracy
set_var ccsp_tail_tol 0.02 ;# CCSP accuracy
set_var ccsp_related_pin_mode 2 ;# use 3 for multiple input switching scnarios and Voltus only libraries

#----------------------------------------------- Power ---------------------------------------------------------------------------------------------------
### Leakage ###
set_var max_leakage_vector [expr 2**10]
set_var leakage_float_internal_supply 0 ;# get worst case leakage for power switch cells when off
set_var reset_negative_leakage_power 1 ;# convert negative leakage current to 0

### Power ###
set_var voltage_map 1 ;# create pg_pin groups, related_power_pin / related_ground_pin
set_var pin_based_power 0 ;# 0=based on VDD only; 1=power based on VDD and VSS (default);
set_var power_combinational_include_output 0 ;# do not include output pins in when conditions for combinational cells

set_var force_default_group 1
set_default_group -criteria {power avg} ;# use average for default power group

#set_var power_subtract_leakage 4 ;# use 4 for cells with exhaustive leakage states.
set_var subtract_hidden_power 2 ;# 1=subtract hidden power for all cells
set_var subtract_hidden_power_use_default 3 ;# 3=subtract hidden power from matched when condition then default group
set_var power_multi_output_binning_mode 1 ;# binning for multi-output cell considered for both timing and power arcs
set_var power_minimize_switching 1
set_var max_hidden_vector [expr 2**10]
#--------------------------------------------------------------------------------------------------------------------------------------------------------------

I specifically used set_var constraint_combinational 2 in the settings, in case the Bisection pass/fail mode fails to capture the constraints. In my spice simulation, the hold_rise (D=1, CLK=R, Q=R) arc at-least requires ~250 ps for minimum CLK/D slew combination (for the  by default smallest capacitive load as per Liberate)  while Liberate reports only ~30 ps. The define_cell template to this flip flop is pretty generic, which does not have any user specified arcs. So which settings most likely affecting the constraint measurements in Liberate and how can I debug this issue ?

Thanks

Anuradha

Hello,

I am using Virtuoso 6.1.7.

I am performing the parasitic extraction of a MOM cap array of 32 caps. I use Quantus QRC and I enable field solver. I select “QRCFS” for field solver type and “High” for field solver accuracy. The unit MOM cap is horizontally and vertically symmetric. The array looks like the sketch below and there are no other structures except the unit caps:

Rationally speaking, the capacitance values of the unit caps should be symmetric with respect to a vertical symmetry axis that is between cap16 and cap17 (shown with dashed red line). For example,

the capacitance of cap1 should be equal to the capacitance of cap32

the capacitance of cap2 should be equal to the capacitance of cap31

etc. as there are no other structures around the caps that might create some asymmetry.

Nevertheless, what I observe is the following after the parasitic extraction:

As it can be seen, the result is not symmetric contrary to what is expected. I should also add that I do not observe this when I perform parasitic extraction with no filed solver.

Why do I get this result? Is it an artifact resulting from the field solver tool (my conclusion was yes but still it must be verified)? If not, how can something like this happen?

Many thanks in advance.

Best regards,

Can

Hello,

I'm reading the Design specification for IP6514E.

We will use the DAC mode.

It would seem to be very simple but I don't see any code sequence, i.e.

  1.Write 03(Basic Read) to this register

  2, Write start adress to this register

  3. Write "execute" to this register

  4. Read the data from this register

Thanks,

Stefan

پوری دنیا میں کوروناوائرس (Coronavirus) کا خوف ہے۔ لوگ گھروں سے باہر نکلنے میں بھی ڈر رہے ہیں لیکن ایسالگ رہا ہے کہ پاکستان (Pakistan) کے لوگوں کوکوروناوائرس کا کوئی ڈر نہیں ہے۔

میگھالیہ (Meghalaya) میں کوروناوائرس (Coronavirus) سے جان گنوانے والے پہلے شخص 69 سالہ ایک ڈاکٹر کو موت کے 36 گھنٹے بعد جمعرات کو یہاں دفنا دیا گیا۔ ایک قبرستان نے کوروناوائرس سے جان گنوانے والے لوگوں کی لاشوں کو دفنانے کیلئے پی پی ای نہیں ہونے اور مقامی لوگوں کی مخالفت کا حوالہ دیتے ہوئے ڈاکٹر کی بدھ کو آخری رسوم کرنے سے انکار کردیا تھا۔

شہزادی بسمہ نے ٹویٹر اکاونٹ پر لکھا جیسا کہ آپ جانتے ہیں کہ فی الحال میں الحائر جیل میں کسی جرم کے بغیر سزا کاٹ رہی ہوں ، میری صحت اس حد تک بگڑ رہی ہے کہ اس سے میری موت تک ہوسکتی ہے ۔

لاک ڈٓاون کی خلاف ورزی کرنے پر پولیس نے ان لوگوں کو حراست میں لے لیا ۔ حالانکہ بعد میں انہیں چھوڑ بھی دیا گیا ، لیکن ایمبولنس ڈرائیور کو پولیس نے ضرور گرفتار کرلیا اور اس کی گاڑی بھی ضبط کرلی ۔

મહેસાણાઃ મહેસાણામાં આવેલ નાગલપુર કોલેજમાં એક તરફી પ્રેમમાં યુવકે વિદ્યાર્થીની પર એસિડ વડે હુમલો કર્યો છે. ત્યારે એસિડ એટેક તરનાર હાર્દિક પ્રજાપતીની પોલીસે ધરપકડ કરી છે. તેણે કોલેજમાં ફસ્ટયરમાં અભ્યાસ કરતી વિદ્યાર્થીની પર હુમલો કરાયો કર્યો હતો.

ایک رپورٹ کے مطابق ڈپارٹمینٹ آف ہیومن سروس نے جنم کی شرح کا ڈاٹا رلیز کیا تھا جس کے مطابق بچوں کو جنم دینے والے 22 مرد ٹرنسجینڈر تھے۔ حالانکہ سال 2009 تک اس سلسلے میں کوئی اعدادوشمار سامنے نہیں آیا تھا۔ بچوں کو جنم دینے کے ساتھ ہی ان مردوں کا 228 کی اس فہرست میں شامل ہوگیا جس میں گزشتہ ایک دہائی میں بچوں کو جنم دینے والے لوگوں کے نام درج تھے۔

حسین جہاں کا ایک ویڈیو سوشل میڈیا پر فینس کافی پسند کررہے ہیں ، جس میں وہ ڈانس کررہی ہیں ۔

حکومت نے کہا ہے کہ یہ سہولت ادائیگی کی بنیاد پر مہیا کرائی جائےگی ۔ ان شہریوں کو لانے کیلئے خصوصی مسافر پروازوں کا انتظام کیا جائےگا ۔

ریلائنس جیو میں یہ تیسری ہائی پروفائل سرمایہ کاری ہے۔ فیس بک نے جیو میں 9.9 فیصد حصے داری 43،534 کروڑ روپئے میں اور سلور لیک نے 555 کروڑ میں 1.55فیصد حصے داری کی سرمایہ کاری کی۔ اس ہفتے کی شروعات میں Jio میں سلور لیک کے ذریعے کی گئی سرمایہ کاری بھی فیس بک ڈیل کے پریمیم جیسی تھی۔ تین ہفتوں کے اندر جیو پلیٹ فارم نے ٹیکنا لوجی سرمایہ کاروں سے 60،596.37 کروڑ روپئے جٹائے ہیں۔

ملزم ٹیچر نے ایسے چیٹس کی جانکاری ہونے پر طلبہ و طالبات کو وارننگ دی ہے کہ وہ پولیس میں شکایت کرے گا ۔

#સાબરકાંઠા જિલ્લાના બહુચર્ચિત રૂ.55 લાખના પુસ્તક કૌભાંડમાં ચોંકાવનારી વિગતો સામે આવી છે. આ મામલે આરોપી ક્લાર્કની ધરપકડ કરાતાં રિમાન્ડ દરમિયાન અન્ય સ્ફોટક માહિતી સામે આવી છે. ચકચારી આ કૌભાંડમાં કચેરીના અધિકારી અને અન્ય કર્મચારીઓ પણ સંકળાયેલા હોવાનું પોલીસ તપાસમાં ખુલવા પામ્યું છે.

USની PE ફર્મ Vista Equity પાર્ટનર્સ Jio પ્લેટફોર્મ્સમાં રૂ.‌11,367 કરોડનું રોકાણ કરશે

વડોદરાઃ વડોદરામાં પ્રથમ વખત રાજય સરકારના ઉર્જા અને પેટ્રોકેમિકલ્સ વિભાગ અને એફજીઆઈના સંયુકત ઉપક્રમે 6 થી 10 ઓકટોબર દરમિયાન સ્વીચ 2016 પ્રદર્શન યોજાશે.ઈલેકટ્રીકલ્સ એન્જીનીયરીંગ અને નાવીન્યપૂર્ણ શોધ સંદર્ભે આતંરરાષ્ટ્રીય સ્વીચ પ્રદર્શન યોજાશે.

શિયાળામાં ઠંડીની શરૂઆત થતા જ લોકોના ઘરમાં લીલી હળદરનું શાક બને છે. લોકો આ શાકને બાજરીના રોટલા સાથે ખાય છે. જેના ફાયદા પણ અનેક છે. તમે પણ આ સ્વાસ્થ્યવર્ધક લીલી હળદરનું ગ્રેવીવાળું શાક બનાવાવની Recipe નોંધી લો.

જાન્યુઆરીથી માર્ચ 2020 દરમિયાન કંપનીની નેટ પ્રોફિટ (Jio Net Profit)લગભગ ત્રણ ગણી વધીને 2,331 કરોડ રુપિયા પહોંચી ગઇ, રિલાયન્સ જિયો 38.75 કરોડ સબ્સક્રાઇબર્સની સાથે દુનિયાની સૌથી મોટી ટેલિકોમ કંપની છે

રિલાયન્સ ઇન્ડસ્ટ્રીઝ (RIL-Reliance Industries Q4 Results)નો ચોથા ક્વાર્ટ્સ એટલે કે જાન્યુઆરી-માર્ચનો નફો 6,348 કરોડ રુપિયા રહ્યો

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dnsmasq-utils version 2.79-1 dhcp_release denial of service proof of concept exploit.

Inout PPC Engine suffers from a cross site request forgery vulnerability.