A controller receives a request to perform a release space operation. A determination is made that a new discard scan has to be performed on a cache, in response to the received request to perform the release space operation. A determination is made as to how many task control blocks are to be allocated to the perform the new discard scan, based on how many task control blocks have already been allocated for performing one or more discard scans that are already in progress.

For a plurality of input/output (I/O) operations waiting to assemble complete data tracks from data segments, a process, separate from a process responsible for the data assembly into the complete data tracks, is initiated for waking a predetermined number of the waiting I/O operations.

A flash memory file system including a plurality of flash modules. Each of the plurality of flash modules includes a respective cache memory, a respective flash memory, and a respective flash controller in communication with the respective cache memory and the respective flash memory. A first flash module of the plurality of flash modules is configured to receive a file lookup message including a path name for file data stored on a second flash module of the plurality of flash modules. A third flash module of the plurality of flash modules is configured to select the second flash module based on the path name and a directory table, and generate a file metadata message responsive to the file lookup message. The file metadata message identifies the second flash module as containing the file data.

Systems, processors, and methods for keeping uncacheable data coherent. A processor includes a multi-level cache hierarchy, and uncacheable load memory operations can be cached at any level of the cache hierarchy. If an uncacheable load misses in the L2 cache, then allocation of the uncacheable load will be restricted to a subset of the ways of the L2 cache. If an uncacheable store memory operation hits in the L1 cache, then the hit cache line can be updated with the data from the memory operation. If the uncacheable store misses in the L1 cache, then the uncacheable store is sent to a core interface unit. Multiple contiguous store misses are merged into larger blocks of data in the core interface unit before being sent to the L2 cache.

Provided is a method and system for reducing duplicate buffers in buffer cache associated with a storage device. Reducing buffer duplication in a buffer cache includes accessing a file reference pointer associated with a file in a deduplicated filesystem when attempting to load a requested data block from the file into the buffer cache. To determine if the requested data block is already in the buffer cache, aspects of the invention compare a fingerprint that identifies the requested data block against one or more fingerprints identifying a corresponding one or more sharable data blocks in the buffer cache. A match between the fingerprint of the requested data block and the fingerprint from a sharable data block in the buffer cache indicates that the requested data block is already loaded in buffer cache. The sharable data block in buffer cache is used instead thereby reducing buffer duplication in the buffer cache.

A heterogeneous memory system includes a main memory arrangement, a first-level cache, and a memory management unit (MMU). The first-level cache includes an SRAM arrangement and a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the SRAM arrangement or the DRAM arrangement for storage of the first data and stores the first data in the selected one of the SRAM arrangement or DRAM arrangement. The MMU reads second data from one of the SRAM arrangement or DRAM arrangement and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.

Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.

Techniques for handling version information using a copy engine. In one embodiment, an apparatus comprises a copy engine configured to perform one or more operations associated with a block memory operation in response to a command. Examples of block memory operations may include copy, clear, move, and/or compress operations. In one embodiment, the copy engine is configured to handle version information associated with the block memory operation based on the command. The one or more operations may include operating on data in a cache and/or modifying entries in a memory. In one embodiment, the copy engine is configured to compare version information in the command with stored version information. The copy engine may overwrite or preserve version information based on the command. The copy engine may be a coprocessing element. The copy engine may be configured to maintain coherency with other copy engines and/or processing elements.

Systems, methods, and other embodiments associated with a distributed cache coherency protocol are described. According to one embodiment, a method includes receiving a request from a requester for access to one or more memory blocks in a block storage device that is shared by at least two physical computing machines and determining if a caching right to any of the one or more memory blocks has been granted to a different requester. If the caching right has not been granted to the different requester, access is granted to the one or more memory blocks to the requester.

To provide a storage device with low power consumption. The storage device includes a plurality of cache lines. Each of the cache lines includes a data field which stores cache data; a tag which stores address data corresponding the cache data; and a valid bit which stores valid data indicating whether the cache data stored in the data field is valid or invalid. Whether power is supplied to the tag and the data field in each of the cache lines is determined based on the valid data stored in the valid bit.

A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.

In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity to help determine whether a reallocation of resources between nodes may improve memory affinity for a logical partition or for the computer system. If so, the reallocation of resources is performed so memory affinity for the logical partition or computer system is improved. Memory affinity is computed relative to the physical layout of the resources according to a hardware domain hierarchy that includes a plurality of primary domains and a plurality of secondary domains.

A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit.

A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range.

An optical backup apparatus is provided and includes an optical storage device, an interface module to connect with at least one type of external storage medium, and a control unit to back up data from the external storage medium to the optical storage device in response to an external remote control operation.

Machine implemented method and system for generating a disaster recovery copy of an expandable storage volume having a namespace for storing information for accessing data objects stored at a data constituent volume is provided. A transfer operation for transferring a point in time copy of the expandable storage volume from a first location to a second location is generated. Information regarding the expandable storage volume from the first location is retrieved and a destination expandable storage volume is resized to match components of the expandable storage volume at the first location. Thereafter, the point in time copy of the expandable storage volume is transferred from the first location to the second location and configuration information regarding the point in time copy is copied from the first location to the second location.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

A method and computer-readable storage media are provided for rearranging data in physical memory units. In one embodiment, a method may include monitoring utilization counters. The method may further include, comparing the utilization counters for a match with an instance in a first table containing one or more instances when data may be rearranged in the physical memory units. The table may further include where the data should be relocated by a rearrangement. The method may also include, continuing to monitor the utilization counters if a match is not found with an instance in the first table. The method may further include, rearranging the data in the physical memory units if a match between the utilization counters and an instance in the first table is found.

Methods and apparatuses for implementing a system cache with quota-based control. Quotas may be assigned on a group ID basis to each group ID that is assigned to use the system cache. The quota does not reserve space in the system cache, but rather the quota may be used within any way within the system cache. The quota may prevent a given group ID from consuming more than a desired amount of the system cache. Once a group ID's quota has been reached, no additional allocation will be permitted for that group ID. The total amount of allocated quota for all group IDs can exceed the size of system cache, such that the system cache can be oversubscribed. The sticky state can be used to prioritize data retention within the system cache when oversubscription is being used.

Proposed are a management apparatus and a management method capable of improving the stability of the overall computer system. In a computer system which manages a storage area provided by each of a plurality of mutually connected storage apparatuses as a logical pool, provides to a host computer a virtual volume associated with the logical pool, and assigns a real storage area from the logical pool to the virtual volume when the host computer writes into the virtual volume, when a storage apparatus is added to the plurality of storage apparatuses, the host computer is controlled to switch the access path to the added storage apparatus.

A mechanism is provided in a storage device for performing a write operation. The mechanism configures a write buffer memory with a plurality of write buffer portions. Each write buffer portion is dedicated to a predetermined block size category within a plurality of block size categories. For each write operation from an initiator, the mechanism determines a block size category of the write operation. The mechanism performs each write operation by writing to a write buffer portion within the plurality of write buffer portions corresponding to the block size category of the write operation.

Various systems and methods are described for configuring a logical data storage container. In one embodiment, an instruction to perform an operation to modify an attribute of the logical data storage container that is an abstraction of a plurality of pertinent storage containers is received. A translated instruction to perform a sub-operation associated with the operation is transmitted to each of a number of the plurality of pertinent storage containers. A level of success of the performing of the operation on the logical data storage container is detected based on a comparison of a threshold value to a level of success of the performing of the sub-operation on each of the number of the plurality of pertinent storage containers. A report of the detected level of success is communicated.

A dispersed storage (DS) unit for use within a dispersed storage network is capable of self-configuring using registry information provided to the DS unit. The registry information includes a slice name assignment indicating a range of slice names corresponding to a plurality of potential data slices of potential data objects to be stored in the DS unit. Based on the registry information, the DS unit allocates a portion of physical memory to store the potential data slices.

A partition manager relocates a logical partition from a primary shared processor pool to a secondary shared processor pool in response to a predetermined condition, such as a hardware failure. The relocated logical partition is allocated a smaller quantity of processing units from the secondary pool than it was allocated from the primary pool. A quantity of processing units reserved for a second logical partition is identified in the secondary shared processor pool, and a portion of those reserved processing units are allocated to the relocated logical partition. The reserved processing units may be redistributed among multiple relocated logical partitions.

System and method for conversion of virtual machine files without requiring copying of the virtual machine payload (data) from one location to another location. By eliminating this step, applicant's invention significantly enhances the efficiency of the conversion process. In one embodiment, a file system or storage system provides indirections to locations of data elements stored on a persistent storage media. A source virtual machine file includes hypervisor metadata (HM) data elements in one hypervisor file format, and virtual machine payload (VMP) data elements. The source virtual machine file is converted by transforming the HM data elements of the source file to create destination HM data elements in a destination hypervisor format different from the source hypervisor format; maintaining the locations of the VMP data elements stored on the persistent storage media constant during the conversion from source to destination file formats without reading or writing the VMP data elements; and creating indirections to reference the destination HM data elements in the destination hypervisor format and the existing stored VMP data elements.

The invention pertains to a memory management unit for a microprocessor system, the memory management unit being connected or connectable to at least one processor core of the microprocessor system and being connected or connectable to a physical memory of the microprocessor system. The memory management unit is adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware The memory management unit comprises a first register table indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other; a second register table indicating an allowed address range of physical addresses accessible to a process running in or under supervisor mode; wherein the memory management unit is adapted to prevent write access to the second register table by a process not in hypervisor mode. The memory management unit is further adapted to allow write access to the first register table of a process running in or under supervisor mode to reconfigure the physical address information indicated in the first register table with memory mapping information relating to at least one physical address, if the at least one physical address is in the allowed address range, and to prevent write access to the first register table of the process running in or under supervisor mode if the at least one physical address is not in the allowed address range. The invention also pertains to a microprocessor system and a method for managing memory.

Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.

A prefetch optimizer tool for an information handling system (IHS) may improve effective memory access time by controlling both hardware prefetch operations and software prefetch operations. The prefetch optimizer tool selectively disables prefetch instructions in an instruction sequence of interest within an application. The tool measures execution times of the instruction sequence of interest when different prefetch instructions are disabled. The tool may hold hardware prefetch depth constant while cycling through disabling different prefetch instructions and taking corresponding execution time measurements. Alternatively, for each disabled prefetch instruction in the instruction sequence of interest, the tool may cycle through different hardware prefetch depths and take corresponding execution time measurements at each hardware prefetch depth. The tool selects a combination of hardware prefetch depth and prefetch instruction disablement that may improve the execution time in comparison with a baseline execution time.

A dynamically expandable and contractible fault-tolerant storage system employs a virtual hot spare that is created from unused storage capacity across a plurality of storage devices. This unused storage capacity is available if and when a storage device fails for storage of data recovered from the remaining storage device(s). On an ongoing basis, the storage system may determine the amount of unused storage capacity that would be required for the virtual hot spare (e.g., based on the number of storage devices, the capacities of the various storage devices, the amount of data stored, and the manner in which the data is stored) and generate a signal if additional storage capacity is needed for a virtual hot spare.

A method and apparatus are disclosed of monitoring a number of virtual machines operating in an enterprise network. One example method of operation may include identifying a number of virtual machines currently operating in an enterprise network and determining performance metrics for each of the virtual machines. The method may also include identifying at least one candidate virtual machine from the virtual machines to optimize its active application load and modifying the candidate virtual machine to change its active application load.

A data processing entity that includes a mass memory with a plurality of memory locations for storing memory blocks. Each of a plurality of software images includes a plurality of memory blocks with corresponding image addresses within the software image. The memory blocks of software images stored in boot locations of a current software image are relocated. The boot blocks of the current software image are stored into the corresponding boot locations. The data processing entity is booted from the boot blocks of the current software image in the corresponding boot locations, thereby loading the access function. Each request to access a selected memory block of the current software image is served by the access function, with the access function accessing the selected memory block in the associated memory location provided by the control structure.

In a satellite communication system comprising at least a hub and a plurality of terminals, at least one terminal may include a cache for storing data objects. The cache may be based on a detachable memory device that may be inserted to or removed from the terminal at any given time, including after the terminal is deployed. Aspects are directed to preventing a prefetching of objects already stored in a cache of a remote terminal. In some embodiments, an efficient multicasting of content to terminals over an adaptive link may occur in a manner which may benefit terminals comprising a cache while not affecting or minimally affecting the performance of terminals that may not include a cache.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

A method and system for dynamic distributed data caching is presented. The system includes one or more peer members and a master member. The master member and the one or more peer members form cache community for data storage. The master member is operable to select one of the one or more peer members to become a new master member. The master member is operable to update a peer list for the cache community by removing itself from the peer list. The master member is operable to send a nominate master message and an updated peer list to a peer member selected by the master member to become the new master member.

The present application relates to novel substituted 1-benzylcycloalkylcarboxylic acid derivatives, to processes for their preparation, to their use for the treatment and/or prevention of diseases, and to their use for producing medicaments for the treatment and/or prevention of diseases, especially for the treatment and/or prevention of cardiovascular disorders.

The present invention provides α-keto alkylperacids and methods for producing and using the same. In particular, α-keto alkylperacids are useful as antimicrobial agents.

The present application relates to novel 3-phenylpropionic acid derivatives, to processes for their preparation, to their use for the treatment and/or prevention of diseases and to their use for preparing medicaments for the treatment and/or prevention of diseases, in particular for the treatment and/or prevention of cardiovascular disorders.

In a process for the separation and drying of crude carboxylic acid crystals from a slurry in a solvent, the slurry is supplied to a filter operating at pressure and at a temperature above the atmospheric boiling point of the solvent. A cake of separated crystals is removed from the filter and passed to a thermal dryer. In a system for the separation and drying of crude carboxylic acid from a slurry in a solvent, a pressure filter device has a slurry inlet and an outlet for a cake of carboxylic acid crystals. The system also has a thermal dryer and means for transporting the cake of carboxylic acid crystals from the pressure filter device to the dryer. The pressure filter device is configured to operate at a pressure and temperature above the atmospheric boiling point of the solvent.

A thermal separation process between a gas ascending in a separating column and a liquid descending in the separating column, which comprise (meth)acrylic monomers, wherein the separating column comprises a sequence of crossflow mass transfer trays, the crossflow mass transfer trays of which have passage orifices for the ascending gas in crossflow direction both in front of and beyond a downcomer for the descending liquid, and such crossflow mass transfer trays and one such crossflow mass transfer tray in a sequence of crossflow mass transfer trays present in a separating column.

A process is provided for recovering aliphatic monocarboxylic acids having from 4 to 11 carbon atoms from the distillation residue obtained in the oxidation of the corresponding aldehyde by means of oxygen or oxygen-containing gas mixtures in the presence of alkali metal carboxylates or alkaline earth metal carboxylates to form the corresponding monocarboxylic acid and subsequent distillation, characterized in that the distillation residue is reacted with an aqueous acid in a tube reactor and the two-phase mixture flowing out from the tube reactor is introduced into a settling vessel in which the organic phase which separates out has a pH of 4.5 or less.

The present invention relates to the use of at least one sulfonic acid for recovering glycerol resulting from a reaction crude from transesterification of glycerides, in particular of triglycerides of vegetable and/or animal origin. The invention also relates to a process for purifying glycerol obtained as a by-product of triglyceride transesterification during the preparation of fatty acids, fatty esters and/or fatty acid salts, and also to a combined process for preparing, on the one hand, fatty acids, fatty esters and/or fatty acid salts and, on the other hand, glycerol, from triglycerides, using at least one sulfonic acid.

A reaction system suitable for production of a methionine salt contains a reactive rectification column containing a weir having a height of 100 mm or more.

According to one embodiment, an actinic-ray- or radiation-sensitive resin composition includes any of the compounds (A) of general formula (I) below that when exposed to actinic rays or radiation, generates an acid and a resin (B) whose rate of dissolution into an alkali developer is increased by the action of an acid. (The characters used in general formula (I) have the meanings mentioned in the description.)

A radiation-sensitive composition includes a compound represented by a formula (1), and a polymer having a structural unit that includes an acid-labile group. In the formula (1), R1 represents a group having a polar group; n is an integer of 1 to 4, wherein, in a case where R1 is present in a plurality of number, the plurality of R1s are identical or different, and optionally at least two R1s taken together represent a cyclic structure; A represents an alicyclic hydrocarbon group having a valency of (n+1); and M+ represents a monovalent onium cation.

The invention discloses a deep-ultraviolet chemically-amplified positive photoresist. The deep-ultraviolet chemically-amplified positive photoresist according to one embodiment of the invention includes a cyclopentenyl pimaric acid, a divinyl ether, a photoacid generator and an organic solvent. The deep-ultraviolet chemically-amplified positive photoresist according to the invention has a good sensitivity and a good transparency.

The invention features methods and compositions for the synthesis of multimerizing agents. An exemplary method for producing AP20187 may comprise: (a) coupling 2-N,Ndimethylaminomethyl-1,3-diaminopropane with AP20792 to produce the dimeric alcohol, AP20793; and (b) coupling the AP20793 so produced with API7362 to yield AP20187. In particular embodiments, the method further includes the step of producing API7362 by coupling API7360 with methyl-L-pipecolic acid, or a salt thereof.

An ammonium hydroxyfluoroalkanesulfinate is obtained by using an organic base while sulfinating a bromofluoroalcohol with a sulfinating agent. An ammonium hydroxyfluoroalkanesulfonate is obtained by oxidizing the ammonium hydroxyfluoroalkanesulfinate. An onium fluoroalkanesulfonate is obtained by converting the ammonium hydroxyfluoroalkanesulfonate into an onium salt through esterification. This onium fluoroalkanesulfonate is useful as a photoacid generator in chemically amplified resists and the like.

Methods of producing terephthalic acid are described. The methods involve using a substantially pure p-toluic acid stream. The substantially pure p-toluic acid stream, a solvent comprising an ionic liquid and optionally a carboxylic acid, a bromine source, a catalyst, and an oxidizing agent are contacted to produce a product comprising terephthalic acid.

Bio-based terephthalic acid (bio-TPA), bio-based dimethyl terephthalate (bio-DMT), and bio-based polyesters, which are produced from a biomass containing a terpene or terpenoid, such as limonene are described, as well as the process of making these products. The bio-based polyesters include poly(alkylene terephthalate)s such as bio-based poly(ethylene terephthalate) (bio-PET), bio-based poly(trimethylene terephthalate) (bio-PTT), bio-based poly(butylene terephthalate) (bio-PBT), and bio-based poly(cyclohexylene dimethyl terephthalate) (bio-PCT).