1 Zambian Kwacha = 0.0206 Japanese Yen

1 South Korean Won = 0.0875 Japanese Yen

1 Jordanian Dinar = 150.3529 Japanese Yen

1 Lebanese Pound = 0.0705 Japanese Yen

1 Bahraini Dinar = 282.0781 Japanese Yen

1 Chilean Peso = 0.1292 Japanese Yen

1 Maldivian Rufiyaa = 6.8807 Japanese Yen

1 Malaysian Ringgit = 24.6135 Japanese Yen

1 Nicaraguan Cordoba Oro = 3.1007 Japanese Yen

1 Netherlands Antillean Guilder = 59.4229 Japanese Yen

1 Estonian Kroon = 7.4795 Japanese Yen

1 Danish Krone = 15.5032 Japanese Yen

1 Fiji Dollar = 47.3476 Japanese Yen

1 New Zealand Dollar = 65.4775 Japanese Yen

1 Croatian Kuna = 15.3743 Japanese Yen

1 Peruvian Nuevo Sol = 31.3842 Japanese Yen

1 Dominican Peso = 1.9381 Japanese Yen

1 Papua New Guinean Kina = 31.0974 Japanese Yen

1 Brunei Dollar = 75.4822 Japanese Yen

PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus is predominantly around the latest updates for PCIe Gen 5 which its version 1.0 specification was just released this year in May.  A series of presentations provided by PCI-SIG on the day 1 with comprehensive information covering all aspects of Gen 5 specification, including protocol, logical, electrical, compliance updates. On the day 2 (only in Taipei), several member companies shared their view on Testing, PCB analysis and Signal integrity. The exhibit is also another spotlight of this event where the member companies showcased their latest PCIe solutions.

Presentation Track (Taipei), Exhibit (Tokyo), Exhibit (Taipei) 

Cadence, as the market leading PCIe IP vendor, participated APAC tour this year with bringing in its latest PCIe IP solution offering (Gen 5/4) to the region as well as showcasing two live demo setups in the exhibit floor. One setup is the PCIe software development kit (SDK) while the other is the Interop/compliance/debug platform. Both come with the Cadence PCIe Gen 4 hardware setup and its corresponding software kit.

The SDK can be used for Device Driver Development, Firmware Development, and for pre-silicon emulation as well. It supports Xtensa and ARM processor with Linux OS and it also equip with Ethernet interface which can be used for remote debugging. It also supports PCIe stress tests for Speed change, link enable/disable, entry/exist for lower power states, …etc. 

Cadence PCIe 4.0 Software Development Kit

The “System Interop/Compliance/Debug platform” was set up to test with multiple endpoint and System platforms. This system come with integrated Cadence software for basic system debug without the need for analyzer to perform the analysis, such as LTSSM History, TS1/TS2 transmitted/received with time stamp, Link training phases, Capturing Packet errors details, Capturing PHY TX/RX internal state machine details, ...etc.

Cadence PCIe System Interop/Compliance/Debug Platform

The year 2019 is certainly a "fruitful year" for the PCIe as more Gen 4 products are now available in the market, Gen 5 v1.0 specification got officially ratified, and PCI-SIG's revealing of Gen 6 specification development. We were glad to be part of this APAC tour with the chance to further introduce Cadence’s complete and comprehensive PCIe IP solution.

See you all next year in APAC again!

More Information

For more information on Cadence's PCIe IP offerings, see our PCI Express page.

For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website.

Related Posts

• Blog: Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product
• Blog: PCIe Gen4: It’s Official, We’re Compliant
• Blog: PCIe 3.0 Still Shines While PCIe Keeps Evolving
• Blog: The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

You can't read anything about technology these days without reading about 5G. But before there was 5G, there was 4G. And before that 3G, 2G, and 1G. A 0G even. For the next few Thursdays,...

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Hello,

I am trying to import (in spectre) an spice model of a ceramic capacitor manufactured by Samsung EM. The link that includes the model is here :-

http://weblib.samsungsem.com/mlcc/mlcc-ec.do?partNumber=CL05A156MR6NWR

They proved static spice model and interactive spice model.

I had no problem while including the static model.

However, the interactive model which models voltage and temperature coefficients seems to not be an ordinary spice model. They provide HSPICE, LTSPICE, and PSPICE model files and I failed to include any of them.

Any suggestions ?

Hello,

I am using Virtuoso 6.1.7.

I am performing the parasitic extraction of a MOM cap array of 32 caps. I use Quantus QRC and I enable field solver. I select “QRCFS” for field solver type and “High” for field solver accuracy. The unit MOM cap is horizontally and vertically symmetric. The array looks like the sketch below and there are no other structures except the unit caps:

Rationally speaking, the capacitance values of the unit caps should be symmetric with respect to a vertical symmetry axis that is between cap16 and cap17 (shown with dashed red line). For example,

the capacitance of cap1 should be equal to the capacitance of cap32

the capacitance of cap2 should be equal to the capacitance of cap31

etc. as there are no other structures around the caps that might create some asymmetry.

Nevertheless, what I observe is the following after the parasitic extraction:

As it can be seen, the result is not symmetric contrary to what is expected. I should also add that I do not observe this when I perform parasitic extraction with no filed solver.

Why do I get this result? Is it an artifact resulting from the field solver tool (my conclusion was yes but still it must be verified)? If not, how can something like this happen?

Many thanks in advance.

Best regards,

Can

Several tools can generate power reports based on libraries & stimulus. The issue is what's NEXT?

• Is there any scope to improve power consumption of my design?
• What is the best-case power?
• Pin-point hot spots in my design?
• How to recover wasted power?

And here is the solution in form of Joules RTL Power Exploration. Joules’ framework for power exploration and power implementation/recovery is stimulus based, where analysis is done by Joules and is explored/implemented by user.

Power Exploration capabilities include:

• Efficiency metrics
• Pin point RTL location
• Cross probe to stim
• Centralize all power data

 Do you want to explore more? What is the flow? What commands can be used?

There is a ONE-STOP solution to all these queries in the form of videos on Joules Power Exploration features on https://support.cadence.com (Cadence login required).

Video Links:

How to Analyze Ideal Power Using Joules RTL Power Solution GUI? (Video)

What is Ideal Power Analysis Flow in Joules RTL Power Solution? (Video)

How to Apply Observability Don’t Care (ODC) Technique in Joules? (Video)

How to Debug Wasted Power Using Ideal Power Analyzer Window in Joules GUI? (Video)

Related Resources

Enhance the Joules experience with videos: Joules RTL Power Solution: Video Library

For any questions, general feedback, or future blog topic suggestions, please leave a comment. 

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This Metasploit module exploits a vulnerability that exists due to a lack of input validation when creating a user. Messages for a given user are stored in a directory partially defined by the username. By creating a user with a directory traversal payload as the username, commands can be written to a given directory. To use this module with the cron exploitation method, run the exploit using the given payload, host, and port. After running the exploit, the payload will be executed within 60 seconds. Due to differences in how cron may run in certain Linux operating systems such as Ubuntu, it may be preferable to set the target to Bash Completion as the cron method may not work. If the target is set to Bash completion, start a listener using the given payload, host, and port before running the exploit. After running the exploit, the payload will be executed when a user logs into the system. For this exploitation method, bash completion must be enabled to gain code execution. This exploitation method will leave an Apache James mail object artifact in the /etc/bash_completion.d directory and the malicious user account.