A control device for a hybrid vehicle includes a portion determining whether an engine torque is necessary, a portion controlling a motor to make a motor torque be a target torque, an engine rotation speed control portion controlling an engine output shaft to rotate at a target engine rotation speed for sudden start/reacceleration while the clutch being disengaged after starting the engine and before an actual rotation speed of the engine output shaft exceeds a reference target engine rotation speed in a case where the engine torque is necessary, a control portion engaging the clutch after the actual rotation speed exceeds the reference target engine rotation speed, and a portion controlling the engine so that the engine torque is assumed to be a target torque by canceling the control by the engine rotation speed control portion after the actual rotation speed exceeds the reference target engine rotation speed.

A traction control system in vehicle comprises a detector for detecting a monitored value which changes according to a degree of a drive wheel slip; a condition determiner for determining whether or not the monitored value meets a control start condition and whether or not the monitored value meets a control termination condition; and a controller for executing traction control to reduce a driving power of the drive wheel during a period of time from when the condition determiner determines that the monitored value meets the control start condition until the condition determiner determines that the monitored value meets the control termination condition; the condition determiner being configured to set at least the control start condition variably based on a slip determination factor which changes according to a vehicle state and such that the control start condition changes more greatly according to the vehicle state than the control termination condition.

This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for transmitting and integrating an intellectual property (IP) block with another user's design. The IP developer can design the IP block to include both a secret portion and a public portion. The IP block developer can send or otherwise provide the IP block to another IP user without disclosing the functional description of the secret portion of the IP block. In some implementations, the IP developer provides the public portion to the IP user at the register-transfer-level (RTL) level, as a hardware description language (HDL)-implemented design, or as a synthesizable netlist. In some implementations, the IP developer provides the secret portion of the IP block to the user in the form of programming bits without providing an HDL, RTL, or netlist implementation of the secret portion.

A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias 1 to x−1 in the group of n adjacent through silicon vias, activating n-x switch circuits to connect n-x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.

A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (IP macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise. The circuit section and the clock path are placed on the basis of the increase of the jitter and an allowable jitter value for the circuit section.

A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired characteristics with other preset characteristics of the transformer or the integrated circuit. A first model of the transformer is defined with typical load impedances and simulated having the combined characteristics to determine performance. Results of the simulation are processed to calculate performance with the load impedances specified by the user. The results are further processed to obtain a mathematical model that includes tuning capacitors. The first and subsequent models are modified by drawing on a rule-set of expert knowledge relating to general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion.

A via disposition information acquiring unit acquires via disposition information indicating a disposition of the plurality of first vias (212). A second conductor information acquiring unit acquires second conductor information indicating disposition positions of a plurality of second conductors (232) repeatedly disposed in the second conductor layer (230). A via extracting unit extracts an extraction via with respect to each of the plurality of second conductors (232). The extraction via is each of the first vias (212) overlapping the second conductor (232). A via selecting unit selects a selection via with respect to each of the plurality of second conductors (232). The selection via is each of first vias (212) selected in a predetermined number from the extraction vias. An opening introducing unit introduces a first opening (234) to each of the plurality of second conductors (232). The first opening (234) overlaps the extraction via not selected by the via selecting unit in plan view.

A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist. Vunits may also contain instance statements to monitor or process signals, such as those needed by assertions.

A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.

Disclosed are methods, systems, and articles of manufactures for implementing physical designs by using multiple force models to iteratively morph a layout decomposition. In addition to attractive force model(s) or repulsive force model(s), the physical implementation also uses a containment force model for grouping multiple design blocks or for confining a node of a cell within the boundary of a container. Another aspect is directed at deriving a first force model at the first hierarchical level from a second force model at the second hierarchical level by directly modifying the second model based at least in part on characteristic(s) of the first hierarchical level and of the second hierarchical level. In a design with multiple hierarchies, a cell-based force model is also used to ensure child nodes of a parent cell stay within a close proximity of the parent node of the parent cell.

Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

The present invention is a solid rinse aid composition and methods of making and using the same. Applicants have surprisingly found that the crystal modifier sodium xylene sulfonate (short chain alkyl benzene or alkyl naphthalene sulfonates) at higher percentage can act as a solidification agent. The solid rinse aid composition generally includes an short chain alkyl benzene or alkyl naphthalene sulfonates solidification agent and an effective amount of a surfactant which can include a sheeting agent component, defoamer component and/or association disruption agent. The solid rinse aid composition may be phosphate-free, aminocarboxylate-free, and GRAS if desired.

Resist stripping agents useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits and/or liquid crystals with reduced metal and metal alloy etch rates (particularly copper etch rates and TiW etch rates), are provided with methods for their use. The preferred stripping agents contain low concentrations of resorcinol or a resorcinol derivative, with or without an added copper salt, and with or without an added amine to improve solubility of the copper salt. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods.

A method for softening laundry employs a softening composition, which includes at least one thickener containing a cationic polymer obtained by polymerization: of a cationic monomer;of a monomer with a hydrophobic nature, of formula (I): wherein R1=H or CH3 R2=alkyl chain having at least 16 carbon atomsX═O, m≧5, y=z=0, orX═NH, m≧z≧5, y=0, orX═NH, m≧y≧5, z=0, of a nonionic monomer.

An elongated segmented soap bar is segmented longitudinally into a plurality of soap bodies separate and discrete from one another. Adjacent soap bodies are movable with respect to one another between at least two different configurations including at least an arc configuration with the plurality of soap bodies disposed in an arc. At least one coupler couples the plurality of soap bodies together to allow the adjacent soap bodies to move with respect to one another between the at least two different configurations.

A process for preparing a particle defoamer. The particle defoamer of 55%-75% of a carrier, 15%-35% of a silicone emulsion, 3%-10% of a texturing agent and 2%-10% of a solvent, based on the total weight of the particle defoamer; the process for preparing the particle defoamer is: (1)first adding a carrier A1 into a mixer, and then adding thereto a silicone emulsion B1, and stirring uniformly; (2)adding a carrier component A2 to the mixture obtained in (1), and stirring uniformly; (3)adding a silicone emulsion B2 to the mixture obtained in (2), and, after uniformly stirring, adding the solvent thereto and stirring uniformly; and (4)pelleting and drying by baking the mixture obtained in(3), so as to produce the product.

The invention relates to a non-corrosive degreasing concentrate and ready to use formulation. In particular, non-corrosive compositions capable of removing polymerized grease as effectively as some alkali metal hydroxide (i.e. caustic) based degreasers without requiring the use of personal protective equipment are disclosed.

The present invention relates to an enzyme composition comprising enzyme containing polymer particles, which is useful for detergent compositions, in particular for liquid detergent compositions. In these enzyme containing particles, the particles comprise i) at least one enzyme, and ii) at least one polymer P, which is selected from homo- and copolymers having a C—C-backbone, wherein the C—C-backbone carries carboxylgroups, which may be present in the acidic form or in the neutralized form, and wherein the C—C-backbone comprises hydrophobic repeating units.

The present invention is directed to provide a semiconductor surface treating agent; composition which is capable of stripping an anti-reflection coating layer, a resist layer, and a cured resist layer in the production process of a semiconductor device and the like easily and in a short time, as well as a method for treating a semiconductor surface, comprising that the composition is used. The present invention relates to a semiconductor surface treating agent; composition, comprising [I] a compound generating a fluorine ion in water, [II] a carbon radical generating agent; , [III] water, [IV] an organic solvent, and [V] at least one kind of compound selected from a group consisting of hydroxylamine and a hydroxylamine derivative represented by the general formula [1], as well as a method for treating the semiconductor surface, comprising that the composition is used: (wherein R1 represents a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups; R2 represents a hydrogen atom, a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups).

A granulated foam control composition comprises a foam control agent based on a polydiorganosiloxane fluid, an organic additive of melting point 45″17C to 100° C. comprising a polyol ester, a water-soluble particulate inorganic carrier and a polymer having a net cationic charge. The mean number of carbon atoms in the organo groups of the polydiorganosiloxane fluid is at least 1.3. The foam control agent includes a hydrophobic filler dispersed in the polydiorganosiloxane fluid, and optionally an organosilicone resin. The polyol ester is miscible with the polydiorganosiloxane fluid.

Fault Current Limiters (FCL) provide protection for upstream and/or downstream devices in electric power grids. Conventional FCL require the use of expensive conductors and liquid or gas cryogen handling. Disclosed embodiments describe FCL systems and devices that use lower cost superconductors, require no liquid cryogen, and are fast cycling. These improved FCL can sustain many sequential faults and require less time to clear faults while avoiding the use of liquid cryogen. Disclosed embodiments describe a FCL with a superconductor and cladding cooled to cryogenic temperatures; these are connected in parallel with a second resistor across two nodes in a circuit. According to disclosed embodiments, the resistance of the superconducting components and its sheath in the fault mode are sufficiently high to minimize energy deposition within the cryogenic system, minimizing recovery time. A scheme for intermediate heat storage also is described which allows a useful compromise between conductor length enabled energy minimization and allowable number of sequential faults to enable an overall system design which is affordable, and yet allows conduction cooled (cryogen free) systems which have fast recovery and allows for multiple sequential faults.

A transmission system is provided with a superconductive cable having three phase conductors and a cryostat, surrounding the phase conductors, and encasing a hollow space, for conducting a cooling agent. For the three phase conductors, a common neutral conductor is provided, being made of electrically normally conducting material, carried out as insulating round conductor and placed outside the cryostat and next to it. The cryostat is made of a circumferentially enclosed, thermally insulated sheath.

Provided is a method of manufacturing a superconducting accelerator cavity in which a plurality of half cells having opening portions (equator portions and iris portions) at both ends thereof in an axial direction are placed one after another in the axial direction, contact portions where the corresponding opening portions come into contact with each other are joined by welding, and thus, a superconducting accelerator cavity is manufactured, the half cells to be joined are arranged so that the axial direction thereof extends in a vertical direction; and concave portions that are concave towards an outer side are also formed at inner circumferential surfaces located below the contact portions of the half cells positioned at a bottom; and the contact portions are joined from outside by penetration welding.

A superconductive magnet includes a superconductive coil that is an air-core coil; a pair of bobbin bodies that support the superconductive coil while interposing the superconductive coil therebetween on both sides of a center axial line direction of the superconductive coil; an outer circumference-side binding portion that extends in the center axial line direction on an outer circumferential side of the superconductive coil to bind the pair of bobbin bodies; and a belt-shaped or a wire-shaped inner circumference-side tension imparted portion which extends in the center axial line direction on an inner circumferential side of the superconductive coil to connect the pair of bobbin bodies, and on which tension is imparted in the center axial line direction.

Low-loss superconducting devices and methods for fabricating low loss superconducting devices. For example, superconducting devices, such as superconducting resonator devices, are formed with a (200)-oriented texture titanium nitride (TiN) layer to provide high Q, low loss resonator structures particularly suitable for application to radio-frequency (RF) and/or microwave superconducting resonators, such as coplanar waveguide superconducting resonators. In one aspect, a method of forming a superconducting device includes forming a silicon nitride (SiN) seed layer on a substrate, and forming a (200)-oriented texture titanium nitride (TiN) layer on the SiN seed layer.

A superconductive electrical direct current cable with at least two conductors insulated relative to each other is indicated, where the cable is placed with at least two conductors insulated relative to each other, where the conductors are arranged in a cryostat suitable for guidance of the cooling agent, wherein the cryostat is composed of at least one metal pipe which is surrounded by a circumferentially closed layer with thermally insulating properties. In the cryostat is arranged a strand-shaped carrier composed of insulating material, where the carrier has at least two diametrically oppositely located outwardly open grooves in each of which is arranged one of the conductors. Each conductor is composed of a plurality of superconductive elements.

The present disclosure relates to a superconducting rotating electrical machine and a manufacturing method for a high temperature superconducting film thereof. The superconducting rotating electrical machine includes a stator, and a rotor rotatable with respect to the stator, the rotor having a rotary shaft and a rotor winding. Here, the rotor winding includes tubes disposed on a circumference of the rotary shaft and each forming a passage for a cooling fluid therein, superconducting wires accommodated within the tubes, and a cooling fluid flowing through the inside of the tubes. This configuration may allow for direct heat exchange between the superconducting wires and a refrigerant, resulting in improvement of heat exchange efficiencies of the superconducting wires.

A persistent-mode High Temperature Superconductor (HTS) shim coil is provided having at least one rectangular shaped thin sheet of HTS, wherein the thin sheet of HTS contains a first long portion, a second long portion parallel to first long portion, a first end, and a second end parallel to the first end. The rectangular shaped thin sheet of high-temperature superconductor has a hollow center and forms a continuous loop. In addition, the first end and the second end are folded toward each other forming two rings, and the thin sheet of high-temperature superconductor has a radial build that is less than 5 millimeters (mm) and able to withstand very strong magnetic field ranges of greater than approximately 12 Tesla (T) within a center-portion of a superconducting magnet of a superconducting magnet assembly.

Disclosed are an oxide superconductor tape and a method of manufacturing the oxide superconductor tape capable of improving the length and characteristics of superconductor tape and obtaining stabilized characteristics across the entire length thereof. A Y-class superconductor tape (10), as an oxide superconductor tape, comprises a tape (13) further comprising a tape-shaped non-oriented metallic substrate (11), and a first buffer layer (sheet layer) (12) that is formed by IBAD upon the tape-shaped non-oriented metallic substrate (11); and a second buffer layer (gap layer) (14), further comprising a lateral face portion (14a) that is extended to the lateral faces of the first buffer layer (sheet layer) (12) upon the tape (13) by RTR RF-magnetron sputtering.

A superconductive electromagnet apparatus and a magnetic resonance imaging apparatus including the superconductive electromagnet apparatus are provided. The superconductive electromagnet apparatus includes a thermal anchor, a cryogenic cooling device which cools the thermal anchor, and at least one connecting ring into which the thermal anchor is inserted and a plurality of wires which are connected to the connecting ring.

A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

A method for manufacturing a base material 2 for a superconductive conductor which includes: a conductive bed layer forming process of forming a non-oriented bed layer 24 having conductivity on a substrate 10; and a biaxially oriented layer forming process of forming a biaxially oriented layer 26 on the bed layer 24.

An inductive fault current limiter (1), has a normally conducting primary coil assembly (2) with a multiplicity of turns (3), and a superconducting, short-circuited secondary coil assembly (4). The primary coil assembly (2) and the secondary coil assembly (4) are disposed at least substantially coaxially with respect to each other and at least partially interleaved in each other. The secondary coil assembly (4) has a first coil section (4a) disposed radially inside the turns (3) of the primary coil assembly (2) and a second coil section (4b) disposed radially outside the turns (3) of the primary coil assembly (2). The fault current limiter has an increased inductance ratio.

The invention relates to a high temperature superconducting tape conductor having a flexible metal substrate that comprises at least one intermediate layer disposed on the flexible metal substrate and comprising terraces on the side opposite the flexible metal substrate, wherein a mean width of the terraces is less than 1 μm and a mean height of the terraces is more than 20 nm, and that comprises at least one high temperature superconducting layer disposed on the intermediate layer, which is disposed on the at least one intermediate layer and comprises a layer thickness of more than 3 μm. The ampacity of the high temperature superconducting tape conductor relative to the conductor width is more than 600 A/cm at 77 K.

A superconducting magnet device is configured to include: a refrigerant circulation flowpath in which a refrigerant (R) circulates; a refrigerator for cooling vapor of the refrigerant (R) in the refrigerant circulation flowpath; a superconducting coil cooled by the circulating refrigerant (R); a protective resistor thermally contacting the superconducting coil and having an internal space (S); a high-boiling-point refrigerant supply section for supplying a high-boiling-point refrigerant having a higher boiling point than the refrigerant (R) and frozen by the refrigerant (R) to the internal space (S) in the protective resistor; and a vacuum insulating container for at least accommodating the refrigerant circulation flowpath, the superconducting coil, and the protective resistor.

A superconducting magnet includes a superconducting coil, a heat shield surrounding the superconducting coil, a vacuum chamber accommodating the heat shield, a magnetic shield covering at least a part of the vacuum chamber, and a refrigerating machine fixed to the vacuum chamber to cool the superconducting coil through a heat conducting body. The magnetic shield abuts against said vacuum chamber with an elastic body therebetween to support the vacuum chamber.

A superconducting magnet apparatus includes: a bobbin around which a superconducting coil is wound, the bobbin serving as a protective resistor; a persistent current switch for supplying a persistent current to the superconducting coil; a first closed circuit with the superconducting coil and the persistent current switch connected in series to the coil; and a second closed circuit with the superconducting coil and the bobbin connected in series to the coil.

A layered superconductor device includes multiple layers of a single crystal superconducting material having intermittent layers of superconducting material dispersed in a pattern with a second material such that each layer of the multiple layers a single crystal superconducting material are interconnected via superconducting material, allowing for a continuous current path, and a thickness of the superconducting material never exceeds a first predetermined thickness.

Provided are a substrate for a superconducting compound and a method for manufacturing the substrate which can realize the excellent adhesive strength simultaneously with high orientation of copper. An absorbed material on a surface of a copper foil to which rolling is applied at a draft of 90% or more is removed by applying sputter etching to the surface of the copper foil, sputter etching is applied to a nonmagnetic metal sheet, the copper foil and the metal sheet are bonded to each other by applying a pressure to the copper foil and the metal sheet using reduction rolls, crystals of the copper in the copper foil are oriented by heating a laminated body formed by such bonding, copper is diffused into the metal sheet by heating with a copper diffusion distance of 10 nm or more, and a protective layer is laminated to a surface of the copper foil of the laminated body.

Disclosed is a splicing method of two second-generation ReBCO high temperature superconductor coated conductors (2G ReBCO HTS CCs), in which, with stabilizing layers removed from the two strands of 2G ReBCO HTS CCs through chemical wet etching or plasma dry etching, surfaces of the two high temperature superconducting layers are brought into direct contact with each other and heated in a splicing furnace in a vacuum for micro-melting portions of the surfaces of the high temperature superconducting layers to permit inter-diffusion of ReBCO atoms such that the surfaces of the two superconducting layers can be spliced to each other and oxygenation annealing for recovery of superconductivity which was lost during splicing.

A self-shield open magnetic resonance imaging superconducting magnet comprises five pairs of coils: shim coils, first main magnetic coils, second main magnetic coils, third main magnetic coils, and shielding coils. The five pairs of coils are symmetric about the center. The shim coils are arranged closest to the center point; the first main magnetic coils, the second main magnetic coils, the third main magnetic coils, and the shielding coils are arranged in sequence outside. The first main magnetic coils are connected with reverse current. The second and third main magnetic coils are connected with positive current for providing the main magnetic field strength. The shim coils are connected with positive current for compensating the magnetic field in the central region. The shielding coils are connected with reverse current for creating a magnetic field opposite to the main magnetic field for compensating the stray magnetic field in the space.

A superconducting magnet device and a magnetic resonance imaging system not only avoid the need for costly aluminum alloy formers but also lower quench pressure effectively, have a baffle covering the former and the coil, with a gap between the baffle and the coil.

A superconducting cable is provided. The superconducting cable includes a core part including a former disposed at the center of the core part, one or more superconducting conductive layers with each electric phase disposed at the outside of the former in a radial directions, a insulating layer disposed at the outside of each the conductive layer in a radial direction and a shielding layer disposed at the outermost of the insulating layer; and a cryostat disposed at the outside of the core part in a radial direction with first space being interposed therebetween, having a vacuum part disposed therein and electrically wired to neutral pole (N pole).

A tape-shaped superconducting film-forming substrate is disclosed, which includes a film-forming face for forming a laminate including a superconducting layer thereon, a rear face that is a face at a side opposite to the film-forming face, a pair of end faces connected to the film-forming face and the rear face, and a pair of side faces connected to the film-forming face, the rear face, and the pair of end faces, in which each of the pair of side faces includes a spreading face that spreads toward an outer side in an in-plane direction of the film-forming face from an edge part of the film-forming face toward the rear face side. A superconducting wire and a superconducting wire manufacturing method are also disclosed.

An AC superconducting cable with an insulating layer on the external circumference of a conductor, and wherein: the insulating layer includes a first insulating layer, a second insulating layer and a third insulating layer, from the inside layer to the outside layer; the insulating layer is impregnated with liquid nitrogen; the product of the dielectric constant ∈1 of the first insulating layer and the dielectric loss tangent tan δ1 and the product of the dielectric constant ∈2 of the second insulating layer and the dielectric loss tangent tan δ2 fulfilling the relationship ∈1×tan δ1>∈2×tan δ2; and the product of the dielectric constant ∈2 of the second insulating layer and the dielectric loss tangent tan δ2 and the product of the dielectric constant ∈3 of the third insulating layer and the dielectric loss tangent tan δ3 fulfilling the relationship ∈2×tan δ2

An electrochemical finishing system for super conducting radio frequency (SCRF) cavities including a low viscosity electrolyte solution that is free of hydrofluoric acid, an electrode in contact with the electrolyte solution, the SCRF cavity being spaced apart from the electrode and in contact with the electrolyte solution and a power source including a first electrical lead electrically coupled to the electrode and a second electrical lead electrically coupled to the cavity, the power source being configured to pass an electric current between the electrode and the workpiece, wherein the electric current includes anodic pulses and cathodic pulses, and wherein the cathodic pulses are interposed between at least some of the anodic pulses. The SCRF cavity may be vertically oriented during the finishing process.

A superconductive cable which has a cryostat with two concentric metal pipes where the cryostat has at least a first axial section with a first axial spring constant, and at least a second axial section which has a second axial spring constant which at most is 20%, more preferred at most 10%, of the axial spring constant of the first section.

In a terminal structure of a superconducting cable conductor, a terminal portion of the superconducting cable conductor is connected with a terminal member of a good conductor. The terminal portion includes a superconducting layer disposed on an outer periphery of a central support; and an insulating layer surrounding the superconducting layer. The insulating layer and the superconducting layer are partially removed to expose the central support and the superconducting layer in this order from an end of the superconducting cable conductor. The terminal member includes a metal sleeve which includes a first cylindrical portion whose inner surface is in close contact with an exposed portion of the central support; a second cylindrical portion which is soldered around an exposed portion of the superconducting layer; and a third cylindrical portion into which the insulating layer is inserted.