Groups of phase shifted Pulse Width Modulation signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals.

In an embodiment, a method of generating a pulse-width modulated signal from an input signal includes calculating a finite number of basis functions of a first pulse-width modulated signal based on the input signal, and forming an electronic output based on the calculated finite number of basis functions.

A phase-locked loop double-point modulator may include a frequency divider having a ratio which can be changed by a first modulation signal, and an oscillator, a frequency of which can be changed by a second modulation signal correlated to the first modulation signal. A calibration circuit may be configured, in a calibration mode, to match the gains of the first and second modulation signals based on frequency measurements of the oscillator for two different calibration values of the second modulation signal. The phase-locked double-point modulator may also include an attenuator having a constant ratio greater than 1 and placed in the path of the second modulation signal, and a selector switch configured to be controlled by the calibration circuit to reduce the ratio of the attenuator in the calibration mode.

An amplifier receives an amplitude signal of a polar modulated signal at a base terminal of a transistor and receives a phase modulated carrier signal of the polar modulated signal at the base terminal of the transistor. The amplifier combines the amplitude signal and the phase modulated signal to produce a full complex waveform at a collector terminal of the transistor.

Some embodiments relate to a phase shifter that includes an I/Q phase shifter and at least one LC balun. Compared to conventional phase shifters, phase shifter has primarily only LC components, thereby limiting losses relative to conventional solutions. In one embodiment, for example, a phase shifter shows a large bandwidth at 77 GHz center frequency (e.g., 1 dB amplitude error bandwidth is approximately 40 GHz; 1° phase error bandwidth is about 16.5 GHz). The inductors included in phase shifter, in contrast to the quarter wave transmission lines used in conventional phase shifters, reduces chip area compared with conventional solutions. In some embodiments, an emitter follower helps to provide a relatively constant output that is largely independent of temperature, input power, VCC, manufacturing variation, and so on.

A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.

A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal. The mismatch compensator is configured to receive the signal generator output signal and compensate a frequency mismatch between a desired signal generator output frequency and the signal generator output frequency generated by the oscillator by providing the fine tuning signal for changing the state of the fine tuning circuit of the oscillator and by providing the coarse tuning signal for changing a state of the coarse tuning circuit of the oscillator. The mismatch compensator provides the coarse tuning signal during a guard period defined in the given communication protocol, during which no RF-signals are transmitted by the transmitter or no RF-signals are to be received by the receiver, such that the state of the coarse tuning circuit is changed within the guard period.

A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one resistance-capacitance (RC) detection result, wherein the digital compensation filter includes an RC compensation module; and tuning the digital compensation filter by inputting the RC detection result into the RC compensation module. For example, the RC detection result may correspond to a detected value representing a product of a resistance value and a capacitance value. In another example, the at least one RC detection result may be obtained by performing RC detection on at least a portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein. An associated digital compensation filter and an associated calibration circuit are also provided.

A new coded continuous phase modulation (CPM) scheme is proposed to enhance physical layer performance of the current DVB-RCS standard for a satellite communication system. The proposed CPM scheme uses a phase pulse design and combination of modulation parameters to shape the power spectrum of CPM signal in order to improve resilience to adjacent channel interference (ACI). Additionally, it uses a low complexity binary convolutional codes and S-random bit interleaving. Phase response using the proposed CPM scheme is a weighted average of the conventional rectangular and raised-cosine responses and provides optimum response to minimize frame error rate for a given data rate.

A PWM circuit that can have two refresh rates, including: a first PWM signal generator and a second PWM signal generator; wherein the first PWM signal generator and the second PWM signal generator respectively control refresh rates in two dimensions of an output data generated from a target apparatus. A PWM signal generation method that can have two refresh rates, including: generating a first PWM signal; generating a second PWM signal; and controlling refresh rates in different dimensions of an output data generated from a target apparatus respectively by using the first PWM signal and the second PWM signal.

A digital pulse width modulation controller includes a pulse width modulation controller, a selection unit having at least one selector, a comparison unit having at least one comparator, and a signal conversion unit having at least one digital-to-analog converter. The digital-to-analog converter generates a reference current and/or voltage. The comparator receives the reference current and/or voltage, and performs a comparison operation to generate a comparison signal based on a feedback signal. The selector selects one selection signal to input into the pulse width modulation controller, which receives other parameters set by a user or the system at the same time so as to control characteristics of the digital pulse width modulation signals, thereby improving the electric properties of a loading circuit.

Techniques and mechanisms for configuring logic to implement a signal modulation. In an embodiment, the logic includes a finite impulse response (FIR) module comprising circuitry. The selection circuitry may be operable to concurrently receive signals from latch circuitry of the FIR module and, based on the signals, to select an input group of the selection circuitry and to output a voltage identifier. In another embodiment, configuration logic is operable to set an operational mode which determines a total number of concurrent input signals, received by the FIR module, which the FIR module will use to select an input group for generating an output representing a voltage level.

A circuit includes a switched modulator stage combining an information signal with a square wave carrier to produce a first modulated signal; and a second modulation stage forming additional steps in the first modulated signal to produce a second modulated signal.

A rail-to-rail comparator including a first comparison unit connected to a first terminal and configured to compare differential input signals to differential reference voltages; a second comparison unit connected to a second terminal and configured to compare the differential input signals to the differential reference voltages; and an output unit configured to be driven in response to a clock signal and to generate a complementary output signal according to comparison results of the first and second comparison units.

An irrigation control device having a modulator that modulates data onto an alternating power signal by distorting amplitude of a first leading portion of selected cycles of the alternating power signal, and permit effectively a full amplitude of the alternating power signal on a following portion of the selected cycles, wherein the first leading portion and the following portion are either both on a high side of a cycle or both on a low side of a cycle of the alternating power signal. The irrigation control device further includes an interface configured to couple the modulator to a multi-wire interface coupled to a plurality of irrigation devices to permit the alternating power signal to be applied to the multi-wire interface.

An example PWM includes a driver and a two-way oscillator. The oscillator includes, a first frequency adjust current source, a second frequency adjust current source, a capacitor, a switching reference and a comparator. The capacitor integrates a frequency adjust current by charging with the first frequency adjust current source. The capacitor subsequently integrates a second frequency adjust current by discharging with the second frequency adjust current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to an oscillator signal. The comparator compares the output of the switching reference with a voltage on the capacitor. The first and second frequency adjust current sources vary the first and second frequency adjust currents to vary the frequency of the PWM signal to spread energy of switching harmonics over a frequency band and to reduce EMI.

A time-varying formant is generated at a formant frequency by generating first and second harmonic phase signals having first and second harmonic numbers, respectively, in relation to a modulation frequency. The first and second harmonic phase signals are generated in proportion to a master phase signal, which varies at the modulation frequency, modulo a factor corresponding to their harmonic numbers. First and second sound signals, based on the first and second harmonic phase signals, are frequency modulated to create an arbitrarily rich harmonic spectrum, depending on an FM index. The time-varying formant is generated by generating a time-varying combination of the first and second harmonic sound signals, weighting the first and second harmonic sound signals in accordance with their spectral proximities to the formant frequency. One or more of the harmonic numbers are updated when the time-varying formant frequency passes the frequency of either sound signal.

Methods and apparatus for translating duty cycle information in duty-cycle-modulated signals to higher frequencies or higher data rates. An exemplary duty cycle translator includes a duty cycle evaluator, a high-speed digital counter, and a comparator. The duty cycle evaluator generates a first digital number representing a duty cycle of a low-frequency input duty-cycle-modulated (DCM) signal. The comparator compares the first digital number to a second digital number generated by the high-speed digital counter, and generates, based on the comparison, an output DCM signal having a higher frequency or data rate than the frequency or data rate of the low-frequency input DCM signal but a duty cycle that is substantially the same as the duty cycle of the low-frequency input DCM signal.

A communications transmitter includes a baseband processor configured to generate amplitude, angle, in-phase and quadrature baseband signals and a combination modulator that is configurable to modulate in the polar domain and, alternatively, in the quadrature domain. The combination modulator includes a quadrature modulator and a separate and distinct angle modulator that is configured to serve as a local oscillator for the quadrature modulator. In one embodiment of the invention the combination modulator is configured to modulate in the quadrature domain when the transmitter is operating according to a first communications condition (e.g., first transmit power level or first modulation scheme) and is configured to modulate in the polar domain when the transmitter is operating according to a second communications condition (e.g., second transmit power level or second modulation scheme).

A device for mixing multiple (N) pulse density modulated (PDM) bit streams of a bit rate, the device comprises an input logic, an error accumulation circuit, an error correction circuit and an adder of more than N bits; wherein the device is arranged to output an output PDM bit stream that represents a mixture of the multiple input PDM bit streams; wherein the output PDM bit stream comprises a plurality of output PDM bits, wherein a certain output PDM bit of a plurality of output PDM bits that form the output PDM bit stream is generated during a certain clock cycle; wherein the input logic is arranged to select, during each fraction of the certain clock cycle, a current bit of a selected PDM bit stream, wherein different PDM bit streams are selected during different fragments of the certain clock cycle; wherein the error accumulation circuit is arranged to store intermediate values during a first fraction till a penultimate fraction of the certain clock signal and to store a last value during a last fraction of the certain clock signal.

The present invention relates to a switched-mode power supply apparatus and a corresponding method. For an effective compensation of non-linearities caused by dead-time and voltage drops in the switching power amplifier of the apparatus, an apparatus is proposed comprising a switching power amplifier (14) for amplifying a signal supplied by an external signal source (11) and for supplying a load voltage and/or load current to a load (15), and a control unit (12; 12b) for controlling the switching of said switching power amplifier based on a timing setting, said control unit being adapted for simulating the behavior of the switching power amplifier by predicting the average load voltage and/or load current for at least two, in particular a plurality of, timing settings for a desired load voltage and/or load current based on state information about the present state of the switching power amplifier.

A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result.

Provided is a method for transmitting data in a communication or broadcasting system using a linear block code by generating a codeword by encoding input information data bits, interleaving the codeword; outputting modulation signal-constituting bits by bit-mapping the interleaved codeword using a bit-mapping table predetermined depending on a modulation scheme and a coding rate, outputting a modulation signal by modulating the modulation signal-constituting bits and transmitting the modulation signal via a transmit antenna.

A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

Embodiments of digital high-speed bi-phase modulator and method for bi-phase modulation are generally described herein. In some embodiments, the digital high-speed bi-phase modulator comprises a high-speed digital divider, a high-speed digital multiplexer, and matched signal paths provided between the divider and the multiplexer. The high-speed digital divider is configured to receive a carrier signal and generate complementary output signals. The high-speed digital multiplexer is configured to switch between the complementary output signals and generate a bi-phase modulated output at a carrier frequency (fc) modulated with a bi-phase code. The bi-phase code may be provided to control inputs of the multiplexer.

A radio frequency generator includes a power control module, a frequency control module and a pulse generating module. The power control module is configured to generate a power signal indicating power levels for target states of a power amplifier. The frequency control module is configured to generate a frequency signal indicating frequencies for the target states of the power amplifier. The pulse generating module is configured to (i) supply an output signal to the power amplifier, (ii) recall at least one of a latest power level or a latest frequency for one of the target states of the power amplifier, and (iii) adjust a current power level and a current frequency of the output signal from a first state to a second state based on the power signal, the frequency signal, and at least one of the latest power level and the latest frequency of the power amplifier.

Provided is a method of generating a driving signal for driving a dual mode supply modulator for a power amplifier. The method includes obtaining an envelope of a complex baseband signal to be transmitted, comparing the envelope of the complex signal with a preset threshold value, when a current envelope of the complex signal is the preset threshold value or greater or when there is a result having the preset threshold value or greater in previous N comparisons, outputting a digital board output signal configured with a first logic level through a digital-to-analog converter; and when the current envelope of the complex signal is smaller than the preset threshold value and when there is no result having the preset threshold value or greater in the previous N comparisons, outputting a digital board output signal configured with a second logic level through the digital-to-analog converter.

An apparatus for coding a signal by means of amplitude shift keying comprises a class E amplifier including a switching transistor, to whose gate is supplied a voltage having an operating frequency for operating the class E amplifier. For achieving an amplitude shift keying in the output signal of the class E amplifier, a circuit for switching the operating frequency of the voltage supplied to the gate of the switching transistor, or the resonance frequency of the class E amplifier, between a first value and a second value is provided and in order to switch a deviation degree between the operating frequency and the resonance frequency between a first value and a second value.

In an embodiment, a method of producing a multi-level RF signal includes producing plurality of pulse-width modulated signals based on an input signal. The method further includes driving a corresponding plurality of parallel amplifiers with the plurality of pulse-width modulated signals by setting a parallel amplifier to have a first output impedance when a corresponding pulse-width modulated signal is in an active state and setting the parallel amplifier to have a second output impedance when the corresponding pulse-width is in an inactive state. The method also includes phase shifting the outputs of the plurality of parallel amplifiers, wherein phase shifting transforms the second output impedance into a third impedance that is higher than the second output impedance, and combining the phase shifted outputs.

A transmission device for transmitting a signal in a wireless communication system is provided. The transmission device includes: a serial-to-parallel converter configured to convert an input serial bit stream into a parallel bit stream having three bits; and a phase rotation symbol mapper configured to map the parallel bit stream to a symbol having phase rotation characteristics, wherein when the parallel bit stream includes first to third bits, the phase rotation symbol mapper maps the second and third bits to a complex variable and sequentially maps a real number part and an imaginary number part of the complex variable to the front part and the rear part of a symbol in this order or to the rear part and the front part of the symbol in this order.

According to some embodiments, a method and apparatus are provided to vary a clock signal frequency for a first time period between a lower limit of a range of problematic frequencies and a frequency lower than the lower limit, and vary the clock signal frequency for a second period of time between an upper limit of the range of problematic frequencies and a frequency greater than the upper limit.

A modulation apparatus for a class D switching amplifier is capable of reducing power consumption of an Electro-Migration Interface (EMI) of an output end and a gate driver end in a zero input signal. The modulation apparatus for a class D switching amplifier includes a control unit for detecting and outputting a control signal which is a common signal component of a first modulation signal modulated by using a first input signal and a second modulation signal modulated by using a second input signal; and is characterized by feedback of a first output signal, a second output signal and a common output signal outputted by using the first modulation signal, the second modulation signal and the control signal through an input of the modulation apparatus.

A communications system includes a target receiver having a passband and configured to receive an intended signal within the passband. The communications system also includes a jammer configured to jam the target receiver from receiving the intended signal. The jammer has at least one antenna, a jammer receiver coupled to the at least one antenna, a jammer transmitter coupled to the at least one antenna, and a controller configured to cooperate with the jammer receiver. The controller is configured to detect the intended signal and to generate an interfering signal comprising a continuous phase modulation (CPM) waveform having a constant envelope so that the interfering signal at least partially overlaps the passband of the target receiver.

In a method of transmitting a data stream from a transmitter in a multiple-input-multiple-output (MIMO) wireless communication system, where the transmitter comprises a plurality of transmit antennas, a discrete Fourier transform (DFT) is applied to the data stream to generate a plurality of symbol sequences; symbols of a first symbol sequence from the plurality of symbol sequences are paired with symbols of a second symbol sequence from the plurality of symbol sequences to generate a plurality of symbol pairs, wherein the pairing results in an orphan symbol; a space-time block code (STBC) is applied to the symbol pairs to generate a plurality of sets of STBC symbols, each set of STBC symbols being associated with a corresponding one of the plurality of antennas; a cyclic delay diversity (CDD) operation is applied to the orphan symbol to generate a plurality of CDD symbols, each CDD symbol being associated with a corresponding one of the plurality of antennas; and each one of the antennas transmits the corresponding set of STBC symbols and the corresponding CDD symbol.

In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.

A modulation method is provided. The modulation method includes the steps of receiving multiple sinusoidal signals, obtaining the maximum value of the sinusoidal signals, obtaining the median value of the sinusoidal signals, and obtaining the minimum value of the sinusoidal signals within a period to generate a difference between the maximum value and the minimum value, generating a difference according to an upper limit and a lower limit of a predetermined comparison value, and comparing the two differences to generate an optimized modulation signal.

An ultra-wide band frequency modulator is disclosed. The frequency modulator includes a direct modulation phase lock loop that receives a small component. The frequency modulator also includes a delay module that produces a plurality of delay lines. The frequency modulator further includes an edge selector that receives a large component and the plurality of delay lines.

The present invention relates to a digital modulation method and a corresponding modulator. The modulator comprises a transcoder (110) followed by a FIFO register (120) and a 2-PSK modulator (130). The transcoder codes a binary word of fixed size into a code word of variable size using a transcoding table. The transcoding table codes at least one first binary word, leading to a first number of phase transitions at the output of the modulator, into a second word of size greater than that of the first word, leading to, at the output of the modulator, a second number of phase transitions less than the first number of phase transitions.

The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.

Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

A memristor-based emulator including a memristor circuit for use in digital modulation that includes a first current feedback operational amplifier (CFOA) having multiple terminals in communication with a capacitor Cd and in further communication with a resistor Ri. A second CFOA having multiple terminals is in communication with the first CFOA and is adapted to be in further communication with a voltage vM to provide an input current iM for integration by a capacitor Ci. A nonlinear resistor is in communication with the second CFOA. A third CFOA having multiple terminals is in communication with the nonlinear resistor and is in further communication with the first CFOA and a resistor Rd. The third CFOA and the resistor Rd act as an inverting amplifier associated with the nonlinear resistor to increase a current gain to increase a difference between ON and OFF values of a resistance of a realized memristor.

A method for phase modulation of a carrier signal from a transmitter to a contactless transponder in which data is coded as consecutive symbols, each corresponding to a predefined number of carrier cycles, and in which a symbol time is at least two cycles of the carrier signal includes, at the transmitter, spreading a phase jump of a symbol in relation to a preceding symbol over a first part of the symbol time. The establishment of the phase jump is completed in the first part of the symbol time. The periods of the cycles are constant during a second part of the symbol time.

A PWM signal generating circuit, printer, and PWM signal generating method are described. The PWM signal generating circuit includes: a single counter configured to count values expressed in N bits; and at least one arithmetic device configured to generate a PWM signal, each of the at least one arithmetic device including a pulse width data storage unit for storing N-bit pulse width data representing a pulse width of the PWM signal to be generated, and an adder for calculating a carry value from a most significant bit obtained when adding the count value and the pulse width data. A signal having a level corresponding to the carry value is output at every change in the count value so that the PWM signal having the pulse width of the pulse width data is generated.

A modulator which has a first terminal to receive a carrier signal, a second terminal to receive a first control signal to control a frequency band of the carrier signal and a third terminal to receive a second control signal to control a modulation depth of the carrier signal.

A circuit breaker is provided which can be filled with a quenching gas and which has two contact arrangements, which can be moved relative to one another and along a longitudinal axis of the circuit breaker. The contact arrangements form a arcing contact system and a rated current contact system connected electrically in parallel with it. One of the contact arrangements includes inner rated current contacts and outer rated current contacts of the rated current contact system, where the inner rated current contacts overhang the outer rated current contacts in the direction of the longitudinal axis, and the outer rated current contacts coaxially surround the inner rated current contacts. The circuit breaker has a high current carrying capability as well as a reliable switching-on and -off behavior, such as during and after the occurrence of a short-circuit current in the circuit breaker.

To provide an electric current switching apparatus having a fixed-side electrode unit and a movable-side electrode unit that are arranged to align central axes thereof with each other and to face each other, in which a movable contact provided in the movable-side electrode unit reciprocates on the central axis to contact or separate from a fixed-side contact provided in the fixed-side electrode unit, thereby switching electric current flowing through these electrode units, the electric current switching apparatus including a plurality of permanent magnets that are provided in at least one of the fixed-side electrode unit and the movable-side electrode unit, that have bodies arranged on the central axis to align magnetizing directions thereof with the central axis, and that are arranged to cause same poles of adjacent ones of the permanent magnets to face each other as if butting with each other.

This disclosure relates to methods and systems to reduce high voltage breakdown jitters in liquid dielectric switches. In particular, dielectric liquids have been produced that contain a suspension of nanoparticles and a surfactant to reduce the breakdown jitter. In one embodiment, the suspended nanoparticles are Barium Strontium Titanate (BST) nanoparticles.

An arc chute assembly includes a housing having a first wall, a second wall, and a pair of side walls coupled to the first wall. The walls configured to form an arc area. The housing further having a divider wall coupled to the first wall between the side walls. The divider wall configured to form a first sub-arc area, a second sub-arc area, and an arc plate area. The first sub-arc area and the second sub-arc area are configured to be in flow communication with the arc plate area. The arc chute assembly further comprises a support coupled to the first wall and the side walls, and an arc plate coupled to the support. The arc plate having a body extending between the side walls and over the divider wall.

An electromagnetic actuator comprising a core moving between a latched position and an open position, a permanent magnet, a coil designed to generate a first magnetic control flux to move the core from an open position to a latched position, and a second magnetic control flux designed to facilitate movement of the moving core from the latched position to the open position. The permanent magnet is positioned on the moving core so as to be at least partly outside the fixed magnetic circuit in which the first magnetic control flux flows in the open position, and to be at least partly inside the fixed magnetic circuit used for flow of a magnetic polarization flux of the magnet in the latched position.

In an electrical distribution cabinet a mechanism providing quick, reliable, passive arc blast control has a flue chamber surrounding the likely arc site such as an electrical connection point. The flue chamber provides a flue channel which lengthens the arc and attenuates the current and temperature until the arc is extinguished. Preferably, the flue chamber and channel are formed of opposable open-faced polyhedral structures, one fitting inside the other. The mechanism is particularly suited for draw-out circuit breaker connections in a switch gear cabinet.