A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.

A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be selectively output to the execution unit for use as an operand during the execution of instructions by the execution unit. A PRNG may be coupled to an input of an operand multiplexer that outputs to an operand input of an execution unit so that operands provided by instructions supplied to the execution unit are selectively overridden with pseudorandom numbers generated by the PRNG. Furthermore, overridden operands provided by instructions supplied to the execution unit may be used as seed values for the PRNG.

An independently functioning or centrally controlled wall light switch is configured to operate in normal mode and a Jewish holiday mode wherein the state of the light is fixed, regardless of the user's physical manipulation of the light switch. The control system automatically activates holiday mode by combining a geographically determined Jewish religious clock executed by software and hardware that utilizes the current time, date and geographical location of the apparatus in accordance with the Jewish definition of time and laws for calculating numerous religiously significant shifting daily points in time. The control system further incorporates several energy saving and preference modes by utilizing a particular day's calculated religious points in time in conjunction with holiday behavior patterns common to most Jewish families to provide the user with a greatly simplified means of programming an automatically adjusting on/off light timer and dimming overlay functionality during holiday mode.

Described is a radiation-crosslinkable hotmelt adhesive comprising at least one radiation-crosslinkable poly(meth)acrylate formed to an extent of at least 60% by weight of C1 to C10 alkyl(meth)acrylates and at least one oligo(meth)acrylate which comprises nonacrylic C C double bonds and has a K value of less than or equal to 20. The hotmelt adhesive comprises a photoinitiator which may be present in the form of an additive not attached to the poly(meth)acrylate and/or not attached to the oligo(meth)acrylate, may be incorporated by copolymerization into the poly(meth)acrylate, and/or may be attached to the oligo(meth)acrylate. The hotmelt adhesive can be used for producing adhesive tapes.

The present invention is directed to a coating composition including a (meth)acrylate binder resin, a UV initiator, an organic solvent, and silica particles surface-treated with a (meth)acrylate compound, a coating film including a cured product of the coating composition, and a method of producing the coating film. The present invention makes it possible to provide a coating material having high transmittance and a low level of haze, and excellent scratch resistance and self-healing capabilities.

The present disclosure provides a method of providing an adhesive composition comprising the steps of combining crosslinkable composition including: a) a (meth)acryloyl monomer mixture with the b) photocrosslinking agent mixture, and irradiating with UVC radiation to polymerize and crosslink the composition.

This disclosure provides a network security architecture that permits installation of different software security products as virtual machines (VMs). By relying on a standardized data format and communication structure, a general architecture can be created and used to dynamically build and reconfigure interaction between both similar and dissimilar security products. Use of an integration scheme having defined message types and specified query response framework provides for real-time response and easy adaptation for cross-vendor communication. Examples are provided where an intrusion detection system (IDS) can be used to detect network threats based on distributed threat analytics, passing detected threats to other security products (e.g., products with different capabilities from different vendors) to trigger automatic, dynamically configured communication and reaction. A network security provider using this infrastructure can provide hosted or managed boundary security to a diverse set of clients, each on a customized basis.

A method of interacting with data at a wireless communication device is provided. The wireless communication device has access to a first set of capabilities. Data is received at the wireless communication device via a wireless transmission. The data represents visual content that is viewable via a display device. A graphical user interface, including a delayed action selector, is provided via the display device. An input is received within a limited period of time after displaying the delayed action selector. The input is associated with a command to delay execution of an action with respect to the data until the wireless communication device has access to a second set of capabilities. The action is not supported by the first set of capabilities but is supported by the second set of capabilities. An indication of receipt of the input is provided at the wireless communication device.

Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.

A universal serial bus (USB) dongle device includes a USB interface that receives selection data from a host device that indicates a selection of a first video format from a plurality of available formats. The USB interface also receives an input video signal from the host device in the first video format and a power signal from the host device. An encoding module generates a processed video signal in a second video format based on the input video signal, wherein the first video format differs from the second video format. The USB interface transfers the processed video signal to the host device.

A bus interconnect interfaces a host system to a radio frequency (RF) generator that is coupled to a plasma chamber. The bus interconnect includes a first set of host ports, which are used to provide a power component setting and a frequency component setting to the RF generator. The ports of the first set of host ports are used to receive distinct variables that change over time. The bus interconnect further includes a second set of generator ports used to send a power read back value and a frequency read back value to the host system. The bus interconnect includes a sampler circuit integrated with the host system. The sampler circuit is configured to sample signals at the ports of the first set at selected clock edges to capture operating state data of the plasma chamber and the RF generator.

A method, apparatus, and system for switching from an existing target end device to a next target end device in a multi-expander storage topology by using Fast Context Switching. The method enhances Fast Context Switching by allowing Fast Context Switching to reuse or extend part of an existing connection path to an end device directly attached to a remote expander. The method can include reusing or extending at least a partial path of an established connection between an initiator and the existing target end device for a connection between the initiator and the next target end device, whereby the existing target end device and the next target end device are locally attached to different expanders.

A method for efficient dispatch/completion of a work element within a multi-node data processing system. The method comprises: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ.

Disclosed is an information processing device and a task switching method that can reduce the time required for switching of tasks in a plurality of coprocessors. The information processing device (30) includes a processor core (301); coprocessors (311 to 31n) including operation units (321 to 32n) that perform operation in response to a request from the processor core (301) and operation storage units (331 to 22n) that store the contents of operation of the operation units (321 to 32n), save storage units (351 to 35n) that store the saved contents of operation, a task switching control unit (302) that outputs a save/restore request signal when switching a task on which operation is performed by the coprocessors (311 to 31n), and save/restore units (341 to 34n) that perform at least one of saving of the contents of operation in the operation storage units (331 to 33n) to the save storage units (351 to 35n) and restoration of the contents of operation in the save storage units (351 to 35 n) to the operation storage units (331 to 33n) in response to the save/restore request signal.

A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

A method and apparatus for method of continuously producing 1,1,1,2,3-pentafluoropropane with high yield is provided. The method includes (a) bringing a CoF3-containing cobalt fluoride in a reactor into contact with 3,3,3-trifluoropropene to produce a CoF2-containing cobalt fluoride and 1,1,1,2,3-pentafluoropropane, (b) transferring the CoF2-containing cobalt fluoride in the reactor to a regenerator and bringing the transferred CoF2-containing cobalt fluoride into contact with fluorine gas to regenerate a CoF3-containing cobalt fluoride, and (c) transferring the CoF3-containing cobalt fluoride in the regenerator to the reactor and employing the transferred CoF3-containing cobalt fluoride in Operation (a). Accordingly, the 1,1,1,2,3-pentafluoropropane can be continuously produced with high yield from the 3,3,3-trifluoropropene using a cobalt fluoride (CoF2/CoF3) as a fluid catalyst, thereby improving the reaction stability and readily adjusting the optimum conversion rate and selectivity.

A solvent that reversibly converts from a hydrophobic liquid form to hydrophilic liquid form upon contact with water and a selected trigger, e.g., contact with CO2, is described. The hydrophilic liquid form is readily converted back to the hydrophobic liquid form and water. The hydrophobic liquid is an amidine or amine. The hydrophilic liquid form comprises an amidinium salt or an ammonium salt.

A computing section is provided with a plurality of computing units and correlatively stores entries of configuration information that describes configurations of the plurality of computing units with physical configuration numbers that represent the entries of configuration information and executes a computation in a configuration corresponding to a designated physical configuration number. A status management section designates a physical configuration number corresponding to a status to which the computing section needs to advance the next time for the computing section and outputs the status to which the computing section needs to advance the next time as a logical status number that uniquely identifies the status to which the computing section needs to advance the next time in an object code. A determination section determines whether or not the computing section has stored an entry of configuration information corresponding to the status to which the computing section needs to advance the next time based on the logical status number that is output from the status management section. A rewriting section correlatively stores the entry of the configuration information and a physical configuration number corresponding to the entry of the configuration information in the computing section when the determination section determines that the computing section has not stored the entry of configuration information corresponding to the status to which the computing section needs to advance the next time.

The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.

A technique for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.

A method for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.

A system and method is disclosed for communicating with sensors/loggers in integrated radio frequency identification (RFID) tags. An RFID reader uses a Communicate With Data Logger Command to communicate with a data logger in an RFID tag. The RFID reader performs data access processes using an Index Register and a Data Register of the RFID tag. The RFID reader selects one of (1) Index Read access (2) Index Write access (3) Data Write access (4) Data Read access with parity and (5) Data Read access with cyclic redundancy check (CRC). The RFID tag performs the requested data access and then performs an error detection process.

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.

A system and method may generate unit tests for source code concurrently with API documentation. The system may receive a source code file including several comments sections. Each comments section may include a description of a source code unit such as a class, method, member variable, etc. The description may also correspond to input and output parameters the source code unit. The system and method may parsing the source code file to determine a source code function type corresponding to the unit description and copy the unit description to a unit test stub corresponding to the function type. A developer or another module may then complete the unit test stub to transform each stub into a complete unit test corresponding to the source code unit. Additionally, the system and method may execute the unit test and generate a test result indication for each unit test.

An electronic system and method of operation thereof includes: a control unit for receiving a patterned signal; a recognizer module, coupled to the control unit, for recognizing an unique trigger from the patterned signal; an operation module, coupled to the recognizer module, for detecting an operational mode from the unique trigger; and a change module, coupled to the operation module, for configuring a system state change of a memory sub-system based on the operational mode.

Apparatus and method for assessing odors, comprises an electronic nose, to be applied to an odor and to output a structure identifying the odor; a neural network which maps an extracted structure to a first location on a pre-learned axis of odor pleasantness; and an output for outputting an assessment of an applied odor based on said first location. The assessment may be a prediction of how pleasant a user will consider the odor.

The present invention relates to catalysts and to chemical processes employing such catalysts. The catalysts are preferably used for converting acetic acid to ethanol. The catalyst comprises acidic sites and two or more metals. The catalyst has acidic sites on the surface and the balance favors Lewis acid sites.

A method of operation of a navigation system includes: receiving an origin and a destination; receiving a route keyword for routing between the origin and the destination; identifying a via point matching the route keyword; calculating a keyword group locale based on the via point within a group distance threshold from a keyword group center; and calculating a travel route from the origin to the destination traversing the keyword group locale for displaying on a device.

A method of patterning a plurality of layers of a work piece in a series of writing cycles in one or a plurality of write machines, the workpiece being deviced to have a number of N layers and layers of the workpiece having one or a plurality of boundary condition(s) for pattern position, the method comprising the steps of: determining the boundary conditions of layers 1 to N, calculating deviations due to the boundary conditions and calculating a compensation for the deviation of the first transformation added with the assigned part of the deviation due to the boundary conditions.

In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (βf). In some embodiments, the sensitivity to changes in βf is reduced by varying the charged particle surface dosage for a portion of the pattern. Methods for forming patterns on a surface, and for manufacturing an integrated circuit are also disclosed, in which pattern sensitivity to changes in βf is reduced.

Disclosed are methods, systems, and articles of manufactures for implementing physical designs by using multiple force models to iteratively morph a layout decomposition. In addition to attractive force model(s) or repulsive force model(s), the physical implementation also uses a containment force model for grouping multiple design blocks or for confining a node of a cell within the boundary of a container. Another aspect is directed at deriving a first force model at the first hierarchical level from a second force model at the second hierarchical level by directly modifying the second model based at least in part on characteristic(s) of the first hierarchical level and of the second hierarchical level. In a design with multiple hierarchies, a cell-based force model is also used to ensure child nodes of a parent cell stay within a close proximity of the parent node of the parent cell.

Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

The present invention provides personal care compositions comprising a carrier and a mixture of essential oil components having specific levels of eucalyptol, terpene materials and auxiliary fragrance materials. The compositions herein gentle to skin and have a fragrance and activity similar if the composition were made using the pure extracted essential oil.

Resist stripping agents useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits and/or liquid crystals with reduced metal and metal alloy etch rates (particularly copper etch rates and TiW etch rates), are provided with methods for their use. The preferred stripping agents contain low concentrations of resorcinol or a resorcinol derivative, with or without an added copper salt, and with or without an added amine to improve solubility of the copper salt. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods.

Disclosed is a cleansing composition containing from about 6% to about 20% of at least one nonionic surfactant; from about 3% to about 10% of at least one amphoteric surfactant; from about 2% to about 8% of at least one anionic surfactant; and from about 0.1% to about 5% of at least one cationic conditioning surfactant, cationic conditioning amine, or a mixture thereof; wherein the amount of nonionic surfactant present in the final composition is greater than the amount of the amphoteric surfactant, and the ratio of the nonionic surfactant (a) to anionic surfactant (c) is at least about 1.9 as much as the anionic surfactant, based on the weight percent of each surfactant in the final composition.

An elongated segmented soap bar is segmented longitudinally into a plurality of soap bodies separate and discrete from one another. Adjacent soap bodies are movable with respect to one another between at least two different configurations including at least an arc configuration with the plurality of soap bodies disposed in an arc. At least one coupler couples the plurality of soap bodies together to allow the adjacent soap bodies to move with respect to one another between the at least two different configurations.

A transmission system is provided with a superconductive cable having three phase conductors and a cryostat, surrounding the phase conductors, and encasing a hollow space, for conducting a cooling agent. For the three phase conductors, a common neutral conductor is provided, being made of electrically normally conducting material, carried out as insulating round conductor and placed outside the cryostat and next to it. The cryostat is made of a circumferentially enclosed, thermally insulated sheath.

A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

An inductive fault current limiter (1), has a normally conducting primary coil assembly (2) with a multiplicity of turns (3), and a superconducting, short-circuited secondary coil assembly (4). The primary coil assembly (2) and the secondary coil assembly (4) are disposed at least substantially coaxially with respect to each other and at least partially interleaved in each other. The secondary coil assembly (4) has a first coil section (4a) disposed radially inside the turns (3) of the primary coil assembly (2) and a second coil section (4b) disposed radially outside the turns (3) of the primary coil assembly (2). The fault current limiter has an increased inductance ratio.

A superconductive cable which has a cryostat with two concentric metal pipes where the cryostat has at least a first axial section with a first axial spring constant, and at least a second axial section which has a second axial spring constant which at most is 20%, more preferred at most 10%, of the axial spring constant of the first section.

A magnetic field generation device for a magnetic resonance tomography apparatus has a vacuum container that encloses a magnetic coil made of superconducting material, and a conduit of a pipe system is connected with the magnetic coil so as to conduct heat. The pipe system and the conduit are filled with a coolant that places the magnetic coil in a superconducting state during normal operation of the tomography system. A valve connects the pipe system to the interior of a capture container. In the event of non-normal operation, such as a quench, evaporated coolant passes through the valve into the capture container.

A biometric voice command and control switching device has a microphone assembly for receiving a currently spoken challenge utterance and a reference utterance, and a voice processing circuit for creating electronic signals indicative thereof. The device further includes a memory for storing the electronic signals, and a processor for comparing the electronic signals to determine if there is a match. If there is a match, an interface circuit enables the operable control of the controlled device.

An audio encoder for encoding an audio signal has a first coding branch, the first coding branch comprising a first converter for converting a signal from a time domain into a frequency domain. Furthermore, the audio encoder has a second coding branch comprising a second time/frequency converter. Additionally, a signal analyzer for analyzing the audio signal is provided. The signal analyzer, on the hand, determines whether an audio portion is effective in the encoder output signal as a first encoded signal from the first encoding branch or as a second encoded signal from a second encoding branch. On the other hand, the signal analyzer determines a time/frequency resolution to be applied by the converters when generating the encoded signals. An output interface includes, in addition to the first encoded signal and the second encoded signal, a resolution information identifying the resolution used by the first time/frequency converter and used by the second time/frequency converter.

In one embodiment, a view in a graphical user interface includes a selection area that includes identifiers associated with a plurality of attributes, each of the attributes having a plurality of possible values. The area further includes one or more graphical tools to define filter criteria based at least in part on selected ones of the plurality of possible values of one or more of the attributes. The area further includes one or more switch controls each being associated with a respective one of the one or more of the attributes and indicating presentation criteria including: whether selected ones of the possible values of the respective attribute are to be shown in a report, and a dimension of the report in which to space the selected ones of the possible values from one another if the selected ones of the possible values are to be shown in the report.

To improve the consumer experience with portable electronic devices, a user interface combines the use of capacitive sensors with tactile sensors in an input device. When a user places a finger, stylus, or other input instrument near a given key button, a capacitive sensor causes the display to display temporarily an indication of the function of that key in an enlarged format. The user may then press the associated key button to activate the desired function. In one exemplary embodiment, the capacitive sensor fixes the functionality to the function indicated in the display. In this embodiment, a tactile input applied to any key, whether the correct key, multiple keys, or a single incorrect key, results in activating the function indicated in the display as a result of the capacitive input.

Systems and methods of a 3D mobile user interface with configurable workspace management are disclosed. In one aspect, embodiments of the present disclosure include a method, which may be implemented on a system, of a three-dimensional, multi-layer user interface of a mobile device in a mobile network. User environment may include one or more layers or levels of applications, services, or accounts that are all easily accessible to and navigable by the user. For example, an indicator can be used to access a workspace in 3D representing a category or grouping of services or applications for the user. The user can customize or create a unique, non-mutually exclusive grouping, aggregation, or category of applications, services, accounts, or items. The grouping of indicators can be used to swiftly and efficiently navigate to a desired application, service, account or item, in a 3D-enabled user environment.

Images are analyzed within a 3D environment that is generated based on spatial relationships of the images and that allows users to experience the images in the 3D environment. Image analysis may include ranking images based on user viewing information, such as the number of users who have viewed an image and how long an image was viewed. Image analysis may further include analyzing the spatial density of images within a 3D environment to determine points of user interest.