[IMAGE-1]After having their school year totally disrupted by the coronavirus pandemic, a return to some semblance of normalcy come summer is all many school-age kids and their families are looking forward to. For many, this anticipation includes annual summer camp traditions, from sleep-away adventures on the lake to fun-filled day camps for arts, learning or team sports.…

Coronavirus Family Tree The University of Washington Virology lab, which is testing samples for coronavirus, tweeted last night.…

UPDATE: The Department of Veterans Affairs announced after this article was first published that Spokane Veterans Home residents with COVID-19 would be moved to the Mann-Grandstaff VA Medical Center.…

Welcome to the quarantine.…

THE SHOW WILL GO ON…

ON INLANDER.COM NATION: As meatpacking plants nationwide shutdown due to COVID-19 outbreaks, certain meat products are becoming harder to find at grocery stores and fast-food drive-thrus.…

By Adam Liptak The New York Times Company…

Drink Local For the majority of regional craft breweries, most revenue comes from two avenues: direct-to-consumer sales out of a tasting room and selling beer to local bars and restaurants.…

At every level of America's food system, mandated closures and outbreaks of COVID-19 have interrupted the finely tuned network that normally gets food from farmers and food processors to restaurants, grocery stores and food banks.…

ON INLANDER.COM COVER: While Washington state forges alliances, Idaho battles coronavirus its own way.…

A coalition of immigrant-focused organizations has created the Spokane Relief Fund for Undocumented Immigrants, in order to help families who are unable to access federal aid during the coronavirus shutdowns. The partners sponsoring the work include the Spokane Immigrant Rights Coalition (SIRC), the Hispanic Business and Professional Association, Latinos en Spokane, Mujeres in Action and Raiz.…

Two beloved Spokane-based entertainers are teaming up this weekend for a good cause.…

If you've ever taken a stroll around downtown Spokane's west side, you may have come across Barrister Winery, tucked into a historic brick and timber building alongside the railroad tracks at 1213 Railroad Ave.…

For parents of budding artists and creative types, it can often seem like the arts get short shrift in the K-12 curricula, especially at a time when STEM — short for science, technology, engineering and math — is the buzzword in education and the most visible casualties of school budget cuts are librarians and music teachers.…

POMPEII, THE IMMORTAL CITY is on exhibit at the MAC. But galleries that should be thronged with visitors are empty, at least for a while.…

As soon as state Rep. Marcus Riccelli returned home from Olympia, he jumpstarted a community-wide effort to feed Spokane constituents deeply affected by the COVID-19 crisis.…

Methods and arrangements for analyzing and responding to communications data. Telecom data are input, as are social network data. The telecom data and social network data are analyzed, and action tuples representing opportunistic leads are generated based on the analyzed telecom data and social network data.

A system and method that facilitates urban traffic state detection based on support vector machine (SVM) and multilayer perceptron (MLP) classifiers is provided. Moreover, the SVM and MLP classifiers are fused into a cascaded two-tier classifier that improves the accuracy of the traffic state classification. To further improve the accuracy, the cascaded two-tier classifier (e.g., MLP-SVM), a single SVM classifier and a single MLP classifier are fused to determine a final decision for a traffic state. In addition, fusion strategies are employed during training and implementation phases to compensate for data acquisition and classification errors caused by noise and/or outliers.

Polysubstituted cyclopentadiene compound wherein at least two different substituents are present from the group consisting of linear, branched and cyclic alkyls, aralkyls and alkenyls, and a process for the preparation of a cyclopentadiene compound substituted with at least two different groups chosen from the group consisting of linear, branched, cyclic and aromatic alkyls and alkenyls, characterized in that it comprises the reacting of a halide of a first substituting group in a mixture of the cyclopentadiene compound and an aqueous solution of a base, in which the quantity of the base relative to the cyclopentadiene compound is between 5 and 30 mol/mol, in the presence of a phase transfer catalyst, followed by the addition of a halide of a second or optionally a third substituting group to the reaction mixture.

Disclosed is a process for preparing bridged Group 4 metal complexes containing a neutral diene ligand starting from the corresponding novel, metal diene containing complexes by reaction thereof with the divalent derivative of a bridged bidentate ligand compound. The novel, intermediate metal diene complexes, their formation from tetravalent metal salts and an integrated process combining both process steps are claimed.

A particle-polymer hybrid material can include: a substance having the structure of Formula 1 Z(Y-FP)m, wherein Z is a particle smaller than 1 mm; m is an integer; Y is a linker including a silicon atom linked to the particle; FP is a functionalized polymer having: a first structure derived from a first norbornene compound linked to the Y; and one or more repeating units linked to the first structure, each unit being derived from a second norbornene compound and having a functional group.

The present invention relates to epoxy group-terminated polymers of the formula (I). Said epoxy group-terminated polymers are suited extremely well as impact resistance modifiers, particularly in epoxy resin compositions. They are particularly suited for use in heat-curing epoxy resin adhesives. It has been found that such epoxy resin compositions not only have excellent mechanical properties and high glass transition temperatures, but also above all improved impact resistance properties, both at room temperature and at low temperatures.

A method and user equipment for simultaneous transmission of a first set of information bits and a second set of information bits by a user equipment, either separately encoded utilizing transmit power or rate matching to increase successful decoding of a set of information bits, or jointly encoding using a priori knowledge or bit positioning to increase successful decoding. Also, the use of joint coding where a first set of information bits is encoded first and then encoded with a second set of information bits, and modulation symbol mapping are provided.

Method and apparatus for managing data in a memory. In accordance with some embodiments, a first data object and an associated first ECC data set are generated and stored in a non-volatile (NV) main memory responsive to a first set of data blocks having a selected logical address. A second data object and an associated second ECC data set are generated responsive to receipt of a second set of data blocks having the selected logical address. The second data object and the second ECC data set are subsequently stored in the in the NV main memory responsive to a mismatch between the first ECC data set and the second ECC data set.

A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory that includes a three-dimensional (3D) memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event.

Methods and systems for in-place updating original content stored in a non-volatile storage device and for yielding updated content. Some of the described embodiments illustrate the possibilities for reduction in storage operations, storage blocks, and/or update package size. Some of the described embodiments include the writing of error recovery result(s) such as XOR result(s) which enable the recovery of data in case of an interruption of the update process. In some of the described embodiments, there is re-usage of a protection buffer containing content which is required in the update process.

The present invention discloses a method and apparatus for processing and error correction of a GFP-T superblock, where the 64 bytes of payload data of a first superblock are buffered in the first page of a two-page buffer. The flag byte is buffered in a separate buffer, and a CRC operation is performed in a separate logic element. The result of the CRC operation is checked against a single syndrome table which may indicate single- or multi-bit errors. As the payload data of the first superblock is processed and read out of the first page of the two-page buffer, the payload data of a second superblock is written into the second page of the two-page buffer to be processed and corrected.

A data collection unit obtains physiological data from a subject interface on a subject. The subject interface can be connected to the data collection unit. When the subject interface is connected to the data collection unit, subject interface contacts on the subject interface make contact with data collection unit contacts on the data collection unit. Some of the data collection unit contacts are for communicating physiological data from the subject interface to the data collection unit. Some of the contacts are for powering the data collection unit upon the subject interface being connected to the data collection unit and for powering down the data collection unit upon the subject interface being disconnected from the data collection unit.

The present invention provides a polymerization reactor for producing a super absorbent polymer comprising: a reaction unit; a monomer composition supply unit being connected to the reaction unit and supplying a monomer composition solution containing a monomer, a photoinitiator, and a solvent; an agitating shaft extended in the reaction unit from one end of the reaction unit connected to the monomer composition supply unit to the other end of the reaction unit; a plurality of agitating blades installed around the agitating shaft; and a light irradiation unit providing light to the monomer composition solution furnished from the monomer composition supply unit, and a method of producing super absorbent polymers by using the same.

A crosslinkable curing super-branched polyester and the cured product and the preparation method thereof are disclosed. The super-branched polyester has high refractive index and comprises a compound represented by the following structural formula (I). In the formula (I), HBP is the backbone of the super-branched polyester; both a and b are positive integers; the sum of a and b is less than or equal to n; n is more than or equal to 10 and less than 80. In the super-branched polyester, A is represented by formula (II) and N is represented by formula (III), wherein R is methyl or hydrogen atom; the mole ratio of N relative to the total mole of A and N is more than 30 mol %, and the ratio of the total mole of A and N relative to the product of the total mole of HBP backbone and n is more than 0.5 and less than or equal to 1.

In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal.

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.

An illustrative embodiment of a computer-implemented process for scalable group synthesis receives a group definition, applies a sub-set of conditions to the group definition to form a conditioned group definition, receives a set of entities and populates group membership using the received set of entities and the conditioned group definition, wherein each member responds in the affirmative to the sub-set of conditions.

A liquid crystal compound having a high stability to heat, light and so forth, a high clearing point, a low minimum temperature of a liquid crystal phase, a small viscosity, a suitable optical anisotropy, a large dielectric anisotropy, a suitable elastic constant and an excellent solubility in other liquid crystal compounds, a liquid crystal composition containing the compound, and a liquid crystal display device including the composition. The compound is represented by formula (1): wherein, for example, R1 is fluorine or alkyl having 1 to 10 carbons; ring A1 and ring A2 are 1,4-phenylene, or 1,4-phenylene in which at least one of hydrogen is replaced by fluorine; Z1, Z2 and Z3 are a single bond; L1 and L2 are hydrogen or fluorine; X1 is fluorine or —CF3; and m is 1, and n is 0.

Methods of increasing the solubility of a base in supercritical carbon dioxide include forming a complex of a Lewis acid and the base, and dissolving the complex in supercritical carbon dioxide. The Lewis acid is soluble in supercritical carbon dioxide, and the base is substantially insoluble in supercritical carbon dioxide. Methods for increasing the solubility of water in supercritical carbon dioxide include dissolving an acid or a base in supercritical carbon dioxide to form a solution and dissolving water in the solution. The acid or the base is formulated to interact with water to solubilize the water in the supercritical carbon dioxide. Some compositions include supercritical carbon dioxide, a hydrolysable metallic compound, and at least one of an acid and a base. Some compositions include an alkoxide and at least one of an acid and a base.

A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.

A hypervisor and one or more guest operating systems resident in a data processing system and hosted by the hypervisor are configured to selectively enable or disable branch prediction logic through separate hypervisor-mode and guest-mode instructions. By doing so, different branch prediction strategies may be employed for different operating systems and user applications hosted thereby to provide finer grained optimization of the branch prediction logic for different operating scenarios.

A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.

Embodiments of the present disclosure provide a method and a system for upgrading software. The method includes: a client reports a software upgrade request to a server, wherein the upgrade request carries file information of the local software to be upgraded; the server determines the difference with the latest version software according to the file information of the software to be upgraded in the upgrade request, and generates upgrade instruction information according to the difference and sends it to the client; the client downloads and updates the relevant files and performs the relevant local upgrade operations according to the instructions in received upgrade instruction information. Technical solutions of the present disclosure can save bandwidth resources and reduce the workload for upgrading software.

The present invention relates generally to client-server architectures for allowing generic upload and download functionality between a web application at a server and a client. One exemplary method includes sending a download/upload request to a web application at the server, where the download/upload request specifies at least one file to download/upload; receiving a transmission from the server; parsing the transmission to identify a download/upload command and an associated download/upload manifest, where the download/upload manifest includes executable code that, when executed on the client, will perform the download/upload of the at least one file.

Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each domain is monitored. If a utilization of any of these domains changes, then the number of threads for each of the domains determined for execution may also be adjusted to adapt to the change.

A firmware update method and apparatus of a set-top box for a digital broadcast system is provided. A firmware update method of a set-top box for a digital broadcast system includes determining whether a newly received Code Version Table (CVT) following a public CVT which has been previously received and stored is the public CVT or a filtering CVT; and updating, when the newly received CVG is the filtering CVT, the firmware of the set-top box with a filtering firmware indicated by the filtering CVT.

Traffic information readings corresponding to a vehicle are received, the readings including at least a location. The traffic information readings are compared to information already within a map database, and are used to derive additional map information augmenting or correcting that already within the database, the additional map information subsequently being stored in the database. Additional information that is derived includes the presence of stop signs and traffic lights at intersections, the legality of turns at certain times of day, and the connectedness or non-connectedness of road segments.

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

A via disposition information acquiring unit acquires via disposition information indicating a disposition of the plurality of first vias (212). A second conductor information acquiring unit acquires second conductor information indicating disposition positions of a plurality of second conductors (232) repeatedly disposed in the second conductor layer (230). A via extracting unit extracts an extraction via with respect to each of the plurality of second conductors (232). The extraction via is each of the first vias (212) overlapping the second conductor (232). A via selecting unit selects a selection via with respect to each of the plurality of second conductors (232). The selection via is each of first vias (212) selected in a predetermined number from the extraction vias. An opening introducing unit introduces a first opening (234) to each of the plurality of second conductors (232). The first opening (234) overlaps the extraction via not selected by the via selecting unit in plan view.

A circuit-design support method includes obtaining information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output via the logic circuit; obtaining information concerning a control circuit that has a first flip-flop for scanning and that can control a value of a given signal line by a value set by the first flip-flop; selecting, based on the circuit information, a second flip-flop at an output destination of a signal from the logic circuit, among second flip-flops of the circuit; and generating, based on the control circuit information, information indicating a serial connection of the control circuit between an output source of the signal of the given signal line and the given signal line and a connection of a data input terminal of the first flip-flop and an output terminal of the selected second flip-flop.

Fault Current Limiters (FCL) provide protection for upstream and/or downstream devices in electric power grids. Conventional FCL require the use of expensive conductors and liquid or gas cryogen handling. Disclosed embodiments describe FCL systems and devices that use lower cost superconductors, require no liquid cryogen, and are fast cycling. These improved FCL can sustain many sequential faults and require less time to clear faults while avoiding the use of liquid cryogen. Disclosed embodiments describe a FCL with a superconductor and cladding cooled to cryogenic temperatures; these are connected in parallel with a second resistor across two nodes in a circuit. According to disclosed embodiments, the resistance of the superconducting components and its sheath in the fault mode are sufficiently high to minimize energy deposition within the cryogenic system, minimizing recovery time. A scheme for intermediate heat storage also is described which allows a useful compromise between conductor length enabled energy minimization and allowable number of sequential faults to enable an overall system design which is affordable, and yet allows conduction cooled (cryogen free) systems which have fast recovery and allows for multiple sequential faults.