A wastewater geothermal heat system is supplied with processed wastewater through a drip field in proximity to a thermal array part of a geothermal heat pump system. The wastewater treatment system portion provides a periodic source of treated wastewater. Several sensors and a control system regulate a pump that discharges wastewater from the treatment system and enters a drip field where it is released into the surrounding soil. The dampened soil provides an efficient vehicle to transfer heat into or out of a thermal array which is positioned adjacent to the drip field such that it is in contact with the soil that is dampened by the discharged wastewater.

An ice making system includes a flavored liquid, an ice machine and a refrigerated storage bin. The ice making system continuously produces flavored ice pieces for storage in an ice storage bin. A refrigeration system cools the ice storage bin.

An ice maker has an ice-making vessel having a cylindrical shape, a cooling means, a block ice making mold which is placed inside, and an agitator. The mold includes a main mold body having a plurality of connected L-shaped plates projected radially outward from the central axis; a base plate which is joined to each L-shaped plate, and the top side of the L-shaped plates form a screw insertion part of the mold body such that the agitator fits between the L-shaped plates at a second end of the central axis.

Provided is an environmentally friendly refreezable barrel for chilling a plurality of items in an energy efficient manner that also conserves water. The refreezable barrel includes a cooler body defining an open end and a closed end portion. The cooler body defines a cavity extending from the open end towards the closed end portion. The cavity is configured to receive the plurality of items. A cooling element is disposed within the cooler body and is refreezable to mitigate temperature rise within the cooler body to prolong the melting of ice within the barrel, thereby reducing the overall amount of water used by the barrel. The refreezable barrel also includes a cooler stand defining a recess configured to engage with the closed end portion of the cooler body.

An assembly for cooling heat generating components, such as power electronics, computer processors and other devices. Multiple components may be mounted to a support and cooled by a flow of cooling fluid. A single cooling fluid inlet and outlet may be provided for the support, yet multiple components, including components that have different heat removal requirements may be suitably cooled. One or more manifold elements may provide cooling fluid flow paths that contact a heat transfer surface of a corresponding component to receive heat.

A cooling system for appliances, air conditioners, and other spaces includes a compressor, and a condenser that receives refrigerant from the compressor. The system also includes an evaporator that receives refrigerant from the condenser. Refrigerant received from the condenser flows through an upstream portion of the evaporator. A first portion of the refrigerant flows to the compressor without passing through a downstream portion of the evaporator, and a second portion of the refrigerant from the upstream portion of the condenser flows through the downstream portion of the evaporator after passing through the upstream portion of the evaporator. The second portion of the refrigerant flows to the compressor after passing through the downstream portion of the evaporator. The refrigeration system may be configured to cool an appliance such as a refrigerator and/or freezer, or it may be utilized in air conditioners for buildings, motor vehicles, or other such spaces.

Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

A USB interface to provide power delivery negotiated through a dedicated transmission channel includes a transmitter circuit including a digital-to-analog converter having an output coupled with an input of a transmission filter, a receiver circuit including an analog-to-digital converter having an input coupled with an output of a receiving filter, and a switching circuit configured in an operating mode of the USB interface to connect an output of the transmission filter and an input of the receiving filter to a connection node of the dedicated transmission channel.

A capability determining method for a terminal device, a host, and a system is provided. The capability determining method includes acquiring, by the host, a capability supported by the terminal device. The method also includes determining, by the host according to the capability supported by the terminal device and a capability supported by the host, a capability supported by both the terminal device and the host, and using the capability supported by both the terminal device and the host as an overlapping capability, where the overlapping capability is used by the terminal device to perform capability configuration. The method also includes sending the overlapping capability to the terminal device.

Methods and apparatus for implementing time synchronization across exascale fabrics. A master clock node is coupled to a plurality of slave nodes via a fabric comprising a plurality of fabric switches and a plurality of fabric links, wherein each slave node is connected to the master clock node via a respective clock tree path that traverses at least one fabric switch. The fabric switches are configured to selectively forward master clock time data internally along paths with fixed latencies that bypass the switches' buffers and switch circuitry, which enables the entire clock tree paths to also have fixed latencies. The fixed latency of the clock tree path is determined for each slave node. The local clocks of the slave nodes are then synchronized with the master clock by using master clock time data received by each slave node and the fixed latency of the clock tree path from the master clock node to the slave node that is determined. Techniques for determining a clock rate mismatch between the master clock and a local clock is also provided.

An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

The present application relates to a serial data communications switching device and a method of operating the serial data communications switching device. The serial data communications switching device comprises one host port for connecting to a host device; a plurality of client ports each for connecting to one of a plurality of client devices; an arbiter configured to arbitrate the permission to send a message sequence between the plurality of the client devices according to an arbitration scheme; and a TX flow analyzer adapted to detect a client transmission received at one of the client port from a current client device currently having granted the permission and to instruct the arbiter to maintain the granted permission for the current client device for the ongoing client transmission.

A method of switching an apparatus state of a first apparatus having a first universal serial bus (USB) interface connected via a connecting wire with a second USB interface of a second apparatus is provided. The method may include receiving a state switching instruction, setting a level of a configuration channel (CC) in a USB interface circuit corresponding to the first USB interface from a first high level to a first low level via a logic controller of the first apparatus when the state switching instruction instructs the first apparatus to perform a master-to-slave switch, and setting the level of the CC in the USB interface circuit corresponding to the first USB interface from the first low level to the first high level via the logic controller of the first apparatus when the state switching instruction instructs the first apparatus to perform a slave-to-master switch.

A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support.

A physical layer network interface module (PHY-NIM) adaptation system provides a PHY-NIM device and an attachable media access control (MAC) device. The PHY-NIM device interconnects with the attachable MAC device and the attachable MAC device interconnects to a network appliance to provide at least one of network switch capabilities and MAC device capabilities for use by the network appliance. The PHY-NIM device interconnects directly to the network appliance where the network appliance has at least one of an internal network switch and an internal MAC device in a southbridge input/output (I/O) interface chip of the network appliance.

Examples of adapters for transmitting signals are disclosed. In one example implementation according to aspects of the present disclosure, an adapter may include a first connector communicatively couplable to PCIe port of a computing system via a first plurality of pins and a second connecter communicatively couplable to an electronic device via a second plurality of pins. The first plurality of pins is communicatively coupled to the second plurality of pins. Additionally, signals of a first type are transmittable between the computing system and the electronic device via a first subset of the first and the second pluralities of pins and signals of a second type are transmittable between the computing system and the electronic device via a second subset of the first and the second pluralities of pins. The second subset of the first plurality of pins and the second plurality of pins conforms to the SFF 8639 standard.

A communication system with serial ports for automatically identifying device types and communication protocols and method thereof are described. The communication system and method are capable of automatically identifying the device types and communication protocols of interface devices with different serial device numbers which are disposed in the serial port architecture. Furthermore, the drivers are capable of performing a serial communication based on the serial port architecture for matching the device types and communication protocols correspondingly, thereby reducing the development and manufacturing costs of communication system. Moreover, the user of an application program module only needs to provide the device numbers and data control information without the cooperation of hardware circuits and manufacturing technique of the interface devices to complete the automatic control and monitoring tasks of the interface devices to increase the utilization convenience.

An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.

A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

A technique allows for protecting a PCI device controller from a PCI BDF masquerade attack from Ring-0 and Ring-3 malware. The technique may use Virtualization technologies to create guest virtual machines that can use a hypervisor to allocate ACPI information from ACPI tables to a secure VM and using extended page tables (EPT) and VT-d policies to protect the MMIO memory range during illegal runtime events.

In one aspect, a first device includes a housing, at least one system component housed by the housing, a connector coupled to the housing that engages with a second device for exchange, between the first device and the second device, of at least one of data and power, and a first magnet coupled to the housing. The first magnet is coupled to the housing so that a first pole of the first magnet faces away from the first device to repel a first pole of a second magnet coupled to the second device when the first device is juxtaposed next to the second device in a first orientation relative to the second device.

A storage system includes a first and second control modules (CMs) connected to a client and a storage module over a communication fabric. In response to a data fragment written to the storage module, the first CM is to create a table of contents (TOC) entry in a TOC page maintained in a first storage partition of the storage module, update its FTL map, determine whether the TOC page contains a predetermined number of TOC entries, and in response to determining that the TOC page contains the predetermined number of TOC entries, send a control signal to the second CM via an inter-processor link. In response to the control signal received from the first CM via the inter-processor link, the second CM is to copy the TOC page from the first storage partition to a memory associated with the second CM to allow the second CM to update its FTL map.

A port of a first device includes remote device detection logic to detect, on a link, a remote second device, determine, from a voltage generated at the port, whether the second device is direct current (DC)-coupled or alternating current (AC)-coupled to the link, and select one of first settings or second settings to be applied at the port in communications over the link with the second device based on whether the second device is DC-coupled or AC-coupled.

The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at least one an alternate bus master unit. The CPU, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. The cache invalidation unit generates one or more invalidation requests to the cache memory in response to the alternate bus master unit writing data to the main memory. The cache invalidation unit comprises a page address generator unit to generate page addresses relating to at least one address range and an invalidation request generator unit to generate an invalidation request for each page address. The one or more generated invalidation requests are transmitted by the cache invalidation unit via to the cache memory of the CPU.

A first device is determined as connected to a first one of a plurality of ports of a root complex. Addresses are assigned corresponding to a first hierarchy of devices including the first device. A second device is determined as connected through a mapping portal bridge at a second one of the ports of the root complex, the second device included in another second hierarchy of devices. A mapping table is generated that corresponds to the mapping portal bridge. The mapping table defines a translation between addressing used in a first view of a configuration address space of the system and addressing used in a second view of the configuration address space. The first view includes a view of the root complex and the second view includes a view corresponding to the second hierarchy of devices, the first hierarchy of devices being addressed according to the first view.

Systems, apparatus and methods may provide for creating a communication path through a secure data interface that includes an electronic device control channel between a small form factor computing apparatus such as a compute stick and an external display. A second communication path may be established between a trusted execution environment region of the external display and a trusted execution environment region of the compute stick such that data may be securely transmitted between the compute stick and the external display through the first and second communication paths.

A peripheral interface circuit and a peripheral memory system are provided. The peripheral interface circuit includes an interface sequencer, an input/output controller, a register unit and a data buffer. The interface sequencer receives requests from the input/output controller and accesses the peripheral memory in response to the requests. The data buffer is randomly accessed by address. If target data of the data access request exists in the data buffer, the input/output controller returns data from the data buffer in response to the request; if target data of the data access request does not exist in the data buffer, the input/output controller sends an interface request to the interface sequencer to access the peripheral memory and keeps a copy of at least the target data in the data buffer.

Arbitration circuitry is provided for arbitrating between requests awaiting servicing. The requests require variable numbers of resources and the arbitration circuitry permits the request to be serviced in a different order to the order in which they were received. Checking circuitry prevents a given request other than a oldest request from being serviced when a number of available resources is less than a threshold number of resources. The threshold number is varied based on the number of resources required for at least one other request awaiting servicing.

According to one embodiment, a first control module (CM) of a storage system receives a first request from a client device to read first data stored in a second storage location of a storage module, where the second storage location is associated with a second CM. The first CM includes a first processor and the second CM includes a second processor. The first CM transmits a first control signal the second CM via the inter-processor link to request the second CM to copy the first data from the second storage location to a first memory location associated with the first CM. The first CM initiates a first data transaction to transmit the first data from the first memory location to the client device through a communication fabric without having to go through the second CM.

A semiconductor device includes a plurality of circuits, a general bus configured to be connected to each of the plurality of circuits and to provide a general channel among the plurality of circuits, and a designated bus configured to be connected to a subgroup of circuits from among the plurality of circuits and to provide a designated channel among the subgroup of circuits.

A device and method for communicating, via a memory-mapped communication path, between a host processor and a cellular-communication modem are disclosed. The method includes providing logical channels over the memory-mapped communication path and transporting data organized according to one or more cellular communication protocols over at least one of the logical channels. In addition, the method includes acknowledging when data transfer occurs between the host processor and the cellular-communication modem, issuing commands between the host processor and the cellular-communication modem, and communicating and managing a power state via one or more of the logical channels.

A system and method of conducting precision time management in a universal serial bus system with a retimer. The method includes initiating, from the retimer, a link delay management request on an upstream-facing port of the retimer. The method further includes receiving, at a downstream-facing port of the retimer, a link delay management request and responding to the request received on the downstream-facing port.

A transmission system includes: a master device; and a plurality of slave devices including a first slave device and a second slave device, each of the plurality of slave devices having its own identifier. The master device includes a processor configured to: transmit a control signal of a clock length that the first slave device does not respond to, to the plurality of slave devices at a first timing; and transmit an identifier that identifies the second slave device to the plurality of slave devices at a second timing after the first timing. The second slave device transmits data to the master device when the second slave device receives the control signal and the identifier that identifies the second slave device.

In a system where multiple controllers share a link interface but are not all (1) compatible with the same configuration of the physical layer or (2) using the same clocking, a configuration arbitration subsystem intercepts, organizes, and re-clocks configuration-access requests from the various controller agents. Priorities are assigned according to stored policies. The configuration arbiter grants configuration access to the top-priority agent, synchronizing the agent's message with the arbiter's clock. Lower-priority agents' messages are stored in command queues until they ascend to top priority. Besides preventing timing conflicts and streamlining the coordination of clocks, the configuration arbiter may provide access to physical-layer registers beyond the controllers' built-in capabilities to further optimize configuration.

Described is a computer-implemented method for preventing time out during data transfer to an input/output device. Dummy data is generated and transferred to the input/output device at a time during data transfer, such as when a time out event may occur that would end the data transfer. The transfer of dummy data prevents a time out event from occurring.

A method for using a shared device and a resource sharing system are provided. An arbitrator node sets an initial weight of each of processors based on identification information. The arbitrator node calculates a priority score for each processor based on an initial weight of each of the processors and state diagnostic codes recorded by each processor to establish a priority sequence. When the arbitrator node simultaneously receives a request for requesting an access right of the shared device transmitted by each of two or more processors, the arbitrator node determines one of the processors having the access right of the shared device based on the priority sequence.

A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, and (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node.

A storage system including a hardware module slot, configured to mechanically accommodate a first hardware module. The hardware module slot includes a hardware module data connector configured to electrically interface with the first hardware module inserted into the hardware module slot. The storage system further includes a fabric that includes a first switch. The first switch includes a first protocol interface to the hardware module data connector and is configured to enable first protocol communications between the first hardware module and a second hardware module. The fabric also includes a second switch that includes a second protocol interface to the hardware module data connector and is configured to enable second protocol communications between the first hardware module and the second hardware module.

A method for increasing compatibility of DisplayPort includes: providing a first source device, a second source device, a controller, and a sink device, wherein the first source device is connected to the controller; the first source device transmitting a first image signal to the sink device via a main link for displaying the first image signal on the sink device; causing the controller to disconnect from the first source device and connect to the second source device; executing a simulation process to generate a DC level variation on an auxiliary channel between the controller and the sink device; the second source device transmitting auxiliary data to the sink device; the sink device transmitting link data back to the second source device; and the second source device transmitting a second image signal to the sink device via a second main link for displaying the second image signal on the sink device.

An input/output module is provided for a bus system having a socket, the five contact cups of which each may comprise an electrical contact, and a measuring device for detecting a connector of a four-wire data cable. The measuring device can be configured to detect, when a connector is inserted into the socket, whether the connector comprises four or five electrical contact pins which are each plugged into one of the contact cups and are electrically connected to the respective electrical contact of the contact cups. The measuring device may be configured to close a first and a second switching device only when five electrical contact pins are detected in order to apply a respective supply voltage from two DC voltage supplies to the corresponding plugged contact pins of the connector plugged into the socket via the respective electrical contacts of the contact cups.

An electronic apparatus is provided, the electronic apparatus including: an interface comprising interface circuitry configured to be connectable with at least one of a plurality of sensor modules for sensing an object; a programmable circuit configured to be selectively loaded with at least one of a plurality of hardware images corresponding to the plurality of sensor modules, and to process a sensing signal obtained by sensing the object through the sensor module corresponding to the loaded hardware image; and a controller configured to determine at least one hardware image corresponding to the sensor module connected to the interface from among the plurality of hardware images, and to load the at least one determined hardware image to the programmable circuit.

An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.

Technologies for controlling timing calibration of a dedicated inter-integrated circuit data bus by a primary microcontroller are disclosed. The primary microcontroller performs a data transfer with a secondary integrated circuit using the dedicated inter-integrated circuit data bus, and determines a duration of the data transfer. If the duration is outside of an acceptable range, the primary microcontroller updates one or more data transfer timing parameters so that the duration of future data transfers are closer to the acceptable range.

A flush-mounted fireplace assembly comprising a surround structure configured to encompass a perimeter of an opening in a mounting wall and a bezel structure configured to fit within the outer surround structure. An inner edge of the surround structure and an outer edge of the bezel structure oppose each other and define a gap between inner edge and outer edge such that air can flow through the gap. An outside major surface of the surround structure and an outside major surface of the bezel structure are substantially co-planar with each other and with an exterior surface of the mounting wall.

An air filtration and exhaust system is described. The system comprises a microcontroller, a power supply, and a series of sensors that detect the presence of airborne contaminants such as ultra fine particles, smoke, natural gas and radon gas. In the presence of these airborne contaminants, the system is designed to inactivate and prevent operation of nearby food preparation appliances. Once these contaminants have been safely removed, the operation of these appliances is restored. In addition, the ventilation system may be equipped with a purification subassembly, which safely and efficiently removes such containments from the area. The system may also comprise an alarm that is activatable in the presence of these contaminants.

The present invention provides systems and methods for transferring heat using a variable composition organic heat transfer fluid that remains liquid over a wide operating temperature range useful for solar heating applications. Variable composition heat transfer fluids of the present invention comprise a miscible mixture, optionally a completely miscible mixture, of a high boiling point component selected for its beneficial high temperature physical properties, and a low freezing point component selected for its beneficial low temperature physical properties. In some embodiments, the low freezing point component is removed from the heat transfer fluid as the heat transfer fluid is heated, for example by being removed in the vapor phase, thereby selectively varying the composition and physical properties (e.g., vapor pressure, boiling point, etc.) of the heat transfer fluid as a function of temperature.

Exhaust capture and containment are enhanced by means of automatic or manual side skirts, a sensitive breach detector based on interference effects, a combination of vertical and horizontal edge jets, and/or corner jets that are directed to the center diagonally from corners. Associated control functions are described.

Mounting for a window in an oven appliance is provided so as to allow for thermal expansion during oven use. More particularly, an expansion zone is provided around the window such that, during heating of the window from oven operation, the window is allowed to expand without restraint that could cause cracking or shattering. Space can be allowed for both lateral and longitudinal expansion of the window.

System for establishing a surface shape. The system includes a compliant substrate including the surface and having a reverse side, and a plurality of discrete actuators engaging the reverse side and arranged in a selected pattern to control the surface shape as individual discrete activators are activated. It is preferred that the actuators have multiple discrete stable states of elongation. A particularly preferred embodiment uses actuators that are binary with two stable states of elongation.