A system and method for reordering storage levels in a virtualized environment includes identifying a virtual machine (VM) to be transitioned and determining a new storage level order for the VM. The new storage level order reduces a VM live state during a transition, and accounts for hierarchical shared storage memory and criteria imposed by an application to reduce recovery operations after dynamic resource allocation actions. The new storage level order recommendation is propagated to VMs. The new storage level order applied in the VMs. A different storage-level order is recommended after the transition.

Method and system are provided for managing components of a storage operating environment having a plurality of virtual machines that can access a storage device managed by a storage system. The virtual machines are executed by a host platform that also executes a processor-executable host services module that interfaces with at least a processor-executable plug-in module for providing information regarding the virtual machines and assists in storage related services, for example, replicating the virtual machines.

The technology of the present application provides a networked computer system with at least one workstation and at least one shared resource such as a database. Access to the database by the workstation is managed by a database management system. An access engine reviews job requests for access to the database and allows job requests access to the resource based protocols stored by the system.

The present invention is directed to a combination reactor system for exothermic reactions comprising a trickle-bed reactor and a shell-and-tube reactor. This combination allows the system to efficiently remove heat while also providing the ability to control both the temperature and/or reaction progression. The trickle-bed reactor removes heat efficiently from the system by utilizing latent heat and does not require the use of a cooling or heating medium. The shell-and-tube reactor is used to further progress the reaction and provides a heat exchanger in order to introduce fluid at the desired temperature in the shell-and-tube reactor. Also, additional reactant or reactants and/or other fluids may be introduced to the shell-and-tube section of the reactor under controlled temperature conditions.

Disclosed is a reactor and agitator useful in a high pressure process for making 1-chloro-3,3,3-trifluoropropene (1233zd) from the reaction of 1,1,1,3,3-pentachloropropane (240fa) and HF, wherein the agitator includes one or more of the following design improvements: (a) double mechanical seals with an inert barrier fluid or a single seal;(b) ceramics on the rotating faces of the seal;(c) ceramics on the static faces of seal;(d) wetted o-rings constructed of spring-energized Teflon and PTFE wedge or dynamic o-ring designs; and(e) wetted metal surfaces of the agitator constructed of a corrosion resistant alloy.

A vector data access unit includes data access ordering circuitry, for issuing data access requests indicated by elements of earlier and a later vector instructions, one being a write instruction. An element indicating the next data access for each of the instructions is determined. The next data accesses for the earlier and the later instructions may be reordered. The next data access of the earlier instruction is selected if the position of the earlier instruction's next data element is less than or equal to the position of the later instruction's next data element minus a predetermined value. The next data access of the later instruction may be selected if the position of the earlier instruction's next data element is higher than the position of the later instruction's next data element minus a predetermined value. Thus data accesses from earlier and later instructions are partially interleaved.

Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.

A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction.

A computer-implemented method is provided for evaluating team performance in a product development environment. The method includes receiving a plurality of points of effort made by a team over a plurality of days in a time period, computing a slope associated with a line of best fit through the plurality of points of effort over the plurality of days, computing a deviation of the slope from an ideal slope corresponding to a desired performance rate for the team, and generating a display illustrating at least one of the slope, the ideal slope or the deviation.

The present invention is directed to processes for recovering ethanol obtained from the hydrogenation of acetic acid. Acetic acid is hydrogenated in the presence of a catalyst in a hydrogenation reactor to form a crude ethanol product. The crude ethanol product is separated in one or more columns to recover ethanol. In some embodiments, less than 10 wt. % ethanol is recycled to the hydrogenation reactor.

A process for obtaining an industrially useful 2-chloromethylbenzaldehyde-containing liquid composition at a high yield is provided. More specifically, a process for producing 2-chloromethylbenzaldehyde comprising step (A) of mixing 1-dichloromethyl-2-chloromethylbenzene and sulfuric acid having a concentration of 84.5% by weight or more; and step (B) of mixing a mixture obtained in step (A) and water is provided.

Disclosed herein are processes for alcohol production by reducing ethyl acetate produced by hydrogenating acetic acid in the presence of a suitable catalyst. The product of the acetic acid hydrogenation is fed directly to a decanter to separate the hydrogenation product into an aqueous phase comprising water and ethanol and an organic phase comprising ethyl acetate. The organic phase is reduced with hydrogen in the presence of a catalyst to obtain a crude reaction mixture comprising the alcohol, in particular ethanol, which may be separated from the crude reaction mixture. Thus, ethanol may be produced from acetic acid through an ethyl acetate intermediate without an esterification step. This may reduce the recycle of ethanol in the hydrogenolysis process and improve ethanol productivity.

Dive computers in accordance with embodiments of the invention are disclosed that store information concerning a dive site. The stored information can be accessed during the dive to provide information concerning such things as points of interest and/or hazards. One embodiment of the invention includes a processor, memory connected to the processor, a pressure transducer connected to the processor and configured to measure depth, and a display connected to the processor. In addition, the memory contains factual information concerning a dive site, and the processor is configured to display at least a portion of the stored factual information concerning the dive site via the display.

A method and apparatus for determining a trajectory for a vehicle are disclosed, wherein, the method includes: identifying a starting position (p0) and a desired terminal position (P) for the vehicle; linearly approximating dynamics of the vehicle; and using the starting position (p0), desired terminal position (P), and linear approximation, determining the trajectory for the vehicle. The linear approximation can be constrained by requirements (e.g., specifications) that: (i) an acceleration applied to the vehicle at a point on the trajectory is relatively large when the acceleration acts in a direction that is substantially perpendicular to the velocity of the vehicle; and (ii) an acceleration applied to the vehicle at a point on the trajectory is relatively small when the acceleration acts in a direction that is substantially parallel to the velocity of the vehicle. The vehicle may have a curvature limit.

A method of monitoring an engine coolant system includes modeling the total energy stored within an engine coolant. If an actual temperature of the engine coolant is below a minimum target temperature, the modeled total energy stored within the energy coolant is compared to a maximum stored energy limit to determine if sufficient energy exists within the engine coolant to heat the engine coolant to a temperature equal to or greater than the minimum target temperature. The engine coolant system fails the diagnostic check when the modeled total energy stored within the energy coolant is greater than the maximum stored energy limit, and the minimum target temperature has not been reached.

A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.

A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias 1 to x−1 in the group of n adjacent through silicon vias, activating n-x switch circuits to connect n-x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.

A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (IP macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise. The circuit section and the clock path are placed on the basis of the increase of the jitter and an allowable jitter value for the circuit section.

A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.

Methods and systems are described for placing arithmetic operators on a programmable integrated circuit device (e.g., a PLD). Placement of arithmetic operators of a data flow graph in one of multiple regions (e.g., a region of DSP circuitry blocks or a region of logic fabric circuitry) on the programmable integrated circuitry device may be determined (e.g., randomly). A score related to the performance of the graph (e.g., a score related to data flow graph routing delays or area consumed by the data flow graph) may be determined and this process may be repeated after one of the arithmetic operators of the data flow graph is moved. The placement of arithmetic operators that corresponds to the best value for the score related to the performance of the data flow graph may be stored. Accordingly, more arithmetic operators may be included on a programmable integrated device than in conventional devices.

Aspects of the invention relate to techniques of defect injection for transistor-level fault simulation. A circuit element in a circuit netlist of a circuit is first selected for defect injection. Next, a defect is determined based on whether the selected circuit element is a design-intent circuit element or a parasitic circuit element. After the defect is determined, the defect is injected into the circuit netlist and then the circuit is simulated.

Gemini surfactants of bis-N-alkyl polyether, bis-N-alkenyl polyether, bis-N-cycloalkyl polyether, bis-N-aryl polyether bis-beta or alpha-amino acids or their salts, are produced for use as multifunctional corrosion inhibitors, which protect and prevent corrosion of ferrous metals exposed to acidic, basic and neutral liquids when transporting or storing crude oil and liquid fuels. The surfactants are also used to inhibit corrosion of equipment and pipes used in cooling systems in petroleum and petrochemical equipment. The Gemini surfactants have the structural formula:

A non-aqueous liquid cleaning composition for applicators used for applying non-aqueous hair removal compositions to the skin. The composition includes a solubilizing oil effective for solubilizing the non-aqueous hair removal composition, e.g., mineral oil, and an effective antibacterial amount of an antibacterial agent, e.g., triclosan. The composition may also include fragrances and additional bacteriocides, e.g., phenoxyethanol. When the applicator is contacted with the heated cleaning composition any hair removal composition and bacteria on the applicator are removed therefrom and the applicator is ready for reuse. It is preferred to use surgical stainless steel applicators. Also provided are methods of using these compositions and kits containing, among other items, such compositions and applicators.

The present invention is directed to provide a semiconductor surface treating agent; composition which is capable of stripping an anti-reflection coating layer, a resist layer, and a cured resist layer in the production process of a semiconductor device and the like easily and in a short time, as well as a method for treating a semiconductor surface, comprising that the composition is used. The present invention relates to a semiconductor surface treating agent; composition, comprising [I] a compound generating a fluorine ion in water, [II] a carbon radical generating agent; , [III] water, [IV] an organic solvent, and [V] at least one kind of compound selected from a group consisting of hydroxylamine and a hydroxylamine derivative represented by the general formula [1], as well as a method for treating the semiconductor surface, comprising that the composition is used: (wherein R1 represents a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups; R2 represents a hydrogen atom, a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups).

Provided is a method of manufacturing a superconducting accelerator cavity in which a plurality of half cells having opening portions (equator portions and iris portions) at both ends thereof in an axial direction are placed one after another in the axial direction, contact portions where the corresponding opening portions come into contact with each other are joined by welding, and thus, a superconducting accelerator cavity is manufactured, the half cells to be joined are arranged so that the axial direction thereof extends in a vertical direction; and concave portions that are concave towards an outer side are also formed at inner circumferential surfaces located below the contact portions of the half cells positioned at a bottom; and the contact portions are joined from outside by penetration welding.

Disclosed are an oxide superconductor tape and a method of manufacturing the oxide superconductor tape capable of improving the length and characteristics of superconductor tape and obtaining stabilized characteristics across the entire length thereof. A Y-class superconductor tape (10), as an oxide superconductor tape, comprises a tape (13) further comprising a tape-shaped non-oriented metallic substrate (11), and a first buffer layer (sheet layer) (12) that is formed by IBAD upon the tape-shaped non-oriented metallic substrate (11); and a second buffer layer (gap layer) (14), further comprising a lateral face portion (14a) that is extended to the lateral faces of the first buffer layer (sheet layer) (12) upon the tape (13) by RTR RF-magnetron sputtering.

A method for manufacturing a base material 2 for a superconductive conductor which includes: a conductive bed layer forming process of forming a non-oriented bed layer 24 having conductivity on a substrate 10; and a biaxially oriented layer forming process of forming a biaxially oriented layer 26 on the bed layer 24.

The invention relates to a high temperature superconducting tape conductor having a flexible metal substrate that comprises at least one intermediate layer disposed on the flexible metal substrate and comprising terraces on the side opposite the flexible metal substrate, wherein a mean width of the terraces is less than 1 μm and a mean height of the terraces is more than 20 nm, and that comprises at least one high temperature superconducting layer disposed on the intermediate layer, which is disposed on the at least one intermediate layer and comprises a layer thickness of more than 3 μm. The ampacity of the high temperature superconducting tape conductor relative to the conductor width is more than 600 A/cm at 77 K.

A layered superconductor device includes multiple layers of a single crystal superconducting material having intermittent layers of superconducting material dispersed in a pattern with a second material such that each layer of the multiple layers a single crystal superconducting material are interconnected via superconducting material, allowing for a continuous current path, and a thickness of the superconducting material never exceeds a first predetermined thickness.

Disclosed is a splicing method of two second-generation ReBCO high temperature superconductor coated conductors (2G ReBCO HTS CCs), in which, with stabilizing layers removed from the two strands of 2G ReBCO HTS CCs through chemical wet etching or plasma dry etching, surfaces of the two high temperature superconducting layers are brought into direct contact with each other and heated in a splicing furnace in a vacuum for micro-melting portions of the surfaces of the high temperature superconducting layers to permit inter-diffusion of ReBCO atoms such that the surfaces of the two superconducting layers can be spliced to each other and oxygenation annealing for recovery of superconductivity which was lost during splicing.

In a terminal structure of a superconducting cable conductor, a terminal portion of the superconducting cable conductor is connected with a terminal member of a good conductor. The terminal portion includes a superconducting layer disposed on an outer periphery of a central support; and an insulating layer surrounding the superconducting layer. The insulating layer and the superconducting layer are partially removed to expose the central support and the superconducting layer in this order from an end of the superconducting cable conductor. The terminal member includes a metal sleeve which includes a first cylindrical portion whose inner surface is in close contact with an exposed portion of the central support; a second cylindrical portion which is soldered around an exposed portion of the superconducting layer; and a third cylindrical portion into which the insulating layer is inserted.

A superconducting structure (1) has a plurality of coated conductor tapes (2; 2a-2o), each with a substrate (3) which is one-sided coated with a superconducting film (4), in particular an YBCO film, wherein the superconducting structure (1) provides a superconducting current path along an extension direction (z) of the superconducting structure (1), wherein the coated conductor tapes (2; 2a-2o) provide electrically parallel partial superconducting current paths in the extension direction (z) of the superconducting structure (1), is characterized in that the coated conductor tapes (2; 2a-2o) are superconductively connected among themselves along the extension direction (z) continuously or intermittently. A more stable superconducting structure with which high electric current strengths may be transported is thereby provided.

In order to store excess kinetic energy, an energy storage device and an operating method are described, in which the kinetic energy can be partially converted into electrical energy by a first electric machine using at least two electric machines arranged on a shaft and can be partially converted into additional kinetic energy, such as rotational energy, by a second electric machine. The method for energy storage of excess kinetic energy provides for converting kinetic energy partially into electric energy and partially into additional kinetic energy, such as rotational energy.

A method for producing a superconductive conductor includes: a base material preparation process of preparing a base material having a groove formed on at least one face thereof; a superconducting layer formation process of forming a superconducting layer on a surface of the base material at a side at which the groove is formed; and a cutting process of cutting completely through the base material along the groove.

A layered superconductor device includes multiple layers of a single crystal superconducting material having intermittent layers of superconducting material dispersed in a pattern with a second material such that each layer of the multiple layers a single crystal superconducting material are interconnected via superconducting material, allowing for a continuous current path, and a thickness of the superconducting material never exceeds a first predetermined thickness.

According to one embodiment, an oxide superconductor includes an oriented superconductor layer and an oxide layer. The oriented superconductor layer contains fluorine at 2.0×1016-5.0×1019 atoms/cc and carbon at 1.0×1018-5.0×1020 atoms/cc. The superconductor layer contains in 90% or more a portion oriented along c-axis with an in-plane orientation degree (Δφ) of 10 degrees or less, and contains a LnBa2Cu3O7-x superconductor material (Ln being yttrium or a lanthanoid except cerium, praseodymium, promethium, and lutetium). The oxide layer is provided in contact with a lower surface of the superconductor layer and oriented with an in-plane orientation degree (Δφ) of 10 degrees or less with respect to one crystal axis of the superconductor layer. Area of a portion of the lower surface of the superconductor layer in contact with the oxide layer is 0.3 or less of area of a region directly below the superconductor layer.

An apparatus includes a plurality of applications and an integrator having a voice recognition module configured to identify at least one voice command from a user. The integrator is configured to integrate information from a remote source into at least one of the plurality of applications based on the identified voice command. A method includes analyzing speech from a first user of a first mobile device having a plurality of applications, identifying a voice command based on the analyzed speech using a voice recognition module, and incorporating information from the remote source into at least one of a plurality of applications based on the identified voice command.

A device may include a physical phenomenon detector. The physical phenomenon detector may detect a physical phenomenon related to the device. In response to detecting the physical phenomenon, the device may record audio data that includes speech. The speech may be transcribed with a speech recognition engine. The speech recognition engine may be included in the device, or may be included with a remote computing device with which the device may communicate.

A method of signal processing according to one embodiment includes calculating an envelope of a first signal that is based on a low-frequency portion of a speech signal, calculating an envelope of a second signal that is based on a high-frequency portion of the speech signal, and calculating a plurality of gain factor values according to a time-varying relation between the envelopes of the first and second signal. The method includes attenuating, based on a variation over time of a relation between the envelopes of the first and second signals, at least one of the plurality of gain factor values. In one example, the variation over time of a relation between the envelopes is indicated by at least one distance among the plurality of gain factor values.

A time warp contour calculator for use in an audio signal decoder receives an encoded warp ratio information, derives a sequence of warp ratio values from the encoded warp ratio information, and obtains warp contour node values starting from a time warp contour start value. Ratios between the time warp contour node values and the time warp contour starting value are determined by the warp ratio values. The time warp contour calculator computes a time warp contour node value of a given time warp contour node, on the basis of a product-formation having a ratio between the time warp contour node values of the intermediate time warp contour node and the time warp contour starting value and a ratio between the time warp contour node values of the given time warp contour node and of the intermediate time warp contour node as factors.

An information processing apparatus according to this invention, being capable of communicating with a Web server via a network, receives from the Web server a response to a processing request issued to a Web application of the Web server. The information processing apparatus changes, when screen control information described in a header of the response contains information which designates priority of a screen display by a Web browser of the information processing apparatus, priority of the screen display by the Web browser to the designated priority. When an event to display a screen other than a screen by the Web browser occurs while the Web browser presents a screen display corresponding to the response, the information processing apparatus inhibits an interrupt display by the event in order for the designated priority.

To freely establish a peripheral equipment selection operating environment of excellent operability which can remarkably reduce an operation burden which is applied until construction information of selectable peripheral equipment can be confirmed and can easily confirm the construction information of the selectable peripheral equipment by everyone by a simple operating instruction, a CPU obtains construction information of a printer that is being selected and default setting on the basis of a selection instructing state relative to a selectable printer candidate on a network and allows them to be caption-displayed at a position near the position indicated by a cursor on a printer selection picture plane displayed on a CRT.

A method begins by a router receiving data for storage and interpreting the data to determine whether the data is to be forwarded or error encoded. The method continues with the router obtaining a routing table when the data is to be error encoded. Next, the method continues with the router selecting a routing option from the plurality of routing options and determining error coding dispersal storage function parameters based on the routing option. Next, the method continues with the router encoding the data based on the error coding dispersal storage function parameters to produce a plurality of sets of encoded data slices. Next, the method continues with the router outputting at least some of the encoded data slices of a set of the plurality of sets of encoded data slices to an entry point of the routing option.

Various arrangements for creating and using generic universal resource indicators are presented. To create a generic universal resource indicator, one or more parameters of a universal resource indicator may be identified. An interface that permits a parameter of the one or more parameters to be selected and mapped to a variable may be presented. A selection of the parameter for mapping may be received. An indication of the variable to map to the parameter of the selection may also be received. The generic universal resource indicator having a generic parameter corresponding to the parameter of the selection may be created.