A level-shift circuit that operates stably is provided. The level-shift circuit has a function of boosting a first signal having an amplitude voltage between a first voltage and a second voltage to a second signal having an amplitude voltage between a third voltage and the second voltage. The level-shift circuit includes first to eighth transistors. Gates of the third and seventh transistors are electrically connected to a wiring for transmitting a third signal for controlling the amounts of current flowing into one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the fifth transistor, and one of a source and a drain of the sixth transistor.

An apparatus for facilitating the storage of equipment such as ladders in the upper area, but particularly in the upper area on the outside of emergency vehicles such as trucks which includes a capability of moving the ladder to an extended lower deployed position to facilitate immediate access thereto by emergency workers such as firemen. An outer bracket is connected to an inner housing through a parallel linkage with the inner housing attached to the vehicle and the outer bracket attachable to the equipment. The outer bracket includes a downwardly extendable sliding carriage to facilitate positioning of the equipment at a lower level for aiding in retrieval thereof utilizing a flexible control arm.

An improved apparatus for treating a fire in a multi-floored building where the fire is located on an upper floor vertically displaced from a lower floor from which the fire is treated, and where the upper and lower floors each have a selectively openable environmental access along an external wall of the multi-floored building. The improved apparatus includes a tubular structure having an inlet, an intermediate portion, and an outlet and a bracing system. The bracing system has a frame, a first pivot point, and a second pivot point. The frame provides support against a sturdy surface. The tubular structure is supported on the first pivot point and rotates thereon to elevate or hoist the outlet towards the upper floor environmental access. The tubular structure is further supported on a second pivot point and further rotates thereon to elevate the outlet.

A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.

The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising:first and second conduction electrodes (201, 202);a channel zone (203) arranged between the first and second conduction electrodes;a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222);an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.

A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.

A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.

An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.

A VDC resource request method, user equipment, and a base station, where the VDC resource request method includes sending, by user equipment, a VDC resource request message to a base station when the user equipment needs to request a VDC resource for sending vehicle service information, where the VDC resource request message includes at least one piece of the following information: a VDC resource status list, or travel information of the user equipment, and an available VDC resource is indicated in the VDC resource status list, receiving a VDC resource allocation indication message from the base station, and sending the vehicle service information by using the VDC resource indicated by the VDC resource allocation indication message.

The disclosure relates in some aspects to resource requirement signaling and rate setting for communication on an unlicensed band. The disclosure also relates in some aspects to determining a token arrival rate as a function of traffic arrival information. In some aspects, the disclosed schemes may avoid traffic collisions on a resource and promote access fairness on the resource.

A phase-locked loop circuit and method for providing for compensation for an offset. A phase-locked loop circuit comprises a phase detector, a compensation circuit, a loop filter, and a VCO. The phase detector is coupled to receive a first input signal and a second input signal. The phase detector is configured to output one or more of a plurality of output signals indicative of a difference between the first input signal and the second input signal. The compensation circuit is coupled to receive the output signals and to reduce a voltage offset between the output signals. The compensation circuit is further configured to provide a plurality of compensated output signals. The loop filter is coupled to receive the compensated control signals. The loop filter is configured to output a first control signal. The VCO is coupled to receive the first control signal and to output the second input signal based on the first control signal. A method of operating a phase-locked loop circuit comprises receiving and comparing a first input signal and a second input signal and providing output signals indicative of the comparison. The method compensates for a voltage offset between the output signals and provides compensated output signals indicative of the compensation. The method filters the compensated control signals and provides a control signal indicative of the filtration. The method provides the second input signal based on the first control signal. Lower skew between the input and output may be achieved.

A tractor includes a prime mover, a driven implement selectively engaged with the prime mover, and a switch for selectively engaging and disengaging the driven implement with the prime mover. The switch has three positions including a disengaged position, a momentary position, and an engaged position located between the disengaged position and the momentary position. The prime mover can be started with the switch in the disengaged position. The prime mover can be started with the switch in the engaged position when the switch was previously moved to the momentary position before being moved to the engaged position, such that after operation of the prime mover is stopped, the prime mover can be restarted without changing the position of the switch.

A build up edge monitoring method is provided for performing online real-time detection and suppression of abnormal build up edges of cutters occurred in a CNC manufacturing process. Signal variation analysis and fast Fourier transform are used for analyzing signals and establishing an algorithm of diagnosing build up edges to improve the efficiency and reliability of the cutting abnormality diagnostics. A vibration acceleration signal is captured and filtered to a frequency exceeding 1.1 times of a blade passing frequency, and an occurrence of accumulated chips is determined according to a sudden increase of the vibration acceleration and whether the main vibration frequency of the current vibration signal determined by a fast Fourier transform analysis matches with the frequency of the build up edge characteristic, and a shutdown instruction is issued to a CNC controller to shut down a cutting machine.

An electronic device is provided with an inclination sensor for computing inclination, a control unit which conducts predetermined control based on a value computed by the inclination sensor, a case which has the inclination sensor and the control unit therein, and a suspension portion for suspending the case, and the control unit controls correction of the reference value of the inclination sensor based on a state where the case is suspended by the suspension portion and still.

A planning and guiding method and excavation guiding device correctly implant an artificial tooth root at a predetermined site, perform various excavation processes on a cortical bone section and a spongy bone section by stage-based guidance, and guide eccentric excavation of the cortical bone section and concentric excavation of the spongy bone section according to a bone pattern, such that the artificial tooth root thus implanted is not only positioned at a planned ideal site but also manifests appropriate initial stability.

The present invention is directed to a system of devices and a method for preparing a tooth to receive a restoration. The system includes a dental instrument for removal of portions of a tooth in the mouth of a patent and an overlay for guiding the dental instrument during the step of tooth removal. The overlay is designed for temporary installation into the mouth of the patient to guide the dental instrument to remove tooth material. The overlay has one or more sets of guide walls, with a predetermined configuration capable of contacting one or more guide projections of the dental instrument, and a receptacle capable of receiving and attaching to the dental instrument.

A hydraulic circuit includes a clutch actuator operatively associated with a clutch that may be disposed in a transmission. A hydraulic fluid source supplies pressurized hydraulic fluid for the clutch actuator. To measure the filling rate of the hydraulic actuator, a reference actuator having a predetermined filling rate is disposed in parallel with the hydraulic actuator and in fluid communication with the hydraulic fluid source. If hydraulic pressure associated with the reference actuator does not correspond to the hydraulic pressure associated with the clutch actuator, a compensation valve can appropriately respond by selectively directing hydraulic fluid to or from the clutch actuator. In a further embodiment, the reference actuator and compensation valve may be replaced with an electrohydraulic valve utilizing feedback from the hydraulic pressure present at the inlet of the clutch actuator.

A hydraulic circuit includes a clutch actuator operatively with a clutch that may be disposed in a transmission. A hydraulic fluid source supplies pressurized hydraulic fluid for the clutch actuator. An on-off valve is disposed in fluid communication between the clutch actuator and the hydraulic fluid source; the on-off valve configured to fill the clutch actuator with hydraulic fluid. An accumulator is disposed in parallel with the on-off valve and in fluid communication with the clutch actuator. The accumulator is adapted to receive hydraulic fluid redirected from the clutch actuator and to provide a counter-pressure for modulating the clutch actuator.

A fluid driving device, a motor assembly and a friction clutch thereof are disclosed. The friction clutch includes: a fixing member fixed on a rotary shaft; a connecting member slidable disposed on the rotary shaft, wherein when the rotary shaft starts rotating, an axial distance between the connecting member and the fixing member changes such that a friction force between the fixing member and the connecting member increases until the connecting member rotates synchronously with the fixing member; a loading member slidable disposed on the rotary shaft, the loading member and the connecting member being circumferentially positioned; and a restoring member configured to reduce an amount of change of the axial distance between the fixing member and the connecting member when the rotary shaft stops rotating.

The invention relates to a device for actuating a clutch-controlled transfer case having a two-stage intermediate gearing and a clutch-controlled transfer case that has a two-stage intermediate gearing and that is equipped with such a device. The device comprises: a rotatably driven selector shaft,a drive for rotating the selector shaft,a clutch cam disk, which can be rotated about a clutch cam disk axis by means of the selector shaft, andat least one scissor lever, wherein: one end (06) of at least one scissor lever is guided in a gate provided on the clutch cam disk,the gate has a curved path for each scissor lever, in which curved path the end of the scissor lever associated with the curved path is guided,the curved path winds around the clutch cam disk axis by at least 360°,the curved path has at least one helical segment having a continuously increasing or decreasing distance from the clutch cam disk axis, along which segment one end of a scissor lever guided therein experiences a continuously increasing or decreasing change in deflection with respect to the clutch cam disk axis during a rotation of the clutch cam disk with increasing angle of rotation, andthe clutch cam disk is disposed in such a way that the clutch cam disk can be rotated with respect to the selector shaft between two stops by an angle-of-rotation range such that, by means of rotation of the selector shaft within the angle-of-rotation range situated between said stops, shifting back and forth between the shifting stages of the intermediate gearing occurs, and, by means of rotation of the selector shaft beyond the angle-of-rotation range, the end of the at least one scissor lever experiences a deflection for actuating the clutch while a selected shifting stage is maintained.

The disclosed technology relate to a device and system that include an outdoor power equipment power unit or cart configured to releasably couple a number of different interchangeable attachments or work implements to a common power unit, where some attachments include and/or require operator presence control, while other attachments do not include and/or require operator presence control. The outdoor power equipment power unit includes a power transfer coupling member operatively coupled to the drive shaft and configured to transfer rotational power to the associated attachment; and an operator presence actuation member operatively coupled to the operator presence control member, the operator presence actuation member configured to rotate in response to user actuation of the operator presence control member.

A cleaning composition according to one embodiment includes a surfactant system comprising nonionic surfactant in combination with an anionic surfactant; water present in an amount from 0 to about 40 wt % based on a total weight of the cleaning composition; a solvent system comprising a polyalcohol, the solvent system being present in an amount effective to solubilize the surfactant system in the water; and an enzyme present in an amount of less than about 15 wt %; wherein the cleaning composition is in a form of a continuous phase, wherein the cleaning composition is characterized as exhibiting about a constant cleaning efficacy as measured using test procedure ASTM D4265 when the cleaning composition is added to 69 liters of exterior water in amounts ranging from about 9 to about 22 grams of cleaning composition. Methods for pretreating and cleaning laundry and nontextile surfaces are also presented.

A bluing composition concentrate comprises an aqueous medium and at least one colorant that exhibits a blue or violet shade when deposited onto a textile material. The concentrate can be used to produce a bluing composition, and the bluing composition can be used to treat textile materials in such a way as to decrease the visually-perceived yellow coloration of textile articles that can occur with repeated use and laundering.

The present invention relates to a cosmetic composition for dyeing keratin fibers, in particular human keratin fibers such as the hair, comprising: a) one or more fatty substances; b) one or more surfactants; c) one or more oxidation bases; d) one or more couplers based on 2-hydroxynaphthalene derivatives or particular phenol derivatives, acylaminophenol derivatives or quinoline derivatives; f) one or more basifying agents; e) optionally one or more chemical oxidizing agents; and the fatty substance content representing in total at least 25% by weight relative to the total weight of the formulation. The present invention also relates to a process using this composition, and to a multi-compartment device that is suitable for performing the said process.

A charge pump circuit includes a capacitor, a first switch between the capacitor and a power supply terminal, a second switch between the capacitor and an output terminal, a third switch between the output terminal and the capacitor, a fourth switch between the capacitor and a ground terminal, and a control unit configured to generate control signals for the switches. The control signals include first signals generated during a first period that cause first and third switches to be in an ON state and second and fourth switches to be in an OFF state, second signals generated during a second period that cause first and third switches to be in an OFF state and second and fourth switches to be in an ON state, and third signals generated between the first and second periods, that cause the ON/OFF state of each of the switches to be switched at different times.

A control switch is connected to a power supply voltage and turns on based on a control signal to output a current. A clamp circuit is connected to a load and performs clamp control of the output voltage of the control switch. A current control element conducts or shuts off a current based on the output voltage to be clamp-controlled. A selector switch group includes switches, and performs switching based on a voltage varying with the current control by the current control element, thereby switching between paths for generating an internal power supply. The switch circuit connects or disconnects the coupling between the clamp circuit and the selector switch group.

An active filter device and a circuit arrangement comprising an active filter device are disclosed. In an embodiment the active filter device includes sensor terminals for applying a sensor signal depending on a sensed noise signal, an output terminal for providing a correction signal that is suitable for reducing the noise signal, a signal source adapted for generating a correction signal and a high-pass filter coupled between the sensor terminals and the signal source, wherein the correction signal is generated with a dependence on a high-pass filtered sensor signal.

An SR latch circuit with single gate delay is provided. The circuit has an an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage.

A semiconductor device includes a first transistor and a clamping circuit. The first transistor is arranged to generate an output signal according to a control signal. The clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level.

The present disclosure relates to a delay control circuit arranged for adding delay to a signal. The delay control circuit includes a driver circuit arranged to receive a first signal and to output a second signal. The driver circuit includes a variable load arranged for outputting the second signal by adding delay to the first signal. The delay control circuit also includes a control circuit arranged to receive the first signal and to control the variable load of the driver circuit based on a current state of the first signal and on a control signal indicative of an amount of delay to be added to the first signal in the current state.

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

A load-driving circuit for receiving a supply of power from a power source and driving a load, wherein the load-driving circuit is provided with: a high-side switching element; a low-side switching element; a high-side current detection circuit connected in parallel to the high-side switching element, the high-side current detection circuit detecting a high-side driving current; and a fault detection circuit for detecting the fault state of the load-driving circuit from the output result of the high-side current detection circuit. The high-side current detection circuit is provided with a high-side sense switching circuit operating in response to a gate signal that is different from the high-side switching element, the high-side sense switching circuit comprising a device of the same type as the high-side switching element. The output result of the high-side current detection circuit, the gate signal of the high-side switching element, and the gate signal of the high-side sense switching element are input and the fault states are detected apart from each other when the connection terminal between the load-driving circuit and the load is in a state of short circuit with the positive electrode side of the power source or in a state of short circuit with the negative electrode side of the power source.

A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.

A transmission circuit includes: a first transistor, a first current source, a third transistor. The first transistor has a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit. The first current source is coupled between a gate terminal of the first transistor and a second reference voltage terminal of the transmission circuit. The third transistor has a drain terminal coupled to the first output terminal of the transmission circuit, a source terminal coupled to the second reference voltage terminal of the transmission circuit, and a gate terminal for receiving a first input signal. The first transistor is of a first conducting type, and the second transistor is of a second conducting type different from the first conducting type.

An integrated circuit includes a drive circuit with a first inverter circuit with a first transistor of a first conductivity type and a second transistor of a second conductivity type. The drains of the first and second transistors are connected. An output circuit is provided having a third transistor of the second conductivity with a gate connected to the drains of the first and second transistors. A capacitor is connected between the gate and a drain of the third transistor and has a capacitance greater than 0.5 pF and less than or equal to 3.0 pF. A gate width of the first transistor when divided by a gate width of the third transistor has a value of less than 1/100. The output circuit is configured to output a transmission signal from the drain of the third transistor.

A signal transfer circuit may include a pass gate coupled between first and second nodes; and a control unit suitable for controlling the pass gate to prevent a current flowing from the second node to the first node during turn-on of the pass gate.

A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.

A duty cycle correction circuit may include: a phase mixing section capable of mixing a first integrated signal generated by integrating a positive clock signal, with a first compensation signal generated by differentiating and integrating the positive clock signal and a negative clock signal, respectively, to generate a first phase-mixed signal, and mixing a second integrated signal generated by integrating the negative clock signal, with a second compensation signal generated by integrating and differentiating the positive clock signal and the negative clock signal, respectively, to generate a second phase-mixed signal; and a noise removal section capable of receiving and removing a common mode noise between the first phase-mixed signal and the second phase-mixed signal by adjusting a cross-point therebetween, and outputting first and second duty-corrected clock signals.

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

An apparatus includes an integrated circuit (IC). The IC includes a power controller, which includes a regulator and a controller. The regulator receives a plurality of input voltages and provides a regulated output voltage. The controller controls the regulator to generate the regulated output voltage from the plurality of input voltages. The power controller provides power to a load integrated in the IC from a set of arbitrary input voltages. The set of arbitrary input voltages includes the plurality of input voltages.

An example circuit includes: a slew rate driver configured to provide an output voltage; a first voltage provider configured to provide a first input voltage to the slew rate driver in response to the output voltage being within a first range; and a second voltage provider configured to provide a second input voltage to the slew rate driver in response to the output voltage being within a second range. The slew rate driver is further configured to change the output voltage based at least in part on the first input voltage or the second input voltage.

A circuit suitable for data backup of a logic circuit is provided. The circuit includes first to fourth nodes, a capacitor, first to third transistors, and first and second circuits. Data can be loaded and stored between the circuit and the logic circuit. The first node is electrically connected to a data output terminal of the logic circuit. The second node is electrically connected to a data input terminal of the logic circuit. The capacitor is electrically connected to the third node. The first transistor controls electrical continuity between the first node and the third node. The second transistor controls electrical continuity between the second node and the third node. The third transistor controls electrical continuity between the second node and the fourth node. The first and second circuits have functions of raising gate voltage of the first transistor and raising gate voltage of the second transistor, respectively.

To provide a clock selection circuit capable of reducing clock omission generated when switching from a state of being synchronized with a first clock to a second clock. The clock selection circuit is equipped with a clock detection circuit which detects a first clock to output a detected signal, a switch which outputs the first clock when the detected signal is at a first level and outputs a second clock when the detected signal is at a second level different from the first level, and a one-shot circuit which outputs a one-shot pulse in response to switching of the detected signal from the first level to the second level. The output of the switch and the output of the one-shot circuit are added to be outputted as an output clock.

A clock-signal generator circuit, for generating an output clock signal starting from an input clock signal, includes: a monostable stage having a clock input configured to receive the input clock signal, a control input configured to receive a control signal, and an output configured to supply the output clock signal having a duty cycle variable as a function of the control signal; and a feedback loop, operatively coupled to the monostable stage for generating the control signal as a function of a detected value, and of a desired value, of the duty cycle of the output clock signal.

A device (442) for producing a dynamic reference signal (UREF) for a control circuit for a power semiconductor switch comprises a reference signal generator (442) for providing a dynamic reference signal (UREF), which has a stationary signal level after elapse of a predefined time following a switching process of the power semiconductor switch, a passive charging circuit (450) which is configured to increase a signal level of the dynamic reference signal in reaction to a switching of a control signal of the power semiconductor switch from an OFF state to ON state for at least one part of the predefined time above the stationary signal level, in order to produce the dynamic reference signal and an output (A) for tapping the dynamic reference signal (UREF).

A half-bridge circuit comprises a high supply contact and a low supply contact. A half-bridge output contact is connectable to drive a load and has a high-side between the high supply contact and the half-bridge output contact and a low-side between the half-bridge output contact and the low supply contact. A high-side bidirectional vertical power transistor at the high-side has a source connected to the high supply contact, and a low-side bidirectional vertical power transistor at the low-side, transistor has a source connected to the low supply contact. The high-side bidirectional vertical power transistor and low-side bidirectional vertical power transistor are connected in cascode and share a common drain connected to the half-bridge output contact, and are controllable to alternatingly allow a current flow from the high supply contact to the half-bridge output contact or from the half-bridge output contact to the low supply contact.

A device for controlling a first control gate transistor, including: a second transistor and a third transistor series-connected between a first and a second terminals of application of a power supply voltage, the junction point of these transistors being connected to the gate of the first transistor; a terminal of application of a digital control signal; a circuit for generating an analog signal according to variations of the power supply voltage; and for each of the second and third transistors, a circuit of selection of a control signal of the first transistor representative of said digital signal or of said analog signal.