An alumino-borosilicate glass for the confinement, isolation of a radioactive liquid effluent of medium activity, and a method for treating a radioactive liquid effluent of medium activity, wherein calcination of said effluent is carried out in order to obtain a calcinate, and a vitrification adjuvant is added to said calcinate.

A process according to various approaches includes flushing an intermediate transfer line between a raffinate stream transfer line and a desorbent stream transfer line away from the adsorptive separation chamber to remove residual fluid including desorbent from intermediate transfer line. The process may include directing the residual fluid flushed from the intermediate transfer line to a recycle stream to introduce the residual fluid into the adsorptive separation chamber.

A liquid crystal display module includes a liquid crystal module and a polarizer stacked with each other. The polarizer includes a polarizing layer, a transparent conductive layer and at least two driving-sensing electrodes. The polarizing layer and the transparent conductive layer are stacked with each other. The at least two driving-sensing electrodes are spaced from each other and electrically connected with the transparent conductive layer.

The invention in particular has as an object detecting incompatibility between equipment items of a on-board system. A logic interface associated with one equipment item comprises at least one input while a logic interface associated with another equipment item comprises at least one output. The input and the output are connected. After a minimal data definition level associated with the input and a data definition level associated with the output have been obtained (505), the said minimal data definition level associated with the input is compared (515) with the said data definition level associated with the output. Following this comparison, if the said minimal data definition level associated with the input is lower than the said data definition level associated with the output, an alarm indicating an incompatibility of these two equipment items is generated (545).

Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. Test wrappers may also be configured to test multiple IP blocks comprising a test partition.

A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.

The invention provides a method and apparatus for creating plasma particles and applying the plasma particles to a liquid. Liquid feedstock (e.g., water and/or hydrocarbons mixed with biomass) is pumped through a pipeline; the single-phase stream is then transformed into a biphasic liquid-and-gas stream inside a chamber. The transformation is achieved by transitioning the stream from a high pressure zone to a lower-pressure zone. The pressure drop may occur when the stream further passes through a device for atomizing liquid. Inside the chamber, an electric field is generated with an intensity level that exceeds the threshold of breakdown voltage of the biphasic medium leading to a generation of a plasma state. Furthermore, the invention provides an energy-efficient highly adaptable and versatile method and apparatus for sanitizing water using plasma particles to inactivate biological agents contaminating water.

A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. This encoding scheme allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for an implementation adapted to shift a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.

A communication device includes a storage unit to store quotients and remainders associated with multiplication values obtained by multiplying a specified integer number, which is expressed in a form of (2β+α) where β is a positive integer number and α is a positive integer number other than integral multiples of 2, respectively, the quotients and the remainders being obtained by dividing the multiplication values by 2β, respectively, a first unit to divide a dividend by 2βand calculate a quotient and a remainder, a second unit to obtain a quotient, which corresponds to the remainder from the storage unit, and a third unit to determine that the data length of the packet data is normal, when a combination of the quotient and the remainder calculated by the first unit is in the storage unit.

A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.

Embodiments of the present invention relate to a method and an apparatus for obtaining equipment identification information, where the method includes: detecting, by using a first GPIO port, a first discharging duration for a capacitor to discharge through a resistor to be tested; detecting, by using a second GPIO port, a second discharging duration for the capacitor to discharge through a fixed value resistor; and obtaining a resistance of the resistor to be tested according to the first discharging duration, the second discharging duration, and a resistance of the fixed value resistor. The embodiments of the present invention are capable of increasing identification efficiency of the GPIO port.

A bridge circuit of an embodiment includes: a command transfer portion which is configured by wired logic into which a host controller capable of sending a command that corresponds to each of a plurality of devices inputs the command, and which is configured to transfer the inputted command to the plurality of devices; a command analysis portion which is configured by wired logic, and which is configured to analyze the command from the host controller; and a response reply portion which is configured by wired logic, and which is capable of reading out a response based on an analysis result of the command analysis portion from a register that holds a response corresponding to the command and sending the response to the host controller.

A liquid crystal compound having a high stability to heat, light and so forth, a high clearing point, a low minimum temperature of a liquid crystal phase, a small viscosity, a suitable optical anisotropy, a large dielectric anisotropy, a suitable elastic constant and an excellent solubility in other liquid crystal compounds, a liquid crystal composition containing the compound, and a liquid crystal display device including the composition. The compound is represented by formula (1): wherein, for example, R1 is fluorine or alkyl having 1 to 10 carbons; ring A1 and ring A2 are 1,4-phenylene, or 1,4-phenylene in which at least one of hydrogen is replaced by fluorine; Z1, Z2 and Z3 are a single bond; L1 and L2 are hydrogen or fluorine; X1 is fluorine or —CF3; and m is 1, and n is 0.

To provide a compound, when the compound has both a high clearing point and a low crystallization temperature, having a wide temperature range of a liquid crystal phase and also an excellent solubility in other liquid crystal compounds, and further having general physical properties necessary for the compound, namely, stability to heat, light and so forth, a suitable optical anisotropy and a suitable dielectric anisotropy. A compound is represented by formula (1): wherein, for example, Ra and Rb are alkyl having 1 to 10 carbons; A1, A2, A3 and A4 are 1,4-phenylene; Z1, Z2, Z3 and Z4 are a single bond or alkylene having 1 to 4 carbons; and m, n, q and r are independently 0, 1, or 2, and a sum of m, n, q and r is 1, 2, 3 or 4.

The invention is to provide a new liquid crystal compound having a high clearing point, a good compatibility with other compounds, a small viscosity, and a high stability to heat, light and so forth; compound (1) is provided: R1CF2nR2 (1) wherein, for example, R1 is alkyl having 4 to 10 carbons or —(CH2)2—CH═CH2, R2 is alkyl having 2 to 10 carbons, n is 8, and R1 and R2 are not allowed to be straight-chain alkyl having an identical number of carbons.

The present invention relates to 1,4-diethynylbenzene derivatives having substituents in the 2,3-position (cf. formula I, Claims), to the use thereof for high-frequency components, to liquid-crystalline media comprising the compounds, and to high-frequency components, in particular antennae, especially for the gigahertz range, comprising these media. The liquid-crystalline media serve, for example, for the phase shifting of microwaves for tuneable ‘phased-array’ antennae.

The invention is drawn to fluid concentrate formulations of fatty acid monoethanolamides comprising (a) about 71-76% by weight of one or more C8-C22 fatty acid monoethanolamides, (b) about 15-17% by weight of water, and (c) about 10-12% by weight of one or more hydrotropes, based on the fluid formulation, wherein the fluid formulation is homogeneous, pumpable and color stable at a temperature of less than 55° C. A preferred embodiment is drawn to fluid concentrate formulations of cocamide monoethanolamide (CMEA) consisting of (a) about 71-76% by weight of CMEA, (b) about 15-17% by weight of water, and (c) about 10-12% by weight of glycerol, based on the fluid formulation. Methods of preparing the fluid concentrate formulations mulations are also disclosed. The fluid concentrate formulations of fatty acid monoethanolamides are useful in the preparation of cosmetic and pharmaceutical compositions.

A heat transfer fluid emulsion includes a heat transfer fluid, and liquid droplets dispersed within the heat transfer fluid, where the liquid droplets are substantially immiscible with respect to the heat transfer fluid and have dimensions that are no greater than about 100 nanometers. In addition, the thermal conductivity of the heat transfer fluid emulsion is greater than the thermal conductivity of the heat transfer fluid.

Particular aspects provide compositions comprising an electrokinetically altered oxygenated aqueous fluid, wherein the oxygen in the fluid is present in an amount of at least 25 ppm. In certain aspects, the electrokinetically altered oxygenated aqueous fluid comprises electrokinetically modified or charged oxygen species present in an amount of at least 0.5 ppm. In certain aspects the electrokinetically altered oxygenated aqueous fluid comprises solvated electrons stabilized by molecular oxygen, and wherein the solvated electrons present in an amount of at least 0.01 ppm. In certain aspects, the fluid facilitates oxidation of pyrogallol to purpurogallin in the presence of horseradish peroxidase enzyme (HRP) in an amount above that afforded by a control pressure pot generated or fine-bubble generated aqueous fluid having an equivalent dissolved oxygen level, and wherein there is no hydrogen peroxide, or less than 0.1 ppm of hydrogen peroxide present in the electrokinetic oxygen-enriched aqueous fluid.

A microfluidic method and device for focusing and/or forming discontinuous sections of similar or dissimilar size in a fluid is provided. The device can be fabricated simply from readily-available, inexpensive material using simple techniques.

A processor for processing loop instructions can include an instruction reorder structure and a loop processing controller. The instruction reorder structure is configured to store decoded instructions according to program order and issue the decoded instructions for execution out of program order. The loop processing controller is configured to detect a loop in the decoded instructions stored in the instruction reorder structure and cause the instruction reorder structure to reissue the decoded instructions that form the loop for re-execution.

Augmented processor hardware contains a microcode interpreter. When encrypted microcode is included in a message from a service, the microcode may be passed to the microcode interpreter. Based on decryption and execution of the microcode taking place at the processor hardware, extended functionality may be realized.

In a multiprocessor system, in general, a processor assigned with a larger amount of tasks is apt to perform a larger amount of communication with other processors assigned with tasks, than a processor assigned with a smaller amount of tasks. Thus in order for each processor to be able to perform the routing process efficiently, tasks are assigned such that, when there are a first processor and a second processor, the number of processors each assigned with one or more tasks and directly connected with the second processor being smaller than the number of processors each assigned with one or more tasks and directly connected with the first processor, the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor.

An improved method for program building uses predefined source files and predefined build scripts comprising a sequence of build commands; wherein each build command comprises an origin command line interpretable by an operating system and addressed to at least one compiling tool.

A method for illustrating an aircraft flight plan comprising at least one waypoint on a flight display of a flight deck of an aircraft, where the method may include displaying on the flight display of the flight deck some type of display indicia that indicates the suitability of locations for future waypoints.

In one embodiment, a navigation system provides predictive natural guidance utilizing a mobile landmark based on location data. The location data may be a schedule. A controller receives data of a schedule of a mobile landmark. The location data could be collected in real time or estimated. The mobile landmark may be a vehicle or a celestial body. The controller correlates a route from an origin location to a destination location and the location of the mobile landmark. The controller generates a message based on the correlation. The message is output during presentation of the route and references the mobile landmark.

A navigation system may calculate a route to a destination and output guidance information with an output device to guide a user of the navigation system along the calculated route. If it is determined that a navigation device has left the calculated route, the navigation system may prompt the user asking whether output of guidance information should be suspended. If the output of guidance information should be suspended, the navigation system may suspend the output of guidance information and calculate a new route to the destination while the output of guidance information is suspended. The navigation system may calculate an estimated arrival time at the destination based on the calculated new route and output the estimated arrival time while the output of guidance information is suspended.

An apparatus and method for determining an Absolute Location of an indoor stationary object, the method comprising: receiving a distance between an indoor stationary object and one or more predetermined spots; determining a location of stationary object relative to one of the predetermined spots; receiving an Absolute Location of one of the predetermined spots; determining an Absolute Location of the stationary object; and storing the Absolute Location of the stationary object with description information of the stationary object.

A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.

A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.

Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times.

An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

A method of creating a datasheet includes obtaining integrated circuit data from at least one data source, creating a data structure including the integrated circuit data obtained from the at least one data source, and creating a datasheet using data contained in the data structure. The datasheet is created in a human-readable format.

A circuit-design support method includes obtaining information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output via the logic circuit; obtaining information concerning a control circuit that has a first flip-flop for scanning and that can control a value of a given signal line by a value set by the first flip-flop; selecting, based on the circuit information, a second flip-flop at an output destination of a signal from the logic circuit, among second flip-flops of the circuit; and generating, based on the control circuit information, information indicating a serial connection of the control circuit between an output source of the signal of the given signal line and the given signal line and a connection of a data input terminal of the first flip-flop and an output terminal of the selected second flip-flop.

A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.

A layout-legalizing system modifies a portion of a circuit layout that is selected by a user to generate a modified portion that satisfies a set of technology constraints and a set of design constraints. The system receives as input the set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes. The system also receives a set of design constraints from the user which restricts how objects in the portion of the circuit layout can be modified to satisfy the set of technology constraints. The system can further receive a selection input from the user which identifies the portion of the circuit layout which is to be legalized. The system then modifies the identified portion of the circuit layout to obtain a modified portion which satisfies the set of design constraints and at least a subset of the set of technology constraints.

Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.

A liquid detergent composition containing (A) 10 to 70 mass % of a nonionic surfactant, (B) 1 to 15 mass % of an anionic surfactant, (C) 0.01 to 2 mass % of a protease, and (D) 0.001 to 0.1 mass % of at least one compound selected from the group consisting of thiazole-based compounds and sulfur-containing amino acids.

The use of ferric hydroxycarboxylate as a chelator and builder for cleaning compositions is disclosed. The cleaning composition may be formulated for warewashing, laundering, and for other means of removing soils and includes a ferric hydroxycarboxylate, an alkalinity source and a surfactant system. The cleaning composition has a pH of between about 9 and about 12.

An information processing apparatus configured to display a user interface on a display unit according to screen information acquired from an outside device changes the screen information according to a display attribute set by a user, and if setting of a display attribute of an object included in the screen information is unchangeable, color conversion processing of a specified object included in the screen information is performed and the screen information obtained by executing conversion processing according to the display attribute set by the user with respect to the screen information including the object which has undergone the color conversion processing is displayed.

A phosphazene compound having a vinyl group is manufactured by a reaction between a vinyl compound and a phosphazene compound having a hydroxyl group and added to a resin composition for manufacturing a prepreg or a resin film so as to be applicable to copper-clad laminates and printed circuit boards to thereby achieve satisfactory circuit laminate properties, namely low coefficient of thermal expansion, low dielectric properties, heat resistant, fire resistant, and halogen-free.

In an apparatus for recording and quickly retrieving video signal parts on a magnetic tape, during recording information about the local position of each video signal part is automatically stored in a memory associated with the apparatus, which is designed for storing identifying information for a large number of magnetic tape cassettes. The retrieval of each video signal part on each of the cassettes can be effected substantially without delay in the quick rewind mode of operation.

A method and device for synchronizing the time between at least two integrated circuits (201, 202), which receive the same pulse signal. In the integrated circuits (201, 202) a counter (204, 206) is used to count the number of pulses in the received pulse signal to synchronize the common time between said integrated circuits.

The present invention provides for an electronic device having cryptographic computation means arranged to generate cryptographic data within the device for enhancing security of communications therewith, the device including an onboard power supplying means arranged to provide for the driving of the said cryptographic computational means, and so as to provide a device by way of a manufacturing phase and a post manufacturing phase arranged for distribution and/or marketing of the device, and wherein the step of generating the cryptographic data occurs during the post manufacturing phase.

An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.